COSC 6385 Computer Architecture
Quiz 1
Name:_______________________________________
1.
Pipelining a.
What problem does forwarding solve in pipelining?
February 22 nd
2010
Forwarding transfers data as soon as it is available to other stages of a pipeline that required the according data item.
It helps to reduce data hazards. b.
What problem can exceptions cause when having a pipelined execution of instruction, and how is the problem typically solved?
Exceptions might be raised out-of-order, since different stages of the pipeline can raise exceptions.
In order to raise exceptions in the same order as the instruction, a status vector is carried along with the instruction, and exceptions are only raised in the WB stage. c.
Explain why the MEM and the IF stage of a pipeline can potentially have a structural hazard. What can be done to avoid that hazard?
The MEM and the IF stages both access the main memory, which can lead to a structural hazard if the memory can not handle multiple simultaneous accesses.
To prevent that, one could use dual port or multi-port memory, which support multiple simultaneous requests.
( 1 Pt)
( 2 Pts)
( 2 Pts)
1

COSC 6385 Computer Architecture
Quiz 1
Name:_______________________________________
February 22 nd
2010 d.
What is the advantage of the ‘Predict Branch Not Taken’ approach vs. the
‘Predict Branch Taken’ approach for dealing with branch hazards?
The ‘Predict Branch Not Taken’ approach knows the next instruction to be executed, while the ‘Predict Branch Taken’ approach might not know that and could therefore still lead to a stall/branch hazard.
2.
Caches a.
What is the role of a write buffer in a write through cache?
A write buffer decouples the writing of a data item into the memory from the
CPU, allowing the CPU to continue without having to wait until the write operation really hits the main memory.
( 1 Pt)
( 1 Pt) b.
What is the main limitation of a write buffer? write buffers are small, typically just a small number of entires. This can therefore lead to write buffer saturation for application with high store frequencies.
( 1 Pt)
2

COSC 6385 Computer Architecture
Quiz 1
Name:_______________________________________
February 22 nd
2010 c.
Explain (briefly) the notion of compulsory misses, capacity misses and conflict misses.
– Compulsory Misses: first access to a block cannot be in the cache (cold start misses)
– Capacity Misses: cache cannot contain all blocks required for the execution
– Conflict Misses: cache block has to be discarded because of block replacement strategy d.
Given the following loop sequence. for (i=0; i<8192; i=i+n ) {
( 3 Pt)
} ar[i] = c + ar[i]; with ar being an array of double precision floating point numbers with each element being 8 bytes. No element of the array ar is in the cache before executing this loop. The cache is large enough to hold the entire array ar , and has a cache block size of k = 8 elements (or 64 bytes). Determine the number of cache misses and the cache miss rate for the variable ar in this loop for various loop increment value of n , namely n=1, n=4, and n=16
For n=1: no of misses: 8192/8 no of accesses: 2 * 8192 miss rate = 8192/8 / 2*8192 = 1/16
For n=4: no. of misses: 8192/8 ( we still need to load all cache lines) no. of accesses: 2 * 8192/4 = 4096 miss rate = 8192/8 / 8192/2 = ¼
For n=16: no. of misses: 8192/16 ( since every element will be a miss) no. of accesses: 2 * 8192/16 miss rate = 8192/16 / 8192/8 = ½
3

COSC 6385 Computer Architecture
Quiz 1
Name:_______________________________________
February 22 nd
2010 e.
In the following, we would like to analyze the impact of the cache block size k on the results obtained in part d. Determine the number of cache misses and the cache miss rate for the ar in this loop as a function of the block sizes k for a fixed loop increment n=1. no. of misses: 8192/k no of accesses: 2 * 8192 miss rate: 8192/k / 2*8192 = 1/2k f.
For n>k , what is the miss rate for the variable ar in the loop above if n>k distinct elements of the loop are in different cache blocks: Thus: no. of misses: 8192/n no of accesses: 2* 8192/n miss rate (k,n) = 1/2 g.
For n<k , give the miss rate for the variable ar in the loop above.
( 2 Pts)
( 1 Pt)
( 1 Pt) if n< k , all cache lines still have to be loaded once: Thus no. of misses: 8192/k no. of accesses: 2 * 8192/n miss rate (k,n) = 2 * 8192/n / 8192/k = n/2k
4