Cadence® Rapid Adoption Kits
Rapid Adoption Kits demonstrate how users can use their tools in their flows to improve
productivity and to maximize the benefits of their tools. These packages can contain
workshop databases or demo designs, instructional documents, overview presentations,
deeper dive Application Notes and videos.
How to access the Rapid Adoption Kits?
To get started with the Rapid Adoption Kits, use the following link:
http://support.cadence.com/wps/myportal/cos/COSHome/resources/RapidAdoptionKits/
Please note that a support.cadence.com account is required to access this content.
There you will find all the related material, including documentation, videos and project files.
The Rapid Adoption Kits are split into three sections:
Silicon-Package-Board Design
These Rapid Adoption Kits are related to the Silicon-Package-Board Design using Allegro tools.
Virtuoso® Custom IC and Sign-off Flow
These Rapid Adoption Kits are related to the Virtuoso Custom IC and Sign-off Flow using Virtuoso
Schematic Editor (VSE), Multi-Mode Simulation (MMSIM), Virtuoso Layout Suite (VLS), Physical
Verification System (PVS) and other Virtuoso products.
Encounter® Digital Implementation (EDI) System and Sign-off Flow
These Rapid Adoption Kits are related to the Encounter Digital Implementation (EDI) System and Signoff Flow using Encounter Digital Implementation (EDI) System, Encounter Timing System (ETS) and
Encounter Power System (EPS).
Synthesis, Test and Verification flow
These Rapid Adoption Kits are related to the Synthesis, Test and Verification flow using RTL Compiler,
Encounter Test, Conformal, and Incisive products.
You can find more information about the available Rapid Adoption Kits below on
this document, or on the landing page.
Last updated: 30/04/2013
Silicon-Package-Board Design
These Rapid Adoption Kits are related to the Silicon-Package-Board Design using
Allegro tools.
PCIe Design-In-Kit: Lite
This kit in intended to help start with high speed SerDes Channel analysis using Allegro PCB SI. The lite
kit also provides an introduction to the Back Channel Analysis on PCIe 3.0 technology. This kit includes
the ami models for PCIe 3.0 transmitter and receiver.
DDR Kit: Lite
DDR3 Design-In Kit (lite version) DDR3 SDRAM (double-data-rate) is a type of dynamic random access
memory with a high bandwidth interface. DDR3 is not directly compatible with any of the earlier types,
DDR or DDR2. This is due to different signaling voltages. This Kit describes the various aspects of DDR3
Design with Allegro.
Tips and Tricks - DEHDL and Associated Utilities Special Edition
This workshop helps you exercise a wide variety of DE-HDL commands, some of which may be already
known but may not! It includes tips & shortcuts that can help you become more productive while saving
you several thousand mouse clicks on an annual basis.
Virtuoso® Custom IC and Sign-off Flow
These Rapid Adoption Kits are related to the Virtuoso Custom IC and Sign-off Flow
using Virtuoso Schematic Editor (VSE), Multi-Mode Simulation (MMSIM), Virtuoso
Layout Suite (VLS), Physical Verification System (PVS) and other Virtuoso products.
Layout Design in IC 6.1.5
Faster, more accurate physical design using Virtuoso Schematic Editor and Virtuoso Layout Suite
This material highlights new features and explores some basic functionality with Virtuoso Schematic
Editor L/XL and Virtuoso Layout Suite L/XL in the 6.1.5 release. You will take a design from concept
through implementation and learn how Virtuoso 6.1.5 capabilities can help you generate designs more
efficiently.
What you will learn:
 Increase designer productivity by leveraging connectivity throughout the design process
 Use ties between schematic capture and layout, commonly referred to as connectivity, to
generate designs rapidly without sacrificing quality or performance
IC 6.1.5 Constraint Driven Custom Design
Optimized exchange between front-end and back-end designers for better layout productivity
The constraint-driven flow enables you to capture and transfer design requirements formally through
the Constraint Management System, and then use automatic and interactive tools to enforce the
requirements in the layout to ensure convergence on design goals. Constraints can be verified between
front and back to ensure that the layout is using them as intended and that they have been
implemented correctly. Finally, the system also enables storing and reusing of constraints across designs
or projects.
What you will learn:
 Use the Constraint Management System
 Use the Circuit Prospector for assisted constraint capture
 Verify constraints to ensure that design intent is met in layout
 Use the module generation (MODGEN) capability for precision Pcell-based array generation
 Perform constraint-driven wire editing
 Perform constraint-aware editing
 Perform special net automated routing (differential pair, shielding, etc.)
 Perform full custom/analog placement
Virtuoso Visualization & Analysis (ViVA)
Analog/mixed-signal waveform viewing and analysis
The Virtuoso Visualization and Analysis tool is an analog/mixed-signal waveform viewer providing the
means to thoroughly analyze the data generated by circuit simulation. Learn how to use it either as a
standalone tool or as an integrated part of the Virtuoso Analog Design Environment (L and XL).
What you will learn:
 View, configure, and export design data in a variety of formats quickly and easily
 Interactively analyze and annotate waveform data for design documentation
 Create and evaluate complex mathematical expressions, and save them for later reuse
 How to efficiently handle gigabyte transient data files
IC6.1 Front to Back Overview
Complete front to back design flow in IC615
This material highlights the complete front to back design flow available in the IC615 release framing
these capabilities in terms of designer productivity and results from the Metrics-driven Productivity
Initiative (MPI).
What you will learn:
 Design creation and constraint capture in the Virtuoso Schematic Editor
 Design analysis and verification with the Analog Design Environment
 Constraints
 Virtuoso environment
 Buses
 Constraint aware editing
 Fluid guardring
 Virtuoso Spaced-based Router & interactive routing
Guidelines on modeling analog circuits with WREAL
This material illustrates wreal modeling concepts by migrating a Verilog-A based model of an AM
modulation-demodulation system to a wreal model with Verilog-AMS. The wreal equivalent of each
block will be created to build up an all digital simulation for system.
What you will learn:
 During the course of the example, guideline steps for creating wreal Verilog-AMS models will be
developed and used for developing the wreal models
 The role of connect modules in a mixed-signal wreal simulation will be investigated
 The effects of sampling frequency will also be discussed, and the bilinear transform will be used
to create a discrete time low pass filter
Introduction to AMS Designer Simulation
This material uses a simple database consisting of an inverter chain to show the setup and use of AMS
Designer.
What you will learn:
 Both the GUI driven flow with ADE L and the text based command line flow are shown
 The steps to setup an AMS simulation in ADE L are discussed
 The ADE AMS Error Explanation tool will be used to show how to resolve simulation setup errors
 The steps needed to build the config view used in AMS simulation are illustrated
 The schematic based test case will be migrated to command line simulation to give an overview
of both the runams and irun AMS command line based simulation flows
IC 6.1.5 Rapid Analog Prototyping (RAP) Workshop
This material steps through a Rapid Analog Prototyping Flow in Virtuoso in IC 6.1.5. The objective of this
flow is to generate the layout of an analog circuit in an automated manner, in order to obtain early
feedback on parasitics and device effects on circuit simulation.
What you will learn:
 As a circuit designer you can thus identify issues early on and make necessary changes to quickly
iterate through the flow which helps avoid costly changes late in the cycle and enables faster
design convergence
 We demonstrate this flow using a sample and hold circuit based on a generic 45nm PDK
Parasitic Aware Design Workshop
ADE GXL's Parasitic Aware Design (PAD) features are used to investigate the effect of parasitic devices
on a circuit. This material has been designed to highlight the features and functionality of the PAD flow
in IC 6.1.5.
What you will learn:
 PAD Flow Overview
 Estimated Parasitic Flow
 Extracted Parasitic Flow
 Parasitic Reporting Flow
 Estimated PAD Flow using Custom Parasitic Cells
Analog Design Environment XL (ADE XL) Workshop
Analog Design Environment XL (ADE XL) Workshop
Virtuoso Analog Design Environment XL provides a multi-test simulation environment for thorough
design validation, extensive design exploration, IP reuse, and early insight into manufacturing variability.
This material has been designed to highlight many of the features and functionality of ADE XL.
What you will learn:
 Use Analog Design Environment XL to efficiently manage all your simulations and to easily
access all results
 Validate designs thoroughly over all required corners
 Automatically create design documentation based on results
 Use Analog Design Environment XL for improved verification coverage and statistical analysis
IC615 VSR (Virtuoso Space-based Router) Workshop
IC615 VSR (Virtuoso Space-based Router) Workshop
This workshop highlights interactive, assisted and automatic routing features available in Virtuoso
Space-based Router (VSR). During the course of the workshop you will be able to apply these features to
do some device and block level routing and analyze your results in R-IDE (Routing Integrated
Development Environment).
What you will learn:
 Interactive and Assisted Routing in VSR (Virtuoso Space-based Router)
 Routing Integrated Development Environment (R-IDE)
Virtuoso Integrated Physical Verification Sytem (Virtuoso IPVS) Workshop
Virtuoso Integrated Physical Verification Sytem (Virtuoso IPVS) Workshop
This workshop is designed to highlight many of the features and functionality of Virtuoso IPVS in the IC
6.1.5 work environment. IPVS is a capability provided in Virtuoso to continuously check design rules
using sign-off rules as you design. The goal of Virtuoso IPVS is to improve productivity by unobtrusively
verifying the design and providing feedback during the design process. This is especially important at
lower process nodes where the design rules are complex and discovering errors early can save time and
effort.
What you will learn:
 Creating layout with Virtuoso IPVS turned on
IC 6.1.5 Virtuoso Schematic Editor XL PIEA, Conformal Low Power: MixedSignal Low Power Structural Verification
Includes Rapid Adoption Kit with demo design (instructions are provided on how to setup user
environment). Introduces the Power Intent Export Assistant (PIEA) feature that has been introduced in
IC615 release. The power intent extracted is then verified by calling Conformal Low Power (CLP) which is
built inside Virtuoso environment.
What you will learn:
 Setup for PIEA
 Perform power intent extraction
 CPF Import
 Generate macro CPF and design CPF
 Perform low power verification by running CLP
Schematic Model Generator
Virtuoso Schematic Model Generator (SMG) is tightly integrated into the Virtuoso design environment
and enables the generation of analog/mixed-signal behavioral models using a schematic-like
representation of the behavioral model. The schematic view is then processed to generate the
behavioral model. With this approach, behavioral modeling becomes easier to comprehend,
communicate to involved team members and is better managed compared to manual textual entry.
What you will learn:
 What is SMG
 Key benefits of SMG and a tutorial to demonstrate how to create a simple behavioral model for
a voltage controlled oscillator (VCO) in the graphical modeling environment Schematic Model
Generator (SMG)
Creating Custom Connect Rules for AMS Simulation in ADE
This document outlines the process used to create custom connect rules for running Mixed-Signal
simulation in ADE with AMS Designer.
What you will learn:
 The 5V connect rules that ship with the AMS simulator in the INCISIV installation will be copied
to the working directory to create a set of custom connect rules for 1.5V.
 The example will show how to modify the rules file for 1.5V and how to build a connect rule
library that will be recognized by the Connect Rule setup dialog in ADE.
 A short simulation will be used to validate the rules.
Spectre Device Checks
Spectre device checking is used to monitor if devices in the circuit design are violating predefined set of
conditions. The example describes the usage of the Spectre device checking feature.
What you will learn:
 Set up device checks to insure that low voltage devices are not inadvertently used in a high
voltage application.
 In the event a device is operating in an overvoltage condition, the check can show a warning or
cause the simulation to stop on an error.
 Checking for conditions such as this can be an important productivity boost for long simulations
since the simulation will stop right away when the condition is violated rather than finding out
after the simulation has completed.
 Device Checking setup can be saved as with the ADE State for reuse or setup with an include file.
Both methods will be explored.
Using Spectre Save-Recover
Spectre and APS have the capability to save a simulation state and restart the simulation from the saved
state file. The simulation state for long simulations can be periodically saved to allow recovery from
unforeseen circumstances, such as power outages or disk full issues. The save/recover methodology can
also be used to restart simulations with different parameters or inputs. This example will illustrate using
Spectre/APS Save-Recover from both ADE and command line based simulation.
What you will learn:
 Using Spectre Save-Recover from ADE
 Using Spectre Save-Recover from the Command Line
 Additional Information/Quick Reference
Basics of Inherited Connections
Often times in design, the same cells need to be used in different parts of the circuit which use different
power supply voltages. Inherited connections provide a mechanism to selectively override net
connections by placing properties on the parent instance. Therefore the same cell can be used with
different power supplies without the need for explicit power and ground pins. This document describes
how inherited connections work with a sample design which shows how power and ground connections
for the same cell can be different in the schematic hierarchy.
What you will learn:
 Investigating Inherited Connections
 Setting Up Inherited Connections
 How Net Expressions Are Evaluated
Passing Parameters in the Schematic Hierarchy with pPar
Schematics can be parameterized with pPar parameters to allow passing parameters from a parent
instance to the lower level schematic (the child). This mechanism facilitates defining high level
parameters to define the functionality of the circuit. The test case used for this example defines a
strength parameter to set the drive capability of a buffer circuit. The strength parameter is passed down
through the schematic hierarchy to define the size of the mos devices making up the buffer which in
turn defines the current the buffer is capable of driving.
What you will learn:
 Investigate Parameter Passing with pPar
 How to Setup Parameter Passing with pPar
 Adding pPar Parameters to Existing Schematics
 Setting defaults for pPar Parameters
Power, Ground and Structured Routing Implementation Flow
The flow leverages a combination of existing Virtuoso functionality, Virtuoso Routing TCL commands,
and custom SKILL scripts to enable users to efficiently build custom power, ground and structured signal
routes. An assisted flow where users have detailed control over how data is created but should rarely
need to create or manipulate the data using the lowest level commands such as create, stretch, etc.
Data is created and manipulated at high level, no need for time consuming zooming, placement or
alignment of objects at the manufacturing grid level. The flow also supports creation of power and
ground rough-in during early floorplanning. This flow is intended for Analog Mixed-Signal designs at the
chip, block and device level in Virtuoso.
What you will learn:
 Power, Ground and Structured Routing Implementation Flow and Methodology
Encounter® Digital Implementation (EDI)
System and Sign-off Flow
These Rapid Adoption Kits are related to the Encounter Digital Implementation
(EDI) System and Sign-off Flow using Encounter Digital Implementation (EDI)
System, Encounter Timing System (ETS) and Encounter Power System (EPS).
Clock Concurrent Optimization (CCOpt)
What you will learn:
 Basics of running clock concurrent optimization (CCOpt) on a design in Encounter Digital
Implementation (EDI) system
 How to configure number of settings that control, how CCOpt will optimize the design
 How to run standalone CCOpt and use its analysis tools to investigate the design
 Advanced design debug techniques with CCOpt
 How to generate RC multipliers by correlating SPEF values with estimates for existing nets
Database Access with DBTCL
What you will learn:
 dbGet basics: interactive queries and introduction to database traversal in Encounter Digital
Implementation (EDI) system
 Advanced dbGet techniques for programming using pattern matching to filter lists of pointers
 Using dbGet .?h and dbSchema to learn more about the database objects and their attributes
 Modifying object attributes using dbSet
Post Assembly Closure (PAC) Flow
What you will learn:
 Basics of running Post Assembly Closure (PAC) flow on a design in Encounter Digital
Implementation (EDI) system
 To assemble the design and libraries into the Encounter Digital Implementation system and
create a floorplan
 To enable the PAC mode
 Verify the correctness of the data
Prototyping Foundation Flat Flow
What you will learn:
 Gigascale Prototyping with FlexModels
 Prototyping Usage Model.
 FlexModels enable GigaScale Design Exploration using EDI System
Prototyping Foundation Top to Bottom Flow
What you will learn:
 Gigascale Prototyping with FlexModels
 Prototyping Usage Model
 FlexModels enable GigaScale Design Exploration using EDI System
Encounter Low-Power Design Flow: CPF Implementation
What you will learn:
 How LP Foundation Flow works
 The advantage of CPF to implement designs with multiple supply voltage (MSV) and power shutoff (PSO) architecture
 Setting up MMMC in Low Power Flow
MMMC SignOff ECO using EDI11 System and ETS11
What you will learn:
 Overview and context
 What is the MMMC SignOff ECO solution
 Use model
 Results on several customer designs
MMMC SignOff ECO using EDI12/13.1 System and ETS12/13.1
What you will learn:
 Overview and context
 What is the MMMC SignOff ECO solution
 Use model based on ETS12 or ETS13.1
 Using AAE-SI delayCal which is the default
 Using read_view_definition as the main command to load the design environment
 Introducing Setup timing closure
 Using resize technique in addition to buffering
 Use model based on ETS12 or ETS13.1
 Runs Hold, DRV and Setup in one single session (using incremental timing closure
 Shows how to assemble a hierarchical design in ETS to perform STA and ECO
 Runs Hierarchical aware Hold, DRV and Setup timing closure in one single session
Global Timing Debug using EDI System or ETS
What you will learn:
 Use Model
 How to use global timing debug utility to do timing analysis
 How to create different categories for timing analysis
 How to perform bottleneck analysis
Time Budgeting using EDI System
What you will learn:
 How to run budgeting, and the associated flow
 Examine the effect of virtual optimization
 Examine the effect of Latency
 Modify and customize budget
 Support for OpenAccess in budgeting
How to RUN TQRC/IQRC/SignOff-QRC using EDI System
What you will learn:
 QRC Extraction Cell Level Flow
 How to run TQRC/IQRC/SignOff-QRC using EDI System
 Check timing using different engines
EDI to Transistor Level QRC Signoff Flow
What you will learn:
 How to extract parasitic
 Prepare different views to be used for post layout simulation
 Flow demonstration by using multiple supported flows i.e. DEF, StreaamOut, OA
Timing and Signal Integrity Analysis using Encounter Timing System (ETS)
What you will learn:
 How to load various input files and prepare setup for ETS
 How to do Timing Analysis and interpret reports
 Setup SI analysis
Digital Mixed Signal (DMS) Implementation using EDI and Virtuoso
What you will learn:
 Design Import and Early Timing Analysis
 Pin Optimization and Refinement
 Analog on Top (AoT) Block Design using Virtuoso and EDI
 FTM creation and top level timing analysis
 Late Cycle ECOs and FTM analysis
Synthesis, Test and Verification flow
These Rapid Adoption Kits are related to the Synthesis, Test and Verification flow
using RTL Compiler, Encounter Test, Conformal, and Incisive products.
RTL Compiler: RC Adoption Kit
Includes RTL Compiler (RC) Rapid Adoption Kit with demo design. Provides detailed RC overview, how to
get started and create a simple script quickly, insights into smart debugging, and general understanding
of RC’s flexible TCL infrastructure for increased productivity.
Skill Level : Beginner
RTL Compiler and Conformal LEC: Getting the Best out of RC and LEC
Includes RTL Compiler(RC) and Conformal LEC(LEC) and Rapid Adoption Kit with demo design (design
embedded within tool release, instructions are provided on how to setup user environment). Introduces
new framework to help RC/LEC verification.
Skill Level : Beginner
RTL Compiler(RC) and Incisive: RTL Power Profiling
Includes RTL Compiler (RC) and Incisive (IES) Rapid Adoption Kit with demo design. Demonstrates how
users can leverage both synthesis and verification technologies to perform early accurate power
analysis.
Skill Level : Intermediate
RTL Compiler Physical: Physically-aware Timing Closure and Congestion
Analysis
Includes RC Physical (RCP) Rapid Adoption Kit with demo design. Demonstrates physically-aware timing
closure and congestion analysis. Hand off fully-placed and legalized seed placement to physical design.
Skill Level : Intermediate
RTL Compiler Physical and Encounter Test: Physically-aware DFT
Includes RTL Compiler Physical (RCP) and Encounter Test (ET) Rapid Adoption Kit with demo design.
Introduces benefits of physically-aware test synthesis driving predictability.
Skill Level : Intermediate
Conformal Low Power, RTL Compiler and Incisive: Low Power Verification
for Beginners
Includes Rapid Adoption Kit with demo design (instructions are provided on how to setup user
environment). Introduces closed loop verification methodology using Conformal Low Power.
Skill Level : Beginner
Conformal Low Power and RTL Compiler: Low Power Verification for
Advanced Users
Includes Rapid Adoption Kit with demo design (instructions are provided on how to setup user
environment). Introduces advanced features of Conformal Low Power – Power Intent Comparison,
Hierarchical Integration and CPF Macro Modeling.
Skill Level : Intermediate
Conformal Constraint Designer: SDC Constraint and CDC Verification
Methodologies
Includes Conformal Constraint Designer (CCD) Rapid Adoption Kit with demo design. Demonstrates how
users can perform SDC constraint checks and Clock Domain Crossing (CDC) checks application for both IP
and chip-level requirements.
Skill Level : Beginner
Conformal ECO Designer and EDI System: Enabling RTL-to-GDSII ECO
Flows
Includes Conformal ECO Designer(ECO) and EDI Rapid Adoption Kit with demo design. Steps through
RTL-to-GDSII ECO flows users can leverage for their own design environment. Demonstrates benefits of
leveraging RTL Compiler under-the-hood for auto delta logic synthesis - transparent to user.
Skill Level : Beginner
Conformal Low Power: CPF Macro Models
Includes Conformal Low Power (CLP) Rapid Adoption Kit with demo design. Demonstrates benefits of
CPF macro modeling that can be leveraged throughout the Cadence low power design flow for increased
productivity.
Skill Level : Intermediate
Conformal Low Power: UPF-to-CPF Translation and Low Power Verification
Includes Conformal Low Power (CLP) Rapid Adoption Kit with demo design. Introduces the low power
interoperability flow using CLP and how to convert UPF to CPF. Included are guidance and
recommendations to navigate around some of the pitfalls of mixed-format flow.
Skill Level : Intermediate
RTL Compiler and Conformal Low Power: Advanced Low Power Synthesis
Validation
Includes RTL Compiler (RC) and Conformal Low power (CLP) Rapid Adoption Kit with demo low power
design and labs. Demonstrates how users can leverage RTL compiler to perform multi-supply voltage
(MSV) synthesis and low power cell insertion for power shutoff (PSO) and MSV. The RAK also
demonstrates the use of Conformal low power to validate power intent (CPF) quality and the
synthesized design netlist for equivalence and electrical integrity.
Skill Level : Intermediate
IC 6.1.5 Virtuoso Schematic Editor XL PIEA, Conformal Low Power: MixedSignal Low Power Structural Verification
Includes Rapid Adoption Kit with demo design (instructions are provided on how to setup user
environment). Introduces the Power Intent Export Assistant (PIEA) feature that has been introduced in
IC615 release. The power intent extracted is then verified by calling Conformal Low Power (CLP) which is
built inside Virtuoso environment. What you will learn: Setup for PIEA, perform power intent extraction,
CPF Import, generate macro CPF and design CPF, perform low power verification by running CLP.
Skill Level: Intermediate
Conformal LEC: LEC Jumpstart Kit
Includes LEC Jumpstart Kit with demo design and lab instructions. Provides detailed LEC technical stepby-step guide, how to get started and create a simple script quickly, insights into smart debugging, and
general understanding of LEC’s terminology and best practices for increased productivity.
Skill Level : Beginner
Encounter Test and RTL Compiler: Integrating DFT during Synthesis
Includes RTL Compiler (RC) and Encounter Test (ET) Rapid Adoption Kit with demo design. Helps user
walk through several of the DFT capabilities available for insertion via RC, including testability analysis,
compression analysis and insertion, and MBIST insertion. Shows the link to ET and how that flow is run.
Skill Level : Beginner
Encounter Test: ATPG and Analysis
Includes Encounter Test (ET) Rapid Adoption Kit with demo design. Demonstrates the static ATPG flow,
the delay test ATPG flow, the delay test ATPG flow with OPCG and SDF annotation as well as the Low
Power ATPG flow in Encounter Test.
Skill Level : Intermediate
Encounter Test: Precision Diagnostics
Includes Encounter Test (ET) Rapid Adoption Kit with demo design. Demonstrates how ET ATPG
customers can step through the precision diagnostics flow using Encounter Diagnostics.
Skill Level : Advanced
Encounter Test and RTL Compiler: Adding Structured Test and ATPG in the
VDI Environment
Includes Encounter Test (ET) and Virtuoso Digital Implementation (VDI) system Rapid Adoption Kit with
demo design. Demonstrates how VDI customers can use RTL Compiler (RC) to create designs ready for
structured test so mixed-signal designers can get familiar with the flow of using RC to insert scan and
test points and then run ATPG using ET.
Skill Level : Intermediate