CMOS RF Circuits for Wireless Communication
Siyou Weng
Integrated Circuit Systems,Inc
CMOS is the preferred choice for wireless transceiver implementation. No other
alternative can beat the cost advantage of CMOS. Also, sub micron CMOS technology
offers enormous computing power needed for the digital signal processing of a
transceiver. CMOS has the potential for full integration. Of course, CMOS process is
optimized for digital application, which do has its disadvantage while it comes to RF and
analog application.
A lot of research have been done in the area of RF CMOS, with great progress. In this
survey, I will go through different aspect of those researches. At section I, I will discuss
passive components, major building blocks will be addressed at section II, finally, I will
talk about different architecture of wireless receiver.
I.
Passive components.
Capacitor
Poly-poly capacitor is the preferred choice in any analog application. Another
approach, which combining lateral and vertical field of the multiple metal layer in
modern CMOS process to increase the metal-metal capacitance density[1].
Varactor
Paper [2] studied 7 different ways to implement a varactor in CMOS, including
quality factor, tenability, control voltage swing.
Inductor
Spiral inductor has been widely studied and used in RF CMOS circuits. Craninckx
studied the optimization of spiral inductors[3]. Yue proposed patterned ground shield as
a way to increase the quality factor [4]. Bonding wire also be explored in various studies.
II Building Block
LNA
A receiver’s sensitivity is mainly decided by the Low Noise Amplifier. Goo [5]
discussed in detail the technique of lowering the Noise Figure of a CMOS LNA.
Mixer
Gilbert multiplier like cell [9] and CMOS multiplier biased in the linear region are
all explored as mixer.
VCO
LC VCO is the primary choice for wireless application because of phase noise
requirement[8].
PA
Depends on the modulation scheme used by system, linearity requirements are
different. Nonlinear PA have higher PAE, using distributed active-transformer can
achieve higher frequency[10].
III Transceiver Architecture
Direct Conversion
Direct conversion architecture is the most straight forward one, but suffers mainly
from dc-offset problem due to VCO leakage. Lee[9] using the fact that a sine wave
with frequency Fc can be represented as product of (N/2) sine waves of frequrncy
(2*Fc/N) with certain phase relationship, using local oscillator only one-third of
carrier frequency but using six phase, then drastically reduce the dc-offset to a
negligible level.
Low IF
[11] use low IF approach, the image rejection is done by quadrature down-mixing,
then uses A/D converter directly digitize the 100K IF signal for baseband process.
This approach eliminate the dc offset problem of direct conversion also preserve the
simplicity.
Double Conversion
Behbahani, et al [12] use double IF structure. First, this avoid the dc offset and 1/f
noise which can significantly degrade SNR of the receiver, especially for 64-QAM
signals, second, this ease the image rejection requirement for the whole data path, for
perfect image-rejection depends on perfect matching, if using a direct conversion, 40db
image rejection ration means better than 1% matching throughout the conversion path,
which is unpractical in CMOS.
Reference
[1] R. Aparico, et al, “Capacity Limits And Matching Properties of Integrated
Capacitors”, IEEE J. Solid-State Circuits , pp384-393, Vol 37, March 2002
[2] A. Porret et al, “Design of High-Q Varactors for Low-Power Wireless
Applications Using a Standard CMOS Process”, IEEE J. Solid-State Circuits, pp 337345, Vol 35, March 2000
[3] J. Craninckx, et al, “A 1.8-GHz Low-Phase-Noise CMOS VCO Using Optimized
Hollow Spiral Inductors”, IEEE J. Solid-State Circuits, pp736-744, vol 32, May 1997
[4] C.P. Yue, et al, “On-chip Spiral inductors with patterned ground shields for Sibased RF ICs”, IEEE J. Solid-State Circuits, vol33, pp 734-752, May 1998
[5] J. Goo, et al, “A Noise Optimization Technique for Integarted Low_Noise
Amplifiers”, IEEE J. Solid-State Circuits, pp994-1002, vol 37, August, 2002
[6] J.C.Rudell, et al, “A 1.9 Ghz Wide-Band IF Double Conversion CMOS Receiver
for Cordless Telephone Applications”, IEEE J. Solid-State Circuits, pp 2071-2088,
Vol 32, Dec 1997
[7] A. Rofougaran,et al, “A Single-Chip 900Mhz Spread-Spectrum Wireless
Transceiver in 1-um CMOS- Part II: Receiver Design”, IEEE J. Solid-State Circuits,
pp.535-547, Vol 33, April 1998
[8] C. Guo, et al, “A Fully Integrated 900-Mhz CMOS Wireless Receiver With OnChip RF and IF Filters and 79-dB Image Rejection”, IEEE J. Solid-State Circuits,
pp1084-1089, Vol 37, August 2002
[9] K. Lee et al, “A Single-Chip 2.4-GHz Direct Conversion Receiver for Wireless
Local Loop using Multiphase Deduced Frequency Conversion Technique”, IEEE J.
Solid-State Circuits, pp.800-809,Vol 36, May, 2001
[10] I. Aoki, et al, “Fully Integrated CMOS Power Amplifier Dedign Using the
Distributed Active-Transformer Architecture”, IEEE J. Solid-State Circuits, pp 371383, Vol 37, March 2002
[11] M. Steyaert, et al, “A 2-V CMOS Cellular Transceiver Front-End”, IEEE J.
Solid-State Circuits, pp 1895-1907, vol 35, Dec, 2000
[12] F. Behbahani, et al, “A 2.4-GHz Low-IF Receiver for Wideband WLAN in
0.6um CMOS-Architecture and Front-End”, IEEE J. Solid-State Circuits, pp19081916, Vol 35, Dec, 2000