IV YEAR
ELECTRONICS AND INSTRUMENTATION
ENGINEERING
EI73-VLSI Design
(2mark questions and answers)
Unit I
1. Define Threshold voltage
The threshold voltage VT for a MOS transistor can be defined as the
voltage between the gate and the source terminals below which the drain
to source current effectively drops to zero.
Define body effect or substrate bias effect.
The threshold voltage VT is not a constant with respect to the voltage
difference between the substrate and the source of the MOS transistor.
This effect is called the body effect or substrate bias effect.
2. Give the different modes of operation of MOS transistor
Cut off mode
Linear mode
Saturation mode
3. What are the different regions of operation of a MOS transistor?
a. Cut off region
Here the current flow is essentially zero (accumulation mode)
b. Linear region
It is also called weak inversion region where the drain current is
dependent on the gate and the drain voltage w. r. to the substrate.
c. Saturation region
Channel is strongly inverted and the drain current flow is ideally
independent of the drain-source voltage (strong-inversion region).
4. Give the expressions for drain current for different modes of
operation of
MOS transistor.
a. Cut off region
ID =0
b. Linear region
ID = kn [(VGS – VT) VDS – VDS2/2]
c. Saturation region
ID = (kn /2) (VGS – VT)2
5. Plot the current-voltage characteristics of a nMOS transistor.
6. Define accumulation mode.
The initial distribution of mobile positive holes in a p type silicon
substrate of a mos transistor for a voltage much less than the threshold
voltage
7. What are the secondary effects of MOS transistor?
a. Threshold voltage variations
b. Source to drain resistance
c. Variation in I-V characteristics
d. Subthreshold conduction
e. CMOS latchup
8. What is CMOS latchup? How it can be prevented?
The MOS technology contains a number of intrinsic bipolar
transistors.These are especially troublesome in CMOS processes, where the
combination of wells and subtrates results in the formation of p-n-p-n
structures. Triggering these thyristor like devices leads to a shorting of VDD
& VSS lines, usually resulting in a destruction of the chip.
The remedies for the latch-up problem include:
(i) an increase in substrate doping levels with a consequent drop in the
value of Rpsubs.
(ii) reducing Rnwell by control of fabrication parameters and ensuring
a low contact resistance to VDD.
(iii) by introducing guard rings.
9. What are the different fabrication processes available to CMOS
technology?
a. p-well process
b. n-well process
c. Twin-tub process
d. Silicon On Insulator (SOI) / Silicon On Sapphire (SOS) process
10. What is intrinsic and extrinsic semiconductor?
The pure silicon is known as Intrinsic Semiconductor. When impurity
is added with pure silicon, it is electrical properties are varied. This is known
as Extrinsic semiconductor.
12. What are the steps involved in manufacturing of IC?
``
i. wafer preparation
ii. Epitaxial growth
iii. Oxidation
iv. photo lithography
v. Diffusion and Ion Implantation
vi. Isolation
vii. Metallization
13. What is meant by ‘ epitaxy ’ ?
Epitaxy means arranging atoms in single crystal fashion upon a single
crystal substrate.
14. what are the process involved in photo lithography?
i. making process
ii. photo etching process
these are important process involved in photolithography.
15. what is the purpose of masking in fabrication of IC?
Masking is used to identify the place in which Ion Implantion should
not be occurred.
16. what are the materials used for masking?
Photo resist, Sio2, SiN, poly Silicon.
17.what are the types of etching ?
Wet etching and dry etching are the types of photo etching.
18. what is diffusion process ? what are doping impurities?
Diffusion is a process in which impurities are diffused in to the silicon
chip at 10000C temperature. B2O3 and P2O5 are used as impurities.
19. what is isolation?
It is a process used to provide electrical isolation between different
components and interconnections.
20. what are the various CMOS technologies?
Various CMOS technologies are
i. n-well process or n-tub process
ii. p-well process or p-tub process
iii. twin-tub process
iv. Silicon on Insulator (SOI) process.
21. what is channel stop implantation?
In n-well fabrication, n-well is protected with resist material. Because,
it should not be affected by Boron implantation. The boron is implanexcept
n-well. It is done using photoresist mask. This type of implantation is known
as channel implantation.
22. what is LOCS?
LOCOS means Local Oxidation Of Silicon. This is one type of oxide
construction.
23. what is SWAMI?
SWAMI means Side Wall Masked Isolation. It is used to reduce
bird’s beak effect.
24. what is LDD?
LDD means Light Doped Drain Structures. It is used for implantation
of n- in n-well process.
25. what is twin-tub process? Why it is called so?
Twin-tub process is one of the CMOS technology. There are two
wells are available in this process. The other name of well is tub. So,
because of these two tubs, this process is known as twin-tub process.
Unit II
1. Draw the circuit of a nMOS inverter.
.
2. Give the expression for pull-up to pull-down ratio ( Zpu/Zpd) for an
nMOS
inverter driven by another nMOS inverter.
.
.
3. Draw the circuit of a CMOS inverter.
4. What are the advantages of CMOS inverter over the other inverter
configurations?
a. The steady state power dissipation of the CMOS inverter circuit is
negligible.
b. The voltage transfer characteristic (VTC) exhibits a full output
voltage wing between 0V and VDD. This results in high noise margin.
5. What are stick diagrams?
Stick diagrams are used to convey layer information through the
use of a color code. A stick diagram is a cartoon of a chip layout. They
are not exact models of layout. The stick diagram represents the
rectangles with lines which represent wires and component symbols.
6. What are the different color codes used for single poly silicon nMOS
technology?
n-diffusion (n-diff.) and other thinoxide regions -green
Polysilicon (poly.) - red
Metal 1 (metal) - blue
Implant - yellow
Contacts - black or brown (buried)
7. What are design rules?
Design rules are the communication link between the designer
specifying requirements and the fabricator who materializes them. Design
rules are used to produce workable mask layouts from which the various
layers in silicon will be formed or patterned.
8. Define a superbuffer.
A superbuffer is a symmetric inverting or noninverting gate that can
supply or remove large currents and switch large capacitive loads faster
than a standard inverter.
9.What are BiCMOS Gates?
When bipolar and MOS technology are merged, the resulting circuits
are referred to as biCMOS circuits. High gain vertical npn transistors with
their collectors tied to the positive rail, and medium-gain lateral npn
transistors are both compatible with conventional CMOS processing.
BiCMOS gates can be used to improve the performance of line drivers and
sense amplifiers.
10. what is the special feature of twin-tub process?
In twin-tub process, threshold voltage, body effect n and p devices are
independently optimized.
11. what are the advantage of twin-tub process?
Advantages of twin-tub process are
i. Separate optimized wells are available.
ii. Balance performance is obtained for n and p transistors.
12. what is SOI? What is the material used as Insulator?
SOI means Silicon-on-Insulator. In this process, Sapphire or SiO2 is
used as insulator.
13. what are the various etching process used in SOI process?
Various etching process used in SOI are
i. Isotropic etching process.
ii. Anisotropic etching process.
iii. Preferential etching process.
14. what are the advantages and disadvantages 0f SOI process?
Advantages of SOI process
i. There is no well formation in this process.
ii. There is no field-Inversion problem.
iii. There is no body effect problem.
Disadvantages of SOI process
i. It is very difficult to protect inputs in this process.
ii. Device gain is low.
iii. The coupling capacitance between wires always exist.
15. what are the possible modes in nMOS enhancement transistor?
i. accumulation mode
ii. depletion mode
ii. Inversion mode
16. In saturation region, what are the factors that affect Ids?
i. distancebetween source and drain.
ii. channel width
iii.Threshold oltage
iv.thickness of oxide layer
v. dielectric constant of gate insulator
vi. Carrier mobility.
17. What is Body effect?
The threshold voltage VT is not a constant w. r. to the voltage difference
between the substrate and the source of MOS transistor. This effect is called
substrate-bias effect or body effect.
18.What is Channel-length modulation?
The current between drain and source terminals is constant and
independent of the applied voltage over the terminals. This is not entirely
correct. The effective length of the conductive channel is actually modulated
by the applied VDS, increasing VDS causes the depletion region at the drain
junction to grow, reducing the length of the effective channel.
19.Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the
voltage applied between the gate and the source of the MOS transistor below
which the drain to source current, IDS effectively drops to zero.
20. Define Rise time
Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its
steady-state value.
21. Define Fall time
Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its
steady-state value.
22. Define Delay time
Delay time, td is the time difference between input transition (50%) and the
50% output level. This is the time taken for a logic transition to pass from
input to output.
23. What are two components of Power dissipation.
There are two components that establish the amount of power dissipated in a
CMOS circuit. These are:
i) Static dissipation due to leakage current or other current drawn
continuously from the power supply.
ii) Dynamic dissipation due to
- Switching transient current
- Charging and discharging of load capacitances.
24. Give some of the important CAD tools.
Some of the important CAD tools are:
i) Layout editors
ii) Design Rule checkers (DRC)
iii) Circuit extraction
25.What is Verilog?
Verilog is a general purpose hardware descriptor language. It is similar in
syntax to the C programming language. It can be used to model a digital
system at many levels of abstraction ranging from the algorithmic level to
the switch level.
Unit III
1. What are the static properties of complementary CMOS Gates?
a. They exhibit rails-to-rail swing with VOH = VDD and VOL =
GND.
b. The circuits have no static power dissipation, since the circuits are
designed such that the pull-down and pull-up networks are mutually
exclusive.
c. The analysis of the DC voltage transfer characteristics and the noise
margins is more complicated than for the inverter, as these parameters
depend upon the data input patterns applied to the gate.
2. Draw the equivalent RC model for a two-input NAND gate.
3. What are the major limitations associated with complementary
CMOS gate?
a. The number of transistors required to implement an N fan-in gate is
2N. This can result in a significantly large implementation area.
b. The propagation delay of a complementary CMOS gate deteriorates
rapidly as a function of the fan-in.
4. What is meant by ratioed logic?
In ratioed logic, a gate consists of an nMOS pull-down network that
realizes the logic function and a simple load device, which replace the entire
pull-up network. A ratioed logic which uses a grounded pMOS load is
referred to as a pseudo-nMOS gate
5. What is true single phase clocked register?
The True single-phase clocked register (TSPCR) uses a single clock,
CLK. For the positive latch, when CLK is high, the latch is in the transparent
mode and corresponds to two cascaded inverters; the latch is non-inverting,
and propagates the input to the output. On the other hand, when CLK=0,
both inverters are disabled, and the latch is in the hold mode.
6. Define a tally circuit.
A tally circuit counts the number of inputs that are high and outputs the
answer. If there are N inputs there are N +1 possible outputs, corresponding
to 0, 1, 2, …. N inputs that are high.
7.
Give
the
NAND-1$1'_LPSOHPHQWDWLRQ_RI_
_$%&___'()_LQ_VWLFN_IRUP_
_
8. 'UDZ_WKH_6WDWLF_$2,_&026_JDWHV_WR_UHDOL]H_
__$%___&'__
_
9. Draw the CMOS implementation of 4-to-1 MUX using transmission
gates .
10. What are the various modeling used in Verilog?
1. Gate-level modeling
2. Data-flow modeling
3. Switch-level modeling
4. Behavioral modeling
11. What is the structural gate-level modeling?
Structural modeling describes a digital logic networks in terms of the
components that make up the system. Gate-level modeling is based on using
primitive logic gates and specifying how they are wired together.
12.What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior of
MOSFETs. Digital circuits at the MOS-transistor level are described using
the MOSFET switches.
13. What are the types of programmable device?
Programmable logic structure
Programmable Interconnect
Reprogrammable gate arry
14. What is CLB?
CLB means Configurable Logic Block.
15.What are the two types of MOSFET?
Two types of MOSET are n-channel MOSET and p-channel MOSFET.
These are known as n-MOS and p-MOS.
16.which MOS can pass logic 1 and logic 0 strongly?
p-MOS can pass strong logic 1
n-MOS can pass strong logic 0
17. What is AOI logic function?
AND OR Invert logic function (AOI) implements operation in the order of
AND, OR, NOT operations. So this logic function is known as AOI logic
function.
18. What is bubble pushing?
According to De Morgan’s laws,
= +
+ =
So NAND gate may be drawn as bubbled OR gate. Bubbles are introduced
in the input side. This concept is known as bubble pushing.
19. Implement y =
using bubble pushing concept?
Y=
can be implemented using bubbled AND gate.
= +
20. What is OAI 221 Gate?
OAI 221, here 221 refers to number of inputs in each section.
21. Write the features of CMOS Domino Logic?
 These structures occupy small area compared with conventional logic
structure.
 Parasitic capacitance is to be small to increase the speed.
 Each gate can make one ‘logic 1’ to ‘logic 0’ transition.
22. What are the tally circuits?
 Tally circuits one of the applications of the pass transistor logic.
 It is used to count the number of inputs which are high and the output
is produced.
23. What are the various forms of inverter based CMOS logic?
i. Pseudo N-MOS logic
ii. Dynamic C-MOS logic
iii. Clocked C-MOS logic
iv. C-MOS domino logic
v. n-p C-MOS logic
24. What is PIP in XILINIX?
PIP means Programmable Interconnect Point in XILINIX.
25. What are the advantages and disadvantages of PLA?
Advantages of PLA
 Simplicity
 Small size
Disadvantages of PLA
 Speed problem occur (pull-ups may become slow on large terms )
Unit IV
1. Give the basic nMOS PLA structure.
The basic PLA structure consists of an AND plane driving an OR
plane. The terminology corresponds to a sum of products (SOP) realization
of the desired function. The SOP realization converts directly into a NANDNAND implementation. When a product of sums (POS) realization is
desired, it can be implemented in OR-AND or NOR-NOR logic. In either
case, the first array is referred to as the AND plane, and the second array as
the OR plane. The line connecting the AND plane to the OR plane are called
the product lines.
2. What do you mean by CMOS PLA.
The basic CMOS PLA is obtained by providing a well and replacing
the pull-up devices in the NAND-NAND array or in the NOR- NOR array
with enhancement mode pMOS devices. The CMOS array can be
precharged or not, and can be clocked 2 AND plane OR plane Register
Register In puts Outputs 1 with the same two-phase clocking scheme as used
for the MOS PLA. CMOS PLA design offers many more varieties of layout
than does nMOS.
3. Define finite state machine.
When feedback is added to the AND OR PLA structure, the PLA
becomes a finite state machine (FSM). An FSM can be designed as a Mealy
Machine or a Moore Machine. The Mealy machine has outputs, which may
change with input changes in an asynchronous manner and cause erroneous
behavior. Hence, the Mealy machine should be avoided whenever possible.
The Moore machine has outputs which depend upon and change only with
state changes, since all the outputs of the Boolean-logic block go through a
state register, and are synchronously clocked.
4. What are the importance of the PLA/FSM in VLSI?
(i) Regularity : It has a standard, easily expandable layout.
(ii) Convenience : Little design effort is required.
(iii) Compacted : It is efficient for small circuits.
(iv) Modularity : It makes it possible to design hierarchical PLAs and
FSMs into large sequential systems.
(v) Suitability to being computer generated.
5. Give the structure of a CPLD.
A CPLD comprises multiple circuit blocks on a single chip, with
internal wiring resources to connect the circuit blocks. Each circuit block is
similar to a PLA or a PAL.It includes four PAL like blocks that are
connected to a set of interconnection wires. Each PAL like block is also
connected to a sub circuit labeled I/O block, which is attached to a number
of the chip’s input and output pins.
6. Give the CPLD packages available.
a. PLCC package: The PLCC package has pins that “wrap around”
the edges of the chip on all four of its sides. The socket that houses the
PLCC is attached by solder to the circuit board, and the PLCC is held in the
socket by friction.
b. quad flat pack package: The QFP package has pins on all four
sides, and they extend outward from the package, with a downward-wiring
shape. The QFP’s pins are much thinner than those on a PLCC, which means
that the package can support a larger number of pins; QFPs are available
with more than 200 pins.
7. Give the structure of MAX 7000 CPLD.
8. What is meant by FPGA?
A field programmable gate array (FPGA) is a programmable logic
device that supports implementation of relatively large logic circuits. FPGAs
can be used to implement a logic circuit with more than 20,000 gates
whereas a CPLD can implement circuits of upto about 20,000 equivalent
gates. FPGAs are quite different from CPLDs because FPGAs do not
contain AND or OR planes. Instead, they provide logic blocks for
implementation of the required functions.
9. Give the general structure of FPGA.
10. What are the different commercial FPGA products?
Manufacturer FPGA products www Locator
Actel Act 1,2 and 3,MX,SX www.actel.com
Altera FLEX6000,8000 and 10k APEX 20kwww.altera.com
Atmel AT6000, AT40k www.ateml.com
Lucent ORCA 1,2 and 3 www.lucent.com
QuickLogic pASIC 1,2 and 3 www.quicklogic.com
Vantis VFI www.vantis.com
Xilinx XC3000,XC4000,XC5200,Virtexwww.xilinx.com
11. What are the types of reprogrammable GA?
Ad-hoc Array and Structured Array are the two types of Reprogrammable
Gate Array.
12. What is the type’s o FPLA?
I. PROM [Programmed Read-Only Memory]
II. PAL [Programmed Array Logic]
13. What are the applications of PAL?
i. Control logic application
ii. Input/Output
iii. Data-path logic
15. What is finite state machine (FSM)?
When feedback is added to AND-OR PLA structure, then it becomes FSM.
16. What are the characteristics of PLA/FSM?
i. Regularity
ii. Modularity
iii. Suitability
iv. Efficiency
17. What is CLB?
CLB means Configurable Logic Block.
18. Define mealy machine?
In mealy machine, output may change with the change in the input
asynchronously.
19. Define moore machine?
In moore machine, output can be changed when state is changed.
20. What is HDL?
VHSIC Hardware description Language.
21. What is VHSIC?
Very High Sped Integrated Circuits.
22. What are the various operators in VHDL?
i. Logical operators
ii. Relational operators
iii. Shift operators
iv. Adding operators
v. Multiplying operators
vi. Miscellaneous operators
23. What are the data types available in VHDL?
i. Scalar type
ii. Composite type
iii. Access type
iv. File type
24. What are the types of subprograms?
Functions and Procedures are types of subprograms.
25. What is the use of actual?
Actual in a subprogram call is used to pass the values from and to a
subprogram.
UNIT 5
VHDL
1)Write the acronym for VHDL?
VHDL is an acronym for VHSIC Hardware Description Language
(VHSIC is an acronym for Very High Speed Integrated Circuits).
2) What are the different types of modeling VHDL?
1) Structural modeling
2) Data flow modeling
3) behavioral modeling
4) Mixed type of modeling
3) What is packages and what is the use of these packages
A package declaration is used to store a set of common declaration
such as components types procedures and functions these declaration can
then be imported into others design units using a use caluse.
4) What is variable class ,give example for variable
An object of variable class can also hold a single value of a given type
, However in this case different values can be assigned to a variable at
different time.
Ex:variable ss: integer;
5) Name two subprograms and give the difference between these two.
1) Function 2) procedure
Only one output is possible in function..
Many outputs possible using procedure
6) What is subprogram Overloading
If two or more subprogram to be executed in a same name.
overloading of subprogram should be performed.
7) write the VHDL coding for a sequential statement (d-flipflop )
entity dff is
port(clk,d:in std_logic;
q:out std_logic);
end;
architecture dff of dff is
begin
process(clk,d)
begin
if clk’ event and clk=’ 1’ then
q<=d;
end process;
end;
8) What are the different kinds of The test bench
Stimulus only
Full testbench
Simulator specific
Hybrid testbench
Fast testbench
9) What is Moore FSM
The output of a Moore finite state machine(FSM) depends only on the
state and not on its inputs. This type of behaviour can be modeled using a
single process with the case statement that switches on the state value.
10) Write the testbench for and gate
entity testand2 is
end entity
architecture io of testand2 is
signal a,b,c:std_logic;
begin
g1:entity work.and2(ex2) port map(a,b,c)
a<=’ 0’ ,’ 1’ after 100 ns;
b<=’ 0’ , ‘1’ after 150 ns;
end;
11. write the syntax of procedure body?
Procedure procedure name (parameterlist)
12. What is test bench?
A test bench is a model which is used to exercise and verify the correctness
of a hardware model.
13. What are the two methods to generate stimulus values?
i. To create waveforms and apply stimulus at discrete time intervals.
ii. To generate stimulus based on the state of the entity or output of the
entity.
14. Differentiate between channeled & channel less gate array.
Channeled Gate Array Channel less Gate Array
1. Only the interconnect is customized only the top few mask layers are
customized.
2. The interconnect uses predefined spaces between rows of base cells. No
predefined areas are set aside for routing between cells.
3. Routing is done using the spaces Routing is done using the area of
transistors unused.
4. Logic density is less Logic density is higher.
15. What is a FPGA?
A field programmable gate array (FPGA) is a programmable logic device
that supports implementation of relatively large logic circuits. FPGAs can be
used to implement a logic circuit with more than 20,000 gates whereas a
CPLD can implement circuits of upto about 20,000 equivalent gates.
16. What are the different methods of programming of PALs?
The programming of PALs is done in three main ways:
• Fusible links
• UV – erasable EPROM
• EEPROM (E2PROM) – Electrically Erasable Programmable ROM
17.What is an antifuse?
An antifuse is normally high resistance (>100MW). On application of
appropriate
programming voltages, the antifuse is changed permanently to a lowresistance
structure (200-500W).
18. What are the different levels of design abstraction at physical
design.
• Architectural or functional level
• Register Transfer-level (RTL)
• Logic level
• Circuit level
19.What are macros?
The logic cells in a gate-array library are often called macros.
20. What are Programmable Interconnects?
In a PAL, the device is programmed by changing the characteristics if the
switching element. An alternative would be to program the routing.
21. Give the steps inASIC design flow.
a. Design entry
b. Logic synthesisSystem partitioning
c. Prelayout simulation.
d. Floorplanning
e. Placement
f. Routing
g. Extraction
22. Write notes on functionality tests?
Functionality tests verify that the chip performs its intended function. These
tests assert that all the gates in the chip, acting in concert, achieve a desired
function. These tests are usually used early in the design cycle to verify the
functionality of the circuit.
23. Write notes on manufacturing tests?
Manufacturing tests verify that every gate and register in the chip functions
correctly. These tests are used after the chip is manufactured to verify that
the silicon is intact.
24. Mention the defects that occur in a chip?
a) layer-to-layer shorts
b) discontinuous wires
c) thin-oxide shorts to substrate or well
25. Give some circuit maladies to overcome the defects?
a. nodes shorted to power or ground
b. nodes shorted to each other
c. inputs floating/outputs disconnected