CEC 222 Digital Electronics Lab
Spring 2015
Lab 9: Design of Counters
Learning Objectives:

Introduction to counters.

Reinforcement of the idea of the “state” of a sequential machine.
Lab Overview:
Counters provide simple examples of sequential logic digital designs as they may not have external inputs
and the outputs may be the same patterns as the state encodings. In the first experiment you will be developing
a simple modulo-8 counter. In the second experiment you will be adding an external input, driven by a switch,
to allow the counter to count either up or down. Finally, you will generate outputs for your counter which
correspond to a “0” concatenated with the seven digits of your student ID and display them on a seven segment
display.
YOUR NAME(S)
Lab 9: Design of Counters
Page 1 of 8
CEC 222 Digital Electronics Lab
Spring 2015
Pre-Lab (10%)
Preparation for Experiment 1.
State Transition Graph
A modulo-8 counter, as the name implies, counts from 0 up to 7 and then
000
repeats the sequence.
111
Question 1. What is the minimum number of flip-flops needed to design a
modulo-7 counter? _____________
Task 1.
001
110
D-type flip-flops have been selected for your counter design.
010
101
011
100
Complete the state transition table below. Note that the “C” FF corresponds
to the most significant bit (MSB) and “A” to the LSB.
Table 1 State Transition Table for a modulo-7 counter
Present State
Task 2.
Next State
Flip-Flop Inputs
𝑄𝐶
𝑄𝐵
𝑄𝐴
𝑄𝐶+
𝑄𝐵+
𝑄𝐴+
0
0
0
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
𝐷𝐶
𝐷𝐵
𝐷𝐴
Derive “simplified1” expressions for the D flip-flop inputs (K-maps?):
DC = ___________________________  Number of gates required = __
DB = ___________________________  Number of gates required = __
DA = ___________________________  Number of gates required = __
State of FFs
Note that this state machine has only a clock as its input and the outputs
are the states (specifically the state encodings).
FF Inputs
Combinational
Logic
Q’s
Flip-Flops
Clock
1
Least number of gates would be one viable approach to simplification.
YOUR NAME(S)
Lab 9: Design of Counters
Page 2 of 8
CEC 222 Digital Electronics Lab
Spring 2015
Preparation for Experiment 2.
State Transition Graph
The modulo-8 up/down counter counts up if the UD input is high and
000
down is the input is low. This up/down counter could be
implemented using a schematic, however, VHDL code can offer a less
111
001
cumbersome solution.
110
Task 3.
010
Review the VHDL code below to implement the up/down
counter and modify/correct it as required.
101
011
100
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ud_counter is
port (
clk, ud: in std_logic;
QC, QB, QA: out std_logic);
end ud_counter;
architecture my_logic of ud_counter is
signal q_tmp: std_logic_vector(2 downto 0):= "000"; -- Initialize
begin
process(clk)
begin
if rising_edge(clk) then
if ud = '1' then
q_tmp <= q_tmp + 1; -- Count UP
else
_________________; -- Count DOWN
end if;
end if;
end process;
QC <= q_tmp(2);
QB <= q_tmp(2);
QA <= q_tmp(2);
end my_logic;
Note that this state machine does have an external input,
State of FFs
other than the clock, however, the outputs are the states
UD
Inputs
FF Inputs
Combinational
Logic
(specifically the state encodings).
Q’s
Flip-Flops
Clock
YOUR NAME(S)
Lab 9: Design of Counters
Page 3 of 8
CEC 222 Digital Electronics Lab
Spring 2015
State Transition Graph
Preparation for Experiment 3.
0
Design a counter to count up or down through the sequence “0” followed by
9
the seven digits of your student ID. For example, if the seven digits of your student
ID is “2655019”, your state transition graph would be as show. This problem highly
2
1
6
resembles our up/down counter, however, now the output can NOT be the same as
0
the states (specifically the state encodings).
5
5
Question 2. Why can’t we simply count through the sequence as shown?
________________________________________________________________________________________
___________________________________________________________________________________________
Question 3. The seven digits of your student ID are = ___________
Task 4.
Modify the following VHDL code which will allow us to use our up\down counter to produce the
desired outputs associated with each state of the counter.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity op_combo_logic is
Port ( QA, QB, QC : in STD_LOGIC;
Student_ID :
out STD_LOGIC_VECTOR (3 downto 0));
end op_combo_logic;
architecture Behavioral of op_combo_logic is
signal q: STD_LOGIC_VECTOR (2 downto 0);
begin
q <= QC & QB & QA; -- Concatinate the bits
with q select -- Based on the counter state set the output
Student_ID <= "0000" when "000", -- Start with a "0"
"????" when "001", -- 1st digit of Student ID
"????" when "010", -- 2nd digit of Student ID
"????" when "011", -- 3rd digit of Student ID
"????" when "100", -- 4th digit of Student ID
"????" when "101", -- 5th digit of Student ID
"????" when "110", -- 6th digit of Student ID
"????" when others; -- Last digit of Student ID
end Behavioral;
than the clock, also, now the outputs are different from the
Inputs
State of FFs
Note that this state machine has an external input, other
states.
Input
Combinational
Logic
FF Inputs
Q’s
Flip-Flops
Output
Combinational
Logic
Clock
YOUR NAME(S)
Lab 9: Design of Counters
Page 4 of 8
CEC 222 Digital Electronics Lab
Spring 2015
Experiments (90%)
EXPERIMENT 1.
A BASIC MODULO-8 COUNTER
In this initial experiment you will be implementing a modulo-8 counter using your pre-lab design as the
basis for a schematic.
Step 1.a: Referring to the first part of the pre-lab, build the circuit in ISE

Start a new schematic project in ISE named “Lab9_Experiment1”

Place three D-type flip-flops (Symbol “fd”) into your schematic named “mod8_counter” and add the
necessary gates required to implement the logic equations from the first part of your pre-lab (i.e., DC, DB,
and DA).

Label the input port CLK_1HZ (clock input) and label the output ports QC, QB, and QA.
Task 5.
Take screenshot of your schematic and insert it into Figure 1.
Figure 1 Schematic of the modulo-8 counter
Step 1.b: Test your design via a simulation

Simulate your design by driving the input “CLK_1HZ” with a 1 us period
clock for a simulatin duration of 10 us (recall Lab 7, Experiment 1info):
 Set the simulation duration to 10.00us
 Restart (
) to clear the traces
 Right click on the signal “CLK_1HZ” and select “Force Clock”
YOUR NAME(S)
Lab 9: Design of Counters
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CEC 222 Digital Electronics Lab
Task 6.
Spring 2015
Place a screenshot of your simulation into Figure 2. You might want to remove all signals other
than CLK_1HZ, QA, QB, and QC. Also, the zoom to full view (
) command will adjust the window to
show all 10 us of your simulation.
Figure 2 Simulation of a modulo-7 counter
EXPERIMENT 2.
AN MODULO-8 UP/DOWN COUNTER
In the first experiment we developed a schematic in order to realize our design. A schematic is once again a
viable approach, however, VHDL code is much more efficient.
Step 2.a: Referring to the second part of the pre-lab, use the code which you modified/corrected to implement
the up/down counter.

Start a new schematic project in ISE named “Lab9_Experiment2”

Add a new schematic named “main”

Add a new VHDL Module named “ud_cnt”, insert your updated code from the 2nd section of the pre-lab
and create a symbol from this code.
 The symbol name will be the same as the entity name (i.e., “ud_counter”)

Label the input ports CLK_1HZ (clock input) and UD also label the output ports QC, QB, and QA.
Step 2.b: Test your design via a simulation

Simulate your design by driving the input “CLK_1HZ” with a 1 us period clock and the UD with a 20 us
period clock for a simulation duration of 20 us (recall Lab 7, Experiment 1info):
 Set the simulation duration to 20.00 us
YOUR NAME(S)
Lab 9: Design of Counters
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CEC 222 Digital Electronics Lab
 Restart (
Spring 2015
) to clear the traces
 Right click on the signal “CLK_1HZ” and select “Force Clock” do the same for signal “UD”
Task 7.
Place a screenshot of your simulation into Figure 3. The zoom to full view (
) command will
adjust the window to show all 20 us of your simulation.
Figure 3 Simulation of a modulo-8 up/down counter
EXPERIMENT 3.
AN MODULO-8 UP/DOWN SEQUENCE COUNTER
In this experiment you will be implementing an up/down sequence counter which increments either up or
down through the sequence “0” concatenated with the seven digits of your student ID. The design will display
the digits on your FPGA’s seven segment display.
Step 3.a: Referring to the third part of the pre-lab, use the code which you modified to implement the output
combinational logic required to assign an output different than the state’s encoding.

To the existing “Lab9_Experiment2” project, add a new VHDL Module named “op_logic”, insert your
updated code from the 3rd section of the pre-lab and create a symbol from this code.
 The symbol name will be the same as the entity name (i.e., “op_combo_logic”)

Connect the output of the “ud_counter” to the inputs of “op_combo_logic”
Step 3.b: Add a symbol to drive the seven segment display

Download a copy of the file “seven_seg.vhd” to your desktop

Right click on the project and select “Add Copy of Source” then navigate to “seven_seg.vhd” to add the
file to your project.
YOUR NAME(S)
Lab 9: Design of Counters
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CEC 222 Digital Electronics Lab

Spring 2015
Select the file “seven_seg.vhd.vhd” and create a schematic symbol (entitled “my_7_seg”) from this
code. Add this symbol to your schematic.

Connect the output of the “op_combo_logic” to the inputs of “my_7_seg”

Label the output port of “my_7_seg” to be “seg”.
Step 3.c: Add a symbol to drive the 1 Hz clock using the on-board 25 MHz clock

Download a copy of the file “slow_clock.vhd” to your desktop

Add a copy of this file to your project and create a symbol from it.

Connect the output of the “slow_clock” to the inputs of “ud_counter” (delete the CLK_1HZ port)

Add an input port named “CLK_25MHZ” to “slow_clock”.
Your final schematic should resemble that of Figure 4 .
Figure 4 Final schematic
Step 3.d: Implement and test your design

Download a copy of the file “Lab9_constraints.ucf” and add it to your project

Review the file carefully to ensure that the names EXACTLY match the port names in your schematic!!!

Synthesize, Implement, and generate a programming file.

Program your FPGA.
Optional Exercise(s) (+10% Extra Credit)
EXPERIMENT 4.
DEBOUNCING A SPST SWITCH
TBD
YOUR NAME(S)
Lab 9: Design of Counters
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