Digital Logic Design – Chapter 6
COMBINATIONAL CIRCUITS
Chapter 5 – COMBINATIONAL CIRCUITS
6-1. To check if a 4-bit binary value lies within the range 0110 to 1100, you may use one AND gate and a.
one 4-bit magnitude comparator b.
two 4-bit magnitude comparators c.
one 4 × 16 decoder with active-high outputs d.
one 8: 1 multiplier e.
one 4-to-2 encoder
6-2. If a 4-bit magnitude comparator has 𝐴 = 0111 and 𝐵 = 1001 on its inputs, the outputs are a.
“ 𝐴 > 𝐵 ” is 0, “ 𝐴 < 𝐵 ” is 0, “ 𝐴 = 𝐵 ” is 0 b.
“ 𝐴 > 𝐵 ” is 0, “ 𝐴 < 𝐵 ” is 0, “ 𝐴 = 𝐵 ” is 1 c.
“ 𝐴 > 𝐵 ” is 0, “ 𝐴 < 𝐵 ” is 1, “ 𝐴 = 𝐵 ” is 0 d.
“ 𝐴 > 𝐵 ” is 1, “ 𝐴 < 𝐵 ” is 0, “ 𝐴 = 𝐵 ” is 0 e.
“ 𝐴 > 𝐵 ” is 1, “ 𝐴 < 𝐵 ” is 1, “ 𝐴 = 𝐵 ” is 1
6-3. A 4-bit parallel adder can add a.
two 4-bit binary numbers b.
two 2-bit binary numbers c.
four 1-bit binary numbers d.
four bits at a time e.
four bits in sequence
6-4. The 74LS83A is a 4-bit adder IC chip. To expand this device to an 8-bit adder, you must a.
use four adders with no interconnections b.
use two adders and connect the sum outputs of one to the bit inputs for the other c.
use eight adders with no interconnections d.
use two adders with the carry output of one connected to the carry input of the other e.
All of the above
6-6. Design a logic circuit that converts a 4-bit signed number 𝐴𝐵𝐶𝐷 in a sign-and-magnitude format into the equivalent 4-bit number 𝑊𝑋𝑌𝑍 in two’s complement format. Express 𝑊, 𝑋, 𝑌 and 𝑍 in simplified
SOP and POS forms. Implement 𝑊 and 𝑋 using two-level AND-OR circuits, and 𝑌 using a two-level
OR-AND circuit (use inverters to obtain primed literals).
6-9. Design a multiply-by-3 circuit that takes in a 2-bit unsigned binary number 𝑌
1
𝑌
0
and produces a 4-bit binary number 𝑀
3
𝑀
2
𝑀
1
𝑀
0
(three), then 𝑀
3
𝑀
2
𝑀
1
𝑀
0
whose value is three times that of 𝑌
1
= 1001 (nine).]
𝑌
0
. [For example, if 𝑌
1
𝑌
0
= 11
Write out the truth table and the simplified SOP expressions for 𝑀
3
, 𝑀
2
, 𝑀
1
and 𝑀
0
.
You are to use a half-adder, an inverter, and an AND gate to implement 𝑀
3
, 𝑀
2
, 𝑀
1
and 𝑀
0
.
6-10. The 4221 code is a weighted code used to represent 10 decimal digits 0 to 9. Define a Boolean function 𝑉(𝐴, 𝐵, 𝐶, 𝐷) that generate 1 if 𝐴𝐵𝐶𝐷 is a valid 4221 code, or 0 if it is an invalid 4221 code.
Using the fewest 4-bit magnitude comparators (whose block diagram is shown on the right), and at most one OR gate (no restriction on the fan-in), implement the function 𝑉 .
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Digital Logic Design – Chapter 6
COMBINATIONAL CIRCUITS
ANSWERS
6-1. (b)
6-2. (c)
6-3. (a)
6-4. (d)
6-6.
𝐴 𝐵 𝐶 𝐷 𝑊 𝑋 𝑌 𝑍
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 1
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 1
0 1 1 0 0 1 1 0
0 1 1 1 0 1 1 1
𝐴 𝐵 𝐶 𝐷 𝑊 𝑋 𝑌 𝑍
1 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1
1 0 1 0 1 1 1 0
1 0 1 1 1 1 0 1
1 1 0 0 1 1 0 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 1 0
1 1 1 1 1 0 0 1
𝑾 = 𝑩 + 𝑨 ⋅ 𝑪 + 𝑨 ⋅ 𝑫
𝑿 = 𝑨
′
⋅ 𝑩 + 𝑩 ⋅ 𝑪
′
⋅ 𝑫
′
+ 𝑨 ⋅ 𝑩
′
𝒀 = 𝑨 ′ ⋅ 𝑪 + 𝑪 ⋅ 𝑫 ′ + 𝑨 ⋅ 𝑪 ′ ⋅ 𝑫
⋅ 𝑪 + 𝑨 ⋅ 𝑩
′
𝒁 = 𝑫
; 𝑾 = (𝑨 + 𝑩) ⋅ (𝑩 + 𝑪 + 𝑫)
⋅ 𝑫 ; 𝑿 = (𝑨 + 𝑩) ⋅ (𝑩 + 𝑪 + 𝑫) ⋅ (𝑨
′
; 𝒀 = (𝑨 + 𝑪) ⋅ (𝑪 + 𝑫) ⋅ (𝑨 ′ + 𝑪 ′
; 𝒁 = 𝑫
+ 𝑩
′
+ 𝑪
′
) ⋅ (𝑨
′
+ 𝑫 ′ )
+ 𝑩
′
+ 𝑫
′
)
2

Digital Logic Design – Chapter 6
COMBINATIONAL CIRCUITS
6-9.
𝑌
1
𝑌
0
𝑀
3
𝑀
2
𝑀
1
𝑀
0
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 1 0
1 1 1 0 0 1
Half
𝑋
Adder
𝐶
𝑌 𝑆
𝑀
𝑀
𝑀
𝑀
3
2
1
0
= 𝑌
1
= 𝑌
= 𝑌
1
1
′
= 𝑌
0
6-10.
𝑨 𝑩 𝑪 𝑫 𝑽
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
𝑋
3
𝑋
2
𝑋
0
𝑌
3
𝑌
1
𝑌
0
𝑋
3
𝑋
2
𝑋
1
𝑋
0
𝑌
3
𝑌
2
𝑌
1
𝑌
0
𝑋 < 𝑌
𝑋 = 𝑌
𝑋 > 𝑌
𝑋 < 𝑌
𝑋 = 𝑌
𝑋 > 𝑌
⋅ 𝑌
⋅ 𝑌
0
0
′
⋅ 𝑌
0
+ 𝑌
1
⋅ 𝑌
0
′
3