VLSI System Design
Lect. 2.2 CMOS Transistor Theory2
Engr. Anees ul Husnain ( anees.buzdar@gmail.com )
Department of Electronics & Computer Systems Engineering,
College of Engineering & Technology, IUB
Outline . . .
 Non-ideal Transistor Behavior

High Field Effects
 Mobility Degradation
 Velocity Saturation

Channel Length Modulation
Ideal Transistor I-V
polysilicon
gate
W
tox
n+
L
SiO2 gate oxide
(good insulator, ox = 3.9)
n+
p-type body


0


V
I ds    Vgs  Vt  ds
2
 
2


V

V


gs
t

2
for nMOS
Vgs  Vt
V V  V
 ds
ds
dsat

Vds  Vdsat
cutoff
linear
saturation
for pMOS
The important practical effects are neglected. . .
Ideal vs. non-ideal
ideal
Non-ideal
 Saturation current does not increase quadratically with Vgs
 Saturation current lightly increases with increase in Vds
REASONS
 Velocity Saturation
 Mobility Degradation
 Channel Length Modulation
 Sub-Threshold Conduction
 Junction Leakage
Ideal vs. non-ideal
 There is leakage current when the transistor is in cut off
 Ids depends on the temperature
Ideal vs. Simulated nMOS I-V Plot

65 nm IBM process, VDD = 1.0 V
Ids (A)
Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts
1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs
ds
DD
Saturation current increases
with Vds
Vgs = 1.0
800
Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with Vgs
400
Vgs = 0.8
Vgs = 0.6
200
Vgs = 0.6
Vgs = 0.4
0
Vds
0
0.2
0.4
0.6
0.8
1
ON and OFF Current
Ids (A)
1000
Ion = 747 mA @
Vgs = Vds = VDD
800
 Ion = Ids @ Vgs = Vds = VDD

Saturation
Vgs = 1.0
600
Vgs = 0.8
400
Vgs = 0.6
200
Vgs = 0.4
0
Vds
0
 Ioff = Ids @ Vgs = 0, Vds = VDD

Cutoff
0.2
0.4
0.6
0.8
1
Electric Fields Effects
 Vertical electric field: Evert = Vgs / tox
 Attracts carriers into channel
 Long channel: Qchannel  Evert
 Lateral electric field: Elat = Vds / L
 Accelerates carriers from drain to source
 Long channel: v = Elat
Coffee Cart Analogy
 Tired student runs from VLSI lab to coffee cart
 Freshmen are pouring out of the some other lecture
 Vds is how long you have been up
 Your velocity = fatigue × mobility
 Vgs is a wind blowing you against the glass (SiO2) wall
 At high Vgs, you are buffeted against the wall
 Mobility degradation
 At high Vds, you scatter off freshmen, fall down, get up
 Velocity saturation
 Don’t confuse this with the saturation region
Velocity Saturation
 When A strong enough electric field is applied:
 the carrier velocity in the semiconductor reaches a
maximum value saturation velocity
 the carriers lose energy through increased levels of
interaction with the lattice, collisions and by emitting phonons
Velocity Saturation
Velocity Saturation
Velocity Saturation
Velocity Saturation
 At high Elat, carrier velocity rolls off
 Carriers scatter off atoms in silicon lattice
 Velocity reaches vsat
 Electrons: 107 cm/s
 Holes: 8 x 106 cm/s
 Better model
Vel Sat I-V Effects
 Ideal transistor ON2 current increases with VDD2
2
W Vgs  Vt 

I ds  Cox
 Vgs  Vt 
L
2
2
 Velocity-saturated ON current increases with VDD
I ds  CoxW Vgs  Vt  vmax
 Real transistors are partially velocity saturated


Approximate with a-power law model
Ids  VDDa
 1 < a < 2 determined empirically (≈ 1.3 for 65 nm)
Alpha model
 Transistor to operate in region: (moderate supply voltages)
 v no longer inc. with field but not completely saturated
 a – velocity saturation index
For the Transistors with
 Long channels or Low Vdd  quadratic I-V characteristics in saturation
 Alpha = 2 (max)
 More velocity saturated  increasing Vgs less effect on current
 Alpha decreases (reaching 1 for completely velocity saturated)
 Simply THE MODEL HAS STRAIGHT LINE IN LINEAR REGION
Alpha model
 0
Vgs  Vt
cutoff

Vds

I ds   I dsat
Vds  Vdsat
linear
 Vdsat
 I dsat
Vds  Vdsat saturation
I dsat  Pc

V

2
gs
 Vt 
a
Vdsat  Pv Vgs  Vt 
a /2
Pc, Pv and alpha are found by fitting the model to the empirical modeling results
Empirical Modeling
 Refers to any kind of (computer) modelling based on empirical
observations rather than on mathematically describable
relationships of the system modelled.

The word empirical denotes information gained by means of
observation, experience, or experiment
Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
 Region between n and p with no carriers
 Width of depletion Ld region grows with reverse bias
 Leff = L – Ld
 Shorter Leff gives more current
 Ids increases with Vds
 Even in saturation
GND
Source
VDD
Gate
VDD
Drain
Depletion Region
Width: Ld
n
+
L
Leff
p GND
n
+
bulk Si
Channel length modulation
• Increasing Vds
 increases depletion width
 decreases effective channel length
 increases current
Channel length
modulation factor
(empirical factor)
Next . . .

Threshold Voltage Effects




Leakage




Body Effect
Drain-Induced Barrier Lowering
Short Channel Effect
Subthreshold Leakage
Gate Leakage
Junction Leakage
Process and Environmental Variations
Threshold Voltage Effects
 Vt is Vgs for which when the channel starts to invert

Means Vgs has the control of thresh hold
 Ideal models assumed Vt is constant
 Really depends (weakly) on almost everything else:
 Body voltage: Body Effect
 Drain voltage: Drain-Induced Barrier Lowering
 Channel length: Short Channel Effect
Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel

Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0  g

fs  Vsb  fs

 fs = surface potential at threshold
fs  2vT ln



NA
ni
Depends on doping level NA
And intrinsic carrier concentration ni
g = body effect coefficient
2q si N A
t
g  ox 2q si N A 
 ox
Cox
DIBL
 Electric field from drain affects channel
 More pronounced in small transistors where the drain is
closer to the channel
 Drain-Induced Barrier Lowering
VVV 
ttds
 Drain voltage also affect Vt
Vt   Vt  Vds
 High drain voltage causes current to increase.
Short Channel Effect
 In small transistors, source/drain depletion regions extend
into the channel
 Impacts the amount of charge required to invert the channel
 And thus makes Vt a function of channel length
 Short channel effect: Vt increases with L
 Some processes exhibit a reverse short channel effect in
which Vt decreases with L
Leakage
 What about current in cutoff?
 Simulated results
 What differs?
 Current doesn’t
go to 0 in cutoff
Leakage Sources

Subthreshold conduction


Transistors can’t abruptly turn ON or OFF
Dominant source in contemporary transistors
Tunnel current

Gate leakage

polysilicon
gate
Tunneling through ultrathin gate dielectric
W
t ox
n+

Junction leakage

L
n+
Subthreshold conductio
p-type body
Reverse-biased PN junction diode current Junction leakage
 Subthreshold leakage is the biggest source in modern transistors
Junction Leakage
 Reverse-biased p-n junctions have some
leakage
p+
n+
n+
p+
p+
n well
p substrate
n+
Leakage current: junction leakage and
tunneling
Junction leakage: reverse-biased p-n junctions have
 VvD

T
some leakage.
I D  I S  e  1


Is depends on doping levels and area and perimeter


of diffusion regions
p+
n+
n+
p+
p+
n+
n well
p substrate
109
0.6 nm
0.8 nm
2
JG (A/cm )
Tunneling leakage:
 Carriers may tunnel thorough very thin gate oxides
 Negligible for older processes
10
tox
VD D trend
6
103
1.0 nm
1.2 nm
100
1.5 nm
1.9 nm
10-3
10-6
10-9
0
0.3
0.6
0.9
VD D
1.2
1.5
1.8
Temperature Sensitivity
 Increasing temperature
 Reduces mobility
 Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature
I ds
increasing
temperature
Vgs
Process variations
threshold voltage 0.97V
threshold voltage 0.57V
Both MOSFETs have 30nm channel with 130 dopant atoms in the channel depletion region
Process variations impact gate length, threshold voltage, and oxide thickness
So What?
 So what if transistors are not ideal?
 They still behave like switches.
 But these effects matter for…





Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation