DIGITAL SYSTEMS TCE1111
Shift Registers and Shift Register Counters
Week 10 and Week 11
(Lecture 2 of 2)
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DIGITAL SYSTEMS TCE1111
Shift Register
Shift Register is one of the most widely used functional device in
Digital Systems. The simple pocket calculator illustrates the shift
register’s characteristics.
How Shift Register Works ?
If a 4-bit shift Register receives 4-bits of parallel data and shift
them to the right four positions into some other device
STEP-1 Parallel load a 1000: 1 0 0 0
Serial receiving
device
0
Q
D
11
CLOCK
INPUT
Cp
Q
D
Q
D
Q
D
0
0
0
Cp
Cp
Cp
X
X
X
X
CLOCK
2
X=Undetermined State
DIGITAL SYSTEMS TCE1111
Shift Register
10 00
STEP -2
0
D
Q
D
01
Apply pulse 1:
Cp
CLOCK
Q
Q
D
Q
1
0
0
Cp
Cp
Cp
0
X
X
X
0
0
X
X
1
10 00
STEP -3
0
Apply pulse 2:
D
Q
01
Cp
CLOCK
D
2
D
Q
D
Q
D
Q
0
1
0
Cp
Cp
Cp
3
DIGITAL SYSTEMS TCE1111
Shift Register
10 00
STEP - 4
0
D
Q
D
01
Apply pulse 3:
Cp
CLOCK
Q
Q
D
Q
0
0
1
Cp
Cp
Cp
0
0
0
X
1
0
0
0
3
STEP -5
0
Apply pulse 4:
10 00
D
Q
01
Cp
CLOCK
D
4
D
Q
D
Q
D
Q
0
0
0
Cp
Cp
Cp
4
DIGITAL SYSTEMS TCE1111
Shift Register
One method of identifying Shift Registers is how data is loaded
into and read from the storage unit. There are Four Categories of
Shift Registers.
5
DIGITAL SYSTEMS TCE1111
Shift Register
Serial in/serial out shift register.
• Serial entry of data into a shift register.
• A 4-bit device implemented with D flip-flop.
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DIGITAL SYSTEMS TCE1111
Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be constructed
from discrete flip-flops as is shown here with a five-bit
serial-in serial-out register.
Each clock pulse will move an input bit to the next flipflop. For example, a 1 is shown as it moves across.
FF0
Serial
data
input
1
D0
C
FF1
Q0
1
D1
C
FF2
Q1
1
D2
C
FF3
Q2
1
D3
C
FF4
Q3
1
D4
Q4
1
Serial
data
output
C
CLK
CLK
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DIGITAL SYSTEMS TCE1111
Shift Register
Input is 01011, lsb in first
Assumed that the registers is initially cleared. Show the state of the 5-bit
register for the specified data input and clock waveforms.
8
DIGITAL SYSTEMS TCE1111
Shift Register
Four bits (1010) being entered serially into the register.
lsb in first
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DIGITAL SYSTEMS TCE1111
Shift Register
Serial out –lsb in first
Four bits (1010) being entered serially into the register.
• The register is initially clear.
• The 0 is put onto the data input line, when the 1st. Clock pulse, FF0 is
reset, thus storing 0.
• Next CLK2. Bit 1, is applied to the data input, making D=1 for FF0 and
D=0 for FF1, when 2nd. Clock pulse occurs, the 1 on the data input is
shifted into FF0, and the 0 was in FF0 is shifted into FF1.
• The CLK3 . Bit, a 0 is put onto the data input line, and a clock pulse is
applied, the 0 is entered into FF0, the 1 stored in FF0 is shifted into FF1,
and the 0 stored in FF1 is shifted into FF2.
• the CLK4, the last bit, a 1, is now applied to the data input and a clock
pulse is applied. This time the 1 is entered into FF0, the 0 stored in FF0 is
shifted into FF1, the 1 stored in FF1 is shifted into FF2, and the 0 stored in
FF2 is shifted into FF3.
• This complete the serial entry of four bits into the shift register.
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DIGITAL SYSTEMS TCE1111
Four bits (1010) being entered serially into the register.
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DIGITAL SYSTEMS TCE1111
Four bits (1010) being entered serially into the register.
• The bits must be shifted our serially and taken off the q3 output.
• After CLK4 in the dta-entry operation, the LSB, 0, appears on the
Q3 output.
• When clock pulse CLK5, the second bit appears on the Q3 output.
• When CLK6, shift the third bits to the output Q3
• When CLK7, shift the fourth bit to the output Q3.
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DIGITAL SYSTEMS TCE1111
Shift Register
A serial in/parallel out shift register.
• Figure shows a 4-bit serial in/parallel out shift register and its logic block
symbol.
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DIGITAL SYSTEMS TCE1111
Serial in/parallel out shift register.
An application of shift registers is conversion of serial
data to parallel form.
For example, assume the binary number 1011 is loaded
sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
FF0
Serial
data
input
1
X
0
D00
D
FF1
Q00
Q
1
0
C
C
D11
D
C
C
FF2
FF2
Q11
Q
0
11
D22
D
C
C
Q22
Q
FF3
FF3
10
D33
D
Q33
Q
11
C
C
CLK
CLK
CLK
Parallel out –msb in first
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DIGITAL SYSTEMS TCE1111
Shift Register
0110, msb in first
Show the of the 4-bit register for the data input and clock waveforms. The register
initially contains all 1’s.
The register contains 0110 after 4 clock pulses.
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DIGITAL SYSTEMS TCE1111
Shift Register
A 4-bit parallel in/serial out shift register.
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DIGITAL SYSTEMS TCE1111
Shift Register
A 4-bit parallel in/serial out shift register.
• There are four data-input lines, D0, D1, D2, D3 and a SHIFT/LOAD input,
which allows four bits of data to load in parallel into the register.
• When SHIFT/LOAD is LOW, gates G1 through G3 are enabled, allowing
each data bit to be applied to the D input of its respective flip-flop.
• When a clock is applied, the flip-flops with D=1 will set and those with
D=0 will reset, thereby storing all four bits simultaneously.
• When SHIFT/LOAD is HIGH, gates G1 through G3 are disabled and G4
through G6 are enabled, allowing the data bits to shift right from one
stage to the next.
• The OR gates allow either the normal shifting operation or parallel dataentry operation, depending on which AND gates are enabled by the level
on the SHIFT/LOAD input.
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DIGITAL SYSTEMS TCE1111
Shift Register
Show the data-output waveform for a 4-bit register with the parallel input data and
the clock and SHIFT/LOAD waveforms given.
Parallel out – msb
first out
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DIGITAL SYSTEMS TCE1111
Shift Register
A parallel in/parallel out register.
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DIGITAL SYSTEMS TCE1111
Shift Register
• The 74HC195 can be used for parallel in/parallel out operation. It also
can be used for serial in/serial out and serial in/parallel out operation.
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DIGITAL SYSTEMS TCE1111
Shift Register
It can be used for parallel in/parallel out by using Q3 as the
output.
• When the SHIFT/LOAD input is LOW, the data on the
parallel inputs are entered synchronously on the positive
transition of the clock.
• When SHIFT/LOAD is HIGH, stored data will shift right (Q0
to Q3) synchronously with the clock.
• Inputs J and K are the serial data inputs to the first stage of
the register (Q0); Q3 can be used for serial output data.
• The active-LOW clear input is asynchronous.
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DIGITAL SYSTEMS TCE1111
Shift Register
Sample timing diagram for a 74HC195 shift register.
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DIGITAL SYSTEMS TCE1111
Shift Register
4-Bit Bidirectional Shift Register-Logic Diagram
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DIGITAL SYSTEMS TCE1111
Shift Register
4-Bit Bidirectional Shift Register-Operation
• A HIGH on the RIGHT / LEFT control input allows data
bits inside the register to be shifted to the right and a LOW
enables data bits inside the register to be shifted to the left.
• When the RIGHT / LEFT control input is HIGH, gates G1
through G4 are enabled, and the state of the Q output of each
flip-flop is passed through to the D input of the following
flip-flop. When a clock pulse occurs, the data bits are shifted
one place to the right.
• When the RIGHT / LEFT control input is LOW, gates G5
through G8 are enabled, and the Q output of each flip-flop is
passed through to the D input of the preceding flip-flop.
When a clock pulse occurs, the data bits are then shifted one
place to the left.
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DIGITAL SYSTEMS TCE1111
Shift Register
4-Bit Bidirectional Shift Register-Timing Diagram
Assume that initially Q0=1, Q1=1, Q2=0, and Q3=1 and the serial data-input
is LOW. Timing diagram for the given
control input
waveform is given below:
RIGHT / LEFT
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DIGITAL SYSTEMS TCE1111
The Johnson Counter
• A Johnson counter will produce a modulus of 2n.
• A 4-bit device has a total of 8 states and the 5-bit device has a total of
10 states.
• The implementation of a Johnson counter is the same regardless of the
number of stages.
• The Q output of each stage is connected to the D input of the next
stage, except the Q output of the last stage is connected back to the D
input of the first stage.
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DIGITAL SYSTEMS TCE1111
The Johnson Counter
Clock Pulse
Q0
Q1
Q2
Q3
0
0
0
0
0
1
1
0
0
0
2
1
1
0
0
3
1
1
1
0
4
1
1
1
1
5
0
1
1
1
6
0
0
1
1
7
0
0
0
1
Four-bit Johnson sequence:
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DIGITAL SYSTEMS TCE1111
The Johnson Counter
Five-bit Johnson sequence:
Clock Pulse
Q0
Q1
Q2
Q3
Q4
0
0
0
0
0
0
1
1
0
0
0
0
2
1
1
0
0
0
3
1
1
1
0
0
4
1
1
1
1
0
5
0
1
1
1
1
6
0
1
1
1
1
7
0
0
1
1
1
8
0
0
0
1
1
9
0
0
0
0
1
28
DIGITAL SYSTEMS TCE1111
The Johnson Counter
Timing sequence for a 4-bit Johnson counter
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DIGITAL SYSTEMS TCE1111
The Johnson Counter
• Timing
sequence for a 5-bit Johnson counter
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DIGITAL SYSTEMS TCE1111
The Ring Counter
Logic diagram for a 10-bit ring counter.
• The inter-stage connections are the same as those for a Johnson
counter, except that Q rather than Q is fed back from the last stage.
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DIGITAL SYSTEMS TCE1111
The Ring Counter
10-bit ring counter sequence
CLOCK PULSE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
2
0
0
1
0
0
0
0
0
0
0
3
0
0
0
1
0
0
0
0
0
0
4
0
0
0
0
1
0
0
0
0
0
5
0
0
0
0
0
1
0
0
0
0
6
0
0
0
0
0
0
1
0
0
0
7
0
0
0
0
0
0
0
1
0
0
8
0
0
0
0
0
0
0
0
1
0
9
0
0
0
0
0
0
0
0
0
1
32
DIGITAL SYSTEMS TCE1111
The Ring Counter
If a 10-bit ring counter has the initial state 1010000000, determine the waveform for
each of the Q outputs.
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