Independent internet
Embedded system MidTerm
Winter 2013
Preformed by: Genady okrain
Instructor: Tsachi Martsiano
Duration: Two semesters - 2013
System Overview
Winter 2013
Part A Goals
• Transfer big files from the PC to the
FPGA and back.
• Ethernet Interface.
• DDR Interface.
• Test data speeds.
• UDP Packets Analyzers:
• Ostinato Packet/Traffic Generator and Analyzer.
• Wireshark network protocol analyzer.
Winter 2013
FPGA – Data Flow
Winter 2013
Embedded Processor Interface
Winter 2013
MPMC
• Double Data Rate (DDR/DDR2/DDR3/LPDDR) and Single
Data Rate (SDR) SDRAM memory support.
• Parameterizable:
• number of ports (1 to 8)
• number of data bits to memory (4, 8, 16, 32, 64)
• configuration of data path FIFOs
• Customize-able Interfaces: XCL, LocalLink (using SDMA),
PLB v4.6 with Xilinx simplifications, NPI, MCB,
MIB/PPC440MC, and VFBC
Winter 2013
MPMC - Configuration
Winter 2013
MPMC – DDR2
Winter 2013
NPI PIM Features
• Allows you to extend the capabilities of MPMC to meet your own
design needs.
• Offers a simple interface to memory that can easily be adapted to
nearly any protocol.
• Provides address, data, and control signals to enable read and write
requests for memory.
• Allows simultaneous push and pull of data from the port FIFOs.
• MPMC supports the following transfer sizes: byte, half-word, word,
double-word, 4-word cacheline, 8-word cacheline, 16-word bursts,
32-word bursts, and 64-word bursts.
Winter 2013
NPI PIM - 32-Word, Burst Write
Winter 2013
NPI PIM - 32-Word, Burst Read
Winter 2013
NPI RW
Winter 2013
NPI RW State Machine
Winter 2013
Embedded Tri-Mode Ethernet MAC
• Fully integrated 10/100/1000 Mb/s Ethernet MAC
• Designed to the IEEE Std 802.3-2002 specification
• Configurable full-duplex operation in 10/100/1000
Mb/s
• Media Independent Interface (MII), Gigabit Media
Independent Interface (GMII), and Reduced Gigabit
Media Independent Interface (RGMII)
Winter 2013
Embedded Tri-Mode Ethernet MAC Interface
Winter 2013
Ethernet MAC
Winter 2013
Ethernet MAC Interface
Winter 2013
Ethernet MAC Registers
Winter 2013
Dummy
Winter 2013
Dummy State Machine
Winter 2013
Clocks & Throughput
• FPGA:
• 125 Mhz
• Microblaze:
• 125 Mhz
• DDR2@200 MHz 64 bits:
• 1.6 Gbyte/sec
• Ethernet:
• 1 Gbit/sec
Winter 2013
Ostinato
Winter 2013
Wireshark
Winter 2013