Cryogenic Process Design Kits For Advanced
CMOS Processes
9/30/2022
Team: Group 2
Colton Acosta
Jaivan Bedal
Gedeon Irumva
Tracy Concialdi
Jason Boyd
Mentor
Prof. Hugh Barnaby
Executive Summary
The Advanced Cryogenic Process Design Kit (PDK) For Advanced CMOS Processes project
aims to develop a compact model for a CMOS process at cryogenic temperatures. PDKs model
transistor behavior using test data collected from integrated circuits (IC) subjected to various
environmental conditions by fitting device parameters to the test data. Typically, semiconductor
fabrication companies, commonly called foundries, send out PDK files to customers so that they
can simulate their IC designs accurately in order to understand performance prior to fabrication.
To this end, the team will work with the SkyWater Technologies foundry to develop a PDK
including temperature and radiation effects at temperatures as low as 40K. The application of
interest for the project is Readout Integrated Circuits (ROIC) used with Focal Plane Arrays
(FPA) in satellite imaging systems.
To complete the project, several cryogenic and radiation hardened printed circuit boards (PCBs)
will be designed and manufactured. These will connect an IC from within a cryogenic testing
chamber to a semiconductor parameter analyzer. Data will then be collected and packaged for
development of the PDK. In the first semester, the data collection setup will be assembled and
preliminary data will be collected. The second semester will focus on modeling and developing
the PDK. The budget for this project will be provided primarily by SkyWater, and the
contracting company Alphacore. Most of the materials for the test setup have already been
purchased, so the $100 budget allocated to the team by the ECEE department will be used to buy
parts for an amplification and filtering PCB.
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Introduction
Over the past few decades, satellite-based imaging systems have been heavily relied upon for a
wide variety of applications such as GPS navigation, defense/intelligence, and scientific
research. These imaging systems typically consist of a photo-sensitive sensor array paired with a
readout circuit that digitizes the photon data for use by a microprocessor. One such sensor is the
Focal Plane Array (FPA), which consists of an array of infrared (IR) photo-sensitive cells
situated at the focal point of a lens. IR radiation incident on these cells produces a photocurrent,
which is measured using a Readout Integrated Circuit (ROIC). These ROICs are typically
constructed using an analog-to-digital converter and CMOS gates, and is situated below the FPA
as shown in Figure 1.
Since these systems are space-borne, they must be designed to withstand very harsh
environmental conditions such as large operating temperature ranges, excessive irradiation, and
low ambient pressures. These adverse operating conditions influence the behavior of the ROIC
CMOS, and therefore necessitate the development of more accurate models than those typically
used for consumer electronics. Additionally, exposure to these conditions result in unique
behavior such as the “kink effect” discussed in [1], which are not observed in more hospitable
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environments. With these considerations in mind, the objective of this project is to make use of
university resources to generate the data required to characterize CMOS devices from the
SkyWater foundry, and develop a new PDK with the acquired data to facilitate the development
of ROICs used along with FPAs in satellite imaging systems.
Customer Discovery
The use of Focal Plane Array (FPA) technology in many satellite-based imaging systems creates
a large customer base ranging from military to the private sector. As previously mentioned, the
inhospitable ambient conditions lead to a high demand for robust imaging technology that can
withstand extreme temperatures and radiation levels over long periods of time. For this reason,
Arizona State University has partnered with Alpha Core and SkyWater in order to conduct these
radiation and temperature tests of CMOS devices. SkyWater has invested in creating a better
semiconductor to aid in the improvement of FPA technology. The team at Arizona State
University is dedicated to validating their new designs to ensure that these semiconductors
perform as expected in the harsh environment of space.
The proximate customer for this project is the research team at Arizona State University led by
Dr. Hugh Barnaby and the ultimate customers are Alpha Core and SkyWater. Alpha Core and
SkyWater will use the PDK data in the development of new FPA technology.
Previous Work
Ever since Taiwan Semiconductor Manufacturing Company (TSMC) opened its doors as a
“pure-play” foundry in 1987, and separated IC design from developing manufacturing processes,
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the need for data driven PDKs has existed. PDKs prove to IC design companies that their designs
will function and with acceptable yield rate. Given the incredibly important role of PDKs, there
have been many improvements and additions to PDKs over the years including Design Rule
Checking (DRC), integrated circuit simulation (SPICE), optical process correction (OPC),
lithographic process checking (LPC), and design for manufacturing (DFM) recommended rules.
Even more recently package assembly design kits (ADK) have come to market, which include all
the IC modeling information typically included in PDKs in addition to external component
models. Consequently, the increased reliability of PDKs has given semiconductor companies the
confidence to continue developing ICs using smaller and more advanced process nodes [2].
Previous work creating cryogenic PDKs includes the paper Characterization and Compact
Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures by Rosario M.
Incandela et al. This paper describes how CMOS transistors function at cryogenic temperatures,
namly 10 mK and 300 K [1].
Previous work creating PDKs for radiation exposure include the 2022 Short Course Notebook
first presented at the 2022 IEEE Nuclear and Space Radiation Effects Conference. This paper
describes how to extract key parameters that describe the effect radiation has on IC
characteristics [3].
Scope
The target specifications for this project have been chosen with priority given to the integrity of
the data and models, structure of the test setup, and needs of the customer. The primary
requirement is that the models must cover the range of cryogenic temperatures that are typically
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encountered in a space environment. SkyWater has requested that testing be performed down to
40K. A secondary target will be the effect of radiation on the CMOS devices. The extent to
which this will be considered in this project will depend on the time available after the first
objective is achieved. Finally, as a reach goal the team also aims to develop several standard
library gates in Cadence such as inverters, NAND, and NOR gates.
In order to meet the stated specifications, the team will work closely with Professor Barnaby to
collect and process the data. Testing will be performed using a cryogenic testing chamber, a
semiconductor parameter analyzer, and several custom PCBs. Special attention will be paid to
sources of noise in the setup, and actions will be taken to reduce this noise as much as possible.
This can be achieved by adequately shielding cable harnesses, using large ground planes on the
PCBs, and routing sensitive signals on inner layers of the PCBs. A transimpedance amplifier
board will also be designed and manufactured to further ensure the integrity of the extracted data.
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The team will present the project with a combination of presentation materials, models, and
visuals of collected data. All final PCBs designs will also be presented so the customer can see
the physical product of this project. In addition, there will be documentation on collected data
and equipment to showcase the developmental process. Furthermore, the novelty of the project
will be demonstrated through the presentation of the model results over a range of temperatures
which are uncommon for most CMOS device processes.
Team Capabilities and Facilities
To achieve the objectives of the project the team will make use of several lab spaces at ASU
including the ISTB4 555 lab, the cryostat testing room in ISTB4, and the circuits lab in GWC.
The 555 lab in ISTB4 has several tools and supplies including a soldering station, several
oscilloscopes and multimeters, and various electronic components for prototyping. The circuits
lab in GWC includes a Keithley 4200 semiconductor parameter analyzer that will be used to
acquire data from the CMOS devices. The cryostat testing room is where most of the data
collection will take place, and is used to store cryogenic fluids and the cryostat itself. The
cryostat consists of a tall, cylindrical chamber within which the IC under test is mounted, and a
pump that fills the chamber with cryogenic fluid as shown in Figure 3. The cryostat is situated on
top of the dewar and is supported by several bars of unistrut.
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Construction of the cryostat and associated infrastructure will be assisted by Professor Barnaby’s
research lab. Currently, the test stand has already mostly been set up. The remaining work is in
the construction of the PCBs to be used for data collection and the cable harnesses which will
connect the PCBs, IC under test, and the semiconductor parameter analyzer. PCBs will be
ordered from Circuit Shop in Albuquerque, New Mexico with the assistance of Professor
Barnaby and ECEE purchasing. They will be assembled in the 555 lab using the soldering
station, and then mounted within the cryostat setup. Connector harnesses will be assembled by
soldering wires directly into the PCBs, and adding the additional insulation and shielding. For
the amplifier board, the circuit will be tested using the multimeters and oscilloscopes in the 555
lab. Finally, the standard cells will be designed by using the Cadence tool with ASU’s student
access to the Cadence software.
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Conclusion
In summary, accurate simulation of space-based digital systems such as the ROICs used in
thermal imaging sensors necessitates extensive data collection over wide ranges of operating
temperatures. This presents semiconductor foundries a unique difficulty in generating PDKs that
will meet the requirements of customers that use CMOS for space applications. The goal of this
project is to leverage university research resources to develop the required models by testing ICs
provided by the SkyWater Technologies foundry under cryogenic temperatures. The resulting
data can then be easily packaged into a compact model and standard library cells to be delivered
to the customer. These goals will be accomplished using several ASU lab spaces, and the
guidance of Professor Barnaby and researchers in his lab. Given that the team consists of a mix
of experienced circuits, device physics, and software specialists, the project will produce a high
quality product with an immense amount of value for the customer.
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References
[1] R. M. Incandela, L. Song, H. Homulle, E. Charbon, A. Vladimirescu, F. Sebastiano,
“Characterization and Compact Modeling of Nanometer CMOS Transistors at
Deep-Cryogenic Temperatures,” Journal of the Electron Devices Society, April, 2018, vol. 6,
pp. 998-1000.
[2] John Ferguson, "The Process Design Kit: Protecting Design Know-How," Semiconductor
Engineering, November 8, 2018. [Online]. Available: Semiconductor Engineering,
https://semiengineering.com. [Accessed September 29, 2022].
[3] Dr. Philippe Paillet, "Experimental characterization of radiation effects parameters for
device and circuit level modeling," in Multi-Scale, Multi-Physics of Radiation Effects:
Presented at the 2022 IEEE Nuclear and Space Radiation Effects Conference, NSREC 2022,
Proco, Utah, USA, July 18-22, 2022, Sylvain Girard, 2022.
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