I602
IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. Y. SEPTEMBER 1989
A Study of Contamination and Damage on Si
Surfaces Induced by Dry Etching
FARHAD K. MOGHADAM
Abstract-Damagelcontamination effects of dry etching in two
different modes, plasma etching (PE) and reactive ion etching (RIE),
on silicon surfaces just after oxide etching were studied. The electrical
measurements on aluminum Schottky diodes were used to evaluate the
effect of dry processing and various post-etch treatments on a Si substrate. The presence of heavy metal contamination on the Si surface as
a result of dry etching is confirmed by secondary ion mass spectroscopy
(SIMS) and SECCO etch defect decoration. C-r (minority-carrier lifetime) measurements on special guard ring devices were used as indirect
evidence of heavy metal contaminants. The quality of a gate oxide
grown on Si surfaces after dry-etching conditions is examined through
breakdown voltage. Improved device electron mobility is observed for
the RIE-exposed Si surface compared to PE, due to the smoother surface after the RIE process.
I. INTRODUCTION
S the minimum CMOS device geometries approach
the submicrometer regime and with junction depths
decreasing, low contamination/damage-free etch technology becomes imperative. There are five major categories
of plasma damage [l]: 1) metallic contaminations (which
lead to deep-level traps, degradation of generation carrier
lifetime, high contact resistance, and leakage current), 2)
polymer formation (source of high contact resistance), 3)
UV radiation (causing traps generation), 4) electrostatic
discharge (causes gate oxide breakdown occurrence), and
5 ) physical damage due to energetic ion bombardment.
There are various test procedures to examine these types
of damage, either analytically (by Auger, SIMS, ESCA,
XPS, RBS, RHEED, etc.) or electrically ( C-V, Z-V,
C-t, BVG stress test, monitoring device parameters such
as electron channel mobility).
Dry etching (in both PE or RIE mode) is carried out in
a reactor with species (electrons, ions, photons) that have
energies in the range of tens to several hundred electronvolts. The bombardment of the substrates by energetic
ions generated in the plasma ensures the directionality of
the pattern transfer. The electrons and photons are the byproducts of these reactions. There is the potential of device electrical characteristics degradation upon coming in
contact with the high-energy species. Several studies have
been published focusing on the characterization of plasma
damage on device performance. These studies consist o f
1) capacitance-voltage ( C-V ) and photocurrent-voltage
techniques used to monitor the MOS capacitor parameters
A
Manuscript received March 22, 1988; revised February 20, 1989. The
review of this paper was arranged by Associate Editor S . J . Fonash.
The authors are with Intel Corporation, Santa Clara, CA 95052.
IEEE Log Number 8928852.
AND
XIAO-CHUN MU
(e.g., interface state densities Qss,charge trapping, etc.
[2], [3]); 2) oxidation-induced stacking faults (OSF), used
to monitor surface damage [4], [5], and heavy metals contamination; 3) deep-level transient spectroscopy (DLTS)
[6], [7] to observe deep level impurities such as Cr atoms,
etc.; and 4) surface analytical techniques such as Auger
electron spectroscopy (AES) [8], secondary ion mass
spectrometry (SIMS) [9]-[ 111, the Rutherford backscattering (RBS) techniques [ 121, [ 131, and RHEED 14. Rapid
thermal annealing (RTA) has been used to restore surface
properties of Si exposed to RIE in a case where there was
no substantial residue layer produced by the etching [20].
In this paper, a combination of qualitative (SECCO)
and quantitative (Z-V characteristics of Schottky diode,
gate breakdown frequency, minority-carrier lifetime generation mobility ) techniques have been employed to study
the impact of dry-etching-induced contamination/damage
on silicon surfaces and its impact on device characteristics.
11. EXPERIMENTAL
PROCEDURE
All of the samples used in this study were p-type (100)
CZ non-epi silicon wafers with resistivities in the range
of 36-63 Q-cm, except for the cases of GOM and C-t
tests, in which cases p--pt epi wafers, with resistivities
in the range of 10-14 Q-cm in the p- epi layer, were used.
The etches were performed on a blank wafer before any
processing. The etchers used were AME-8110 and LRC490. The recipe used in AME-8110 is the following: 1)
CHF3/02 chemistry (75 / 9 SCCM ), 50 mtorr, 1200 W,
for 30 min. Self-bias in this machine was measured to be
-500 V. The recipes used in LRC-490 are: 1) C,F6
chemistry (125 sccm), 400 m torr, l-cm gap, 200 W, for
2 min, or 2) Cl2 chemistry (120 SCCM), 180 mtorr,
0.6-cm gap, 165 W, 2 min. The self-bias in this system
was measured to be less than 20 V . After etching, some
wafers were capped with poly Si for SIMS analysis, and
on some samples AES analysis was also performed. MOS
capacitor structures were built to study the effect of PE
and RIE on the subsequently grown oxide quality. A1-Si
Schottky diodes were fabricated on the etched surfaces to
study the metal-silicon (M-S) barrier height change due
to ion bombardment damage and polymer layer formation. Guard-ring structures (MOS) were formed on the
etched surface to detect any degradation of minority-carrier generation lifetime due to the presence of heavy metal
contamination (Fe, Cr, Ni). Also, some wafers were put
0018-9383/89/0900-1602$01.OO @ 1989 IEEE
MOGHADAM A N D MU: CONTAMINATION A N D DAMAGE O N Si SURFACES
BVG(MED1ANS) AT 1 UM,1 MA,1 MA(R)
A=CONTROL,B= WET,C=PLASMA,D=RIE
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24
20
16
c2
5
2
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grn
12
0
4
0
A
B
C
SPLITS
+
Fig. 1. Gate oxide breakdown voltage ( B V G ) medians at I PA, (initial stress) and I mA (second time) as a function of Si
surface exposure to the different etch conditions.
through high-temperature (1025“C) steam oxidation, and
a SECCO etch was then used to decorate the oxidationinduced surface stacking faults (OSF) formation.
In order to study the thin gate oxide (200-250 A) quality and obtain device-level electron channel mobility data,
a high-temperature TCA oxidation process was used.
n-channel MOS transistors were fabricated using the same
process.
111. RESULTSAND DISCUSSION
A . Gate Oxide Breakdown Voltage
The gate oxide breakdown voltage measurements are
performed on large-area (1 mm2) polysilicon capacitors
by stressing the gate oxide dielectric at three different current levels (1 ps, l mA, and l mA repeat), hereafter defined as the BVG test.
There is a strong dependence of gate oxide quality on
the etching condition/cleaning process used on silicon
surfaces prior to gate ogidation. The quality of the thin
gate oxide (200-220 A) was monitored via the area
breakdown voltage of phosphorus-doped polysilicon gate
capacitors, which is patterned to form a 1-mm2 area. The
performance of the BVG test at three different stress levels (1 pA, 1 mA, and 1 mA repeat) reveals the oxide integrity and defect density levels. Multicurrent BVG testing was employed as a substitute to the time-consuming
Jxt stress. The correlation between the Jxt test (where J
is the current density and t is the time at test) at 1-mA
defect density and the BVG test at 1 mA (repeat) is well
established ( 1 X 10-5/cm2 for BVG at 1 mA (repeat)).
Fig. 1 shows the gate oxide BVG medians at three different stress levels (1 PA, 1 mA, 1 mA (repeat)). A drastic
difference in Fig. 1 is observed between different etching
conditions for 1-mA(R) stress testing. Fig. 2 shows the
gate oxide quality as measured by the defect densities (a
defect is defined as a capacitor with a BVG of less than
14 V). The defects observed at the 1-pA level are known
as “hard defects” while the 1-mA level is indicative of
“intrinsic (latent)” oxide defects.
As can be seen from Fig. 2, the quality of the gate oxide
grown on the RIE-etched surface using the AME-8110
system and CHF, chemistry, as mentioned before, is the
worst when no post-etch surface cleaning process is employed. The lower intrinsic breakdown strength of the oxide grown on the RIE-etched surface is attributed to metallic contamination and polymer formation. The
performance of the SECCO etch for defect decoration indicates a high OSF density (see Section 111-D). The SIMS
analysis of the etched surface indicated an appreciable
concentration of Fe ( 8 X lo”) along with other elements
such as Al, Na, CA, Zn, and K (see Section 111-C).
Comparison of the RIE and PE cases indicates that,
from the standpoint of oxide integrity, RIE-etched surfaces are extremely sensitive to the type of post-etch surface cleaning treatments. Fig. 3 shows that a sulfuric clean
after the etch results in worse oxide latent defect densities
(at 1-mA stress level) compared to an oxygen plasma/sulfuric clean. The addition of an oxygen plasma clean to the
sulfuric clean improves both the “hard defect” and the
‘‘latent defect” densities significantly. A similar result is
observed when a post-etch RCA clean is used (Fig. 4).
The implementation of the RCA clean, which removes
both the polymer and metallic contamination, improves
the breakdown voltage median and results in an improvement in defect densities. As is seen clearly in both Figs.
3 and 4, there is a very strong interaction between the
I601
IEFE TRANSACTIONS ON FLECTRON DEVICES. VOL 36. NO 9. SEPTEMBER 1989
ii n
I
1
A
B
C
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=
=
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VIRGIN SURFACE
WET ETCHED Si SURFACE
PLASM)
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Fig. 2 . Gate oxide defect density as a function of Si surface exposure to the different etch environments.
-.
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POST ETCH SULFURIC CLEAN ONLY
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Fig. 3. Gate oxide integrity as a function of post-etch surface clean treatment, plasma + sulfuric versus sulfuric clean [15].
Fig. 4. Gate oxide integrity (latent defect density) as a function of postetch surface clean treatment, RCA [15].
RIE-exposed Si surface and the post-etch cleans (such interactions are not found with the plasma-etched surfaces).
This strong interaction indicates the presence of a thin
teflon-type polymer formation in the RIE system that gets
removed by either an oxygen clean or an RCA-type clean.
A plasma/sulfuric clean followed by an RCA clean was
adopted in order to restore the Si-surface following the
RIE etch from the standpoint of BVG latent defects.
A more detailed study of the quality of oxide grown on
RIE-exposed Si surfaces revealed the dependence on the
material used in the construction of the RIE chamber. For
example, when the “Lexan” (high-temperature polymer
with glass transition temperature t , = 350°C) is used to
cover the wafer trays in the reactor, as a replacement to
“Ardel,” an exellent gate quality is observed with no interactions between the etch and post-etch cleans. This im-
I605
MOGHADAM A N D MU: CONTAMINATION A N D DAMAGE ON Si SURFACES
1E-2
proved performance is attributed to the cleanliness of
“Lexan” compared to “Ardel,” as confirmed by SIMS
and SECCO etch (see Sections 111-C and 111-E). With the
cleaner wafer tray covers (Lexan), a simple post-etch sulfuric clean is found to be adequate.
B. Electron Channel Mobility Measurements
A device run was fabricated to evaluate the electron
mobility as a function of the etch condition that the Si
surface experiences prior to the thin gate oxide growth.
The measurements were performed on n-channel MOS
transistors. The results are summarized in Table I. The
conclusion made from Table I is that the electron mobility
is improved by about 10 percent for the RIE compared to
the PE case. The improved electron mobility for RIE relates to the high oxide-to-Si substrate etch selectivity (oxide equal to 10-12 : 1 for RIE compared to 1 : 1 for PE),
which leads to a considerably smoother silicon surface.
The channel mobility is increased due to the reduced electron scattering. The Si-surface roughening after PE was
also confirmed by SEM studies.
C . Schottky-Diode Barrier Height Study (I-V)
Measurements
AI-Si (p-type) contacts were employed to evaluate the
Si surfaces after the dry-etching exposure and different
post-etch cleaning procedures. Fig. 5 presents the I-V
characteristics of A1-Si contacts to different Si surfaces.
All the wafers were given a 5 : 1 HF dip for 10 s prior to
A1 metallization in order to remove any native oxide.
Curve a shows the contact to virgin Si surfaces. As can
be seen, the control diode shows very good “ohmic” behavior. The series resistance seen at higher bias is due to
the relatively high resistivity of the substrate, which
agrees well with the literature [16]. Curve b is the I-V
characteristic of the diode made on the PE exposed surfaces. Compared with the control sample, it shows a lower
reverse saturation current. This is believed to be due to
the damage-induced positive charge (i.e., barrier increase), as seen by others [ 171, [ 181. Curve c presents the
I-V characteristics of the diode made on the RIE surface.
It shows a much greater barrier height increase than the
PE case, as judged from the much lower reverse saturation current. Furthermore, under forward bias, the I-V
relation is seen to be severely impeded with a large ideality factor n (about 2.8), indicating the presence of a foreign layer [8]. Different post-RIE cleaning methods, such
as HF dip, H2S04/H202 clean, RCA clean, and
H2S04/H202+ HF, to remove this layer were tried. Fig.
6 shows the results of this effort. As seen from the figure,
judging from the forward bias characteristics of the diode,
the most effective way to remove this foreign layer is to
use H2S04/H202 + HF. This layer was found in a follow-up chemical analysis study (Auger and SIMS) to be
a fluoro-carbon (Teflon-type polymer) layer. Another
point that should be noted is that, even after the removal
of the carbonaceous layer, the barrier increase is still seen
from the rectifying behavior of the diode, indicating the
1E-4
-a
1E-6
1E-8
1E-10
1
0.0
0.2
0.4
0.8
0.6
1.o
(VOLTS)
IFig. 5 . I-V characteristics of AI/Si Schottky-diode fabricated on (curve a )
virgin, (curve b ) PE C,F,-etched, and (curve c ) RIE, CHFJ0,-etched
Si surfaces followed by different post-RIE cleans.
1E-2
1E-4
1E-6
a-
1E-8
0.0
0.2
0.4
0.8
0.6
1.o
(VOLTS)
Fig. 6. I-V characteristics o f AI/Si Schottky-diode fabricated on Si, RIE,
CHFJO, etched Si surfaces followed by different post-RIE cleans.
TABLE I
ELECTRON
CHANNEL MOBILITY
(IN SQUARE CENTIMETER PER VOLT TIMES
SECONDS)
AS A FUNCTION
OF ETCHING
CONDITION
&&s
Mobilitv
(cm2/volt.Sec1
(x f. 3m
I.
Wet Etch
554
2.
Plasma Etch
508
13
3. RIE (30% Overetch)
562
13
4. RIE (60% Overetch)
557 f 6
f
17
IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO 9. SEPrEMBER 1Y89
1606
0
200
400
600
800
1000
1200
1400
1600
E (W
(a)
E (eV)
(b)
Fig. 7. Auger electron spectroscopy (AES) of Si surface exposed to (a) RIE, fluorocarbon polymer formation and (b) PE, no
polymer detected.
presence of the damaged layer. This damage-related barrier increase can give rise to the increased contact resistance. However, it can be annealed out at temperatures
>800°C [17]. This means that if the polymer layer is
properly removed after etching, the damage can be annealed out during subsequent high-temperature step(s).
D. Surface Analysis
I ) Auger Electron Spectrocopy (AES): This surface
analysis technique was used to determine the amount of
polymeric layer formation during the etching process. The
effectiveness of different polymer removal techniques was
also examined. The RIE surfaces show significantly more
polymer than PE (Fig. 7(a) and (b)). This difference is
believed to be caused by the type of etch chemistry employed, The Auger depth profile indicated the film to be
30 A thick. It was identified that the carbon content of
the H2S04/H202 wet-dipped wafer was considerably less
than the nondipped wafers. Consistent with the electrical
data presented in Sections III-A and III-C, no carbon was
detected on the surface after either oxygen plasma clean
plus sulfuric clean or RCA clean.
2) Seconduly Ion Mass Spectroscopy (SIMS): Secondary ion mass spectroscopy (SIMS) using 0: primary ion
bombardment (positive SIMS) with the detection range for
most elements of 0.1-100 ppm (atomic) was used. For
this experimentation, a low primary beam current was
used to enable the analysis of the near-surface regions of
-
I607
MOGHADAM A N D M U : CONTAMINATION A N D DAMAGE O N Si SURFACES
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0.6
0.8
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DEPTH (MICRONS)
(d)
Fig. 8. SIMS analysis of Si surface exposed to (a), (b), PE, some AI detected and (c), (d) RIE, both AI and Fe observed
the wafers. Mass survey spectra (static SIMS) were also
obtained from various samples. The samples were capped
with 4000 A of poly Si to help the initial beam stabilization and noise elimination for the SIMS analysis. The
dynamic SIMS (depth profile) for A1 and Fe for both RIE
and PE exposed surfaces is shown in Fig. 8(a)-(d). The
presence of A1 is attributed to the anodized A1 cathode
used in the construction of both RIE and PE reactor. The
I608
IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO Y, SEPTEMBER 1989
A1 level observed on the Si surface for the RIE condition
is two orders of magnitude higher than that for PE ( 3 X
10l6 atoms/cm3 for PE versus 3 X 10” atoms/cm3 for
RIE). The higher A1 level for the RIE case relates to the
high degree of ion bombardment.
Comparison of the depth profile for heavy metal contamination on the Si surface shows nondetectable quantities for Fe, but a substantial amount of Fe for RIE ( 8 X
10” atoms /cm3 ). This concentration of Fe persists even
after the H2S04/H202clean is applied. The source of
heavy metals for the RIE system is thought to be the stainless-steel parts (gas distribution tube, screws, gas diffusors, etc.) used inside the reactor for various functions as
well as wafer tray covers.
In addition to A1 and Fe, other elements, such as Ca,
Na, K, and Zn, showed up on the SIMS surface mass scan
for the RIE case. The source of these kinds of impurities
was found to be the polymeric material used in covering
the wafer trays and hexode in the RIE system (Ardel). By
switching to an alternative material that is cleaner
(Lexan), the traces of the elements Ca, Na, K, and Zn
disappear. The presence of heavy metals contamination
for RIE was confirmed by SECCO etch decoration as indirect evidence (see Section 111-E).
E. Defect Decoration (SECCO Etch Study)
Some etched Si wafers, both PE and RIE as well as wet
HF etched, were sent through a 1025°C steam oxidation
cycle for about 2 h, which led to the growth of 6500 A
of oxide. It is well known that during high-temperature
steam oxidation, surface stacking faults would form if
there were any nucleation seeds such as those provided by
1) a metallic impurity, 2) severe lattice damage due to
high dose and high energy ion implant, 3) some localized
stress, or 4) heavy B doping, present in the surface region
during the oxidation. These stacking faults can be decorated by removing the oxide and subsequently using the
SECCO etch technique [4]. Fig. 9 shows an optical micrograph of the RIE-exposed 5-pm-long Si surface after
oxidation and SECCO etch. Surface stacking faults with
high density (about 1.8 X 106/cm2) are present on this
surface. The similar procedure on a PE-exposed wafer
leads to a very clean surface with no OSF detected. The
origin of the OSF could be the metallic contamination or
the polymer layer left after etching. To identify which is
the case, different cleaning methods, such as H2S04/H202
clean, RCA clean (SCl, SC2, or SCl
SC2), HF dip,
as well as H2S04/H202 HF dip, were employed as the
post-etch cleaning step prior to high-temperature steam
oxidation. As discussed in Section 111-C, the H,S04/H202
HF dip was very effective in removing the polymer
layer as judged from the Schottky-diode I-V characteristics. However, none of the above cleaning methods was
able to eliminate the OSF or even to reduce its density.
This led us to believe that the surface stacking faults must
be due to the heavy metallic contaminations (Fe, Cr) that
were detected by SIMS. The reason why even an RCA
clean could not remove the Fe is because the Fe atoms (or
+
+
+
Fig. 9. Optical image of Si surface after exposure to RIE and SECCO etch
decoration. The presence of 5-wm-long stacking faults are noted ( 1000
x magnification).
TABLE I1
MINORITY-CARRIER
GENERATION
LIFETIME
( T 3 ) FOR DIFFERENT
WAFERS
ETCH CONDITIONS
v
Virgin Si
79-131
RIE (Ardel)
<I
RIE (Lexan)
35-60
PE (C2F,)
220
PE (C$)
29-145
ions) are not at the top surface of the wafer after etching,
and they must have already peTeated into the Si near the
surface region (say about 100 A or so).
F. Minority-Carrier Generation Lifetime Study (C-t
Measurements)
MOS structures with a guard ring for isolation of MOS
capacitors were employed to measure the minority-carrier
generation time in the depletion region on the dry-etchprocessed wafer surfaces [19]. It is well known that minority-carrier generation lifetime is very sensitive to or is
determined by heavy metal contamination present on the
wafer since they possess deep states in the Si bandgap.
Table I1 presents the measured minority-carrier generation lifetime on control and variously etched wafers. Since
the target number of our incoming material is >50 ps,
any measurement greater than that value is considered
clean of process-induced metallic Contamination. From
Table 11, we can conclude that all the etched wafers, except those RIE etched with the “Ardel” material, are free
of any carrier-lifetime-killing contamination (metallics).
IV. CONCLUSION
The following conclusions can be drawn from this
work:
1) There is a strong dependence of gate oxide quality
on the etchinglcleaning process used on silicon surfaces
prior to gate oxidation. RIE exposed surfaces are especially sensitive to the post-etch cleaning step.
I609
MOGHADAM AND MU: CONTAMINATION AND DAMAGE ON Si SURFACES
2) The electron mobility in NMOS transistors is shown
to be affected by the type of dry-etching techniques used.
The roughening of the Si surface after PE exposure is believed to cause the degradation of the electron mobility.
RIE exposure, on the other hand, did not degrade the
electron mobility.
3) It was again confirmed in this study that Si lattice
damage can induce a positive charge that enhances the
M/S barrier height in p-type Si and decreases the M/S
barrier height in n-type Si. Also, the presence of the polymeric layer after a high Si02-Si selectivity RIE was detected via the Schottky-diode I-V characteristics.
4) AES and SIMS chemical/analytical techniques revealed that a fluoro-carbon polymer film formed on Si surfaces as a result of high Si02-Si selectivity RIE. Metal
impurities such as Fe, Al, Cr, Na, K, and Zn permeated
into Si substrates upon RIE exposure. The source of the
metal impurities is confirmed to be the cover material of
the wafer tray in the RIE machine used.
5 ) The metal impurities permeating into the Si substrate during RIE can cause crystalline defects (surface
stacking faults) in the subsequent high-temperature oxidation steps. No matter what post-RIE cleaning method
was used, the surface stacking faults were still present,
indicating that the metal impurities were already embedded in the Si substrate after RIE exposure.
6) These metal impurities can, in turn, degrade device
characteristics, such as gate oxide quality and minoritycarrier generation lifetime.
ACKNOWLEDGMENT
Appreciation is given in H . Tran for her technical assistance, to P. Davis for SIMS and AES analysis, and to
R. V . Giridhar and G. Wada for GOM and mobility test
data.
[7] M. Matsumoto and T . Sugano, J. Electrochem. Soc., vol. 129, p.
2823, 1982.
[8] X . C . Mu et al., J . Appl. Phys. vol. 59, p. 2958, 1986.
[9] M. Oshima, Surface Sci., vol. 86, p. 858, 1979.
[IO] L. M. Ephrath and R. S . Benett, J. Electrochem. Soc., vol. 129, p.
1822, 1982.
[ 1 I ] S . W. Pang, D. D. Rathman, D. J. Silversmith, R. W. Mountain, and
P. D. DeGraff. J. Appl. Phys., vol. 54, p. 3272, 1983.
[I21 G. S . Oehrlein, R. M. Tromp, J. C. Tsang, Y. H. Lee, and E. J .
Petrillo, J . Electrochem. Soc., vol. 132, p. 1443, 1985.
[I31 H. 0. BIom er a l . , J . Vac. Sci. Technol. A , vol. 4, MaylJune 1986.
[14] X. C. Mu et nl., J . Appl. Phys., vol. 58, Dec. 1985.
[I51 F. Moghadam, R. V. Giridhar, G. Wada, S. Nozaki, Intel Internal
Tech. Memo, May 1987.
[I61 S . M. Sze, Physics of Semiconductor Devices, 2nd ed. New York:
Wiley, 1981.
[I71 S . J . Fonash, SolidState Technol., vol. 28, p. 201, 1985.
(181 X. C . Mu and S . J. Fonash, IEEE Elecrron Device Lett., vol. EDL6, p. 410, 1985.
[I91 S . W. Pang, Solid State Technol., vol. 27, p. 249, 1984.
1201 S . I . Fonash et al., J . Appl. Phys., vol. 58, p. 862, 1985.
Farhad K. Moghadam received the B.S. degree
in metallurgy from the Tehran University of Technology, Iran, in 1977 and the M.S. and Ph.D. degrees in materials science and engineering from
Stanford University in 1979 and 1981, respectively.
He joined Intel Corporation in 1981, and until
April 1984, he worked on a number of assembly
technology development projects as a Senior Engineer. In April 1984, he joined Intel’s Wafer
Processing Development Group and was involved
with various programs such as the application of polymides as interlayer
dielectrics in SRAMS/static logics, plasma etching of 1.5-pm technology
with advanced end-point detection system, and isolation schemes for submicrometer feature sizes. He is currently involved in the Submicron
EPROM Technology Development Group at Intel as a Staff Process Engineer, working on etch and CVD projects.
*
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L. M. Ephrath and D. J. Maria, J . Electrochem. Soc., vol. 123, p.
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T . Hosoya, Y. Ozaki, and K. Hirata, J. Electrochem. Soc., vol. 132,
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Xiao-Chun Mu ieceived the B.S.degree in physics from Nankai University, China, in 1981 and
the Ph.D. degree in solid-state physics from the
Pennsylvania State University in 1986.
He joined Intel Corporation as a Senior Engineer in 1986 and is currently working in the Submicron EPROM Technology Development Group.
His research interests are in the areas of solid-state
devices, materials, and VLSI processing, especially dry-etching-related damage and contamination. He has published more than a dozen papers in these fields and holds one patent.