商业运营计划
Xiaohua （ Paul ） Huang
CMOS Micro Device Inc www.ec-chip.com

List of Content
•   Introduction
•   Differential TCAM cells
•   Differential Match line sensing circuit
•   Multi-level Hit ahead Hierarchical Priority encoding
•   Sample Design

Introduction
Content-addressable memory (CAM) is used for parallel searching applications.
Binary CAM is the simplest type of CAM which uses data search words consisting entirely of 1s and 0s.
Ternary CAM (TCAM) allows a third matching state of "X" or "don't care" for one
or more bits in the stored data word, thus adding flexibility to the search.
For example, a ternary CAM might have a stored word of "1 0 X X 0“
which will match any of the four search words "1 0 0 0 0",
"1 0 0 1 0",
"1 0 1 0 0",
"1 0 1 1 0".
The added search flexibility comes at an additional cost over binary CAM
as the internal memory cell must now encode three possible states instead of
the two of binary CAM.
This additional state is typically implemented by adding a mask
bit ("care" or "don't care" bit) to every memory cell.

CAM/TCAM block

CAM cell

CAM match sensing circuit
Single Match line , slow when more bits

Differential match sensing
Differential match （ hit ） line sensing , faster

Differential TCAM cell
Differential match （ hit ） line TCAM cell

Dummy Differential TCAM cells
Dummy Differential TCAM cell, valid bit

Dummy differential CAM cell
Dummy Differential CAM cell

High speed differential sensing
High speed differential match （ hit ） line sensing circuit

Wave Form
High speed differential match （ hit ） line sensing voltage signal

Low power differential TCAM sensing
Low power differential match （ hit ） line sensing circuit

Wave Form
Low power differential match （ hit ） line sensing voltage signal

Hierarchical Structure
High Density TCAM are divided into many block, arranged in column and row, for high speed hierarchical priority encoding.

hierarchical priority encoding
H
0
=A
0
H
1
=H
0
* A
1
= A
0
* A
1
H
2
= H
1
* A
2
= A
0
* A
1
* A
2
H n
= H n-1
* A n

hierarchical priority encoding

Hierarchical priority encoding
Second Level Priority Encoding

Dynamical Priority encoding circuit
Priority Encoding circuit

Fast Hit Generation
two level hit generation circuit

MUX selection circuit
MUX circuit

1. 90nm TSMC process, divided into 64-block, at 250 Million look up/s
( 250MHz)
Power =8.78 W, die size = 1.4 X1.5 = 2.1 CM ^2
---------------------------------------------------------------------------------------------------------------
2.
40nm TSMC process, divided into 128- block, each block 1K X 160 bit
With priority encoding built in.
Designed with logic rule( TCAM cell is designed in logic rule)
Die size: 46.8 mm^2
power is 17 W at 1GHz speed at typical corner.
speed at typical corner is above 1.0 GHz.
Two cycle delay.

Sample Design
65nm SMIC TCAM
test chip
40nm TCAM IP

1.
Differential TCAM cell and differential match line(hit line) sense circuit achieve high speed and low power,
make TCAM design circuit same as SRAM
2.
Hierarchical priority encoding logic make the high density
TCAM + priority encoding circuit design structural and fast.
3. Combine 1 and 2 , it is convenient to build TCAM compiler and design high density and high speed TCAM.

Reference
1. US patents: 6744653 ， 2004.6.1
“CAM cells and differential sense circuits for content addressable 　 memory(CAM)“
2. US patents.: 7,652,903 ， 2010.1.26 ，
“HIT AHEAD HIERARCHICAL SCALABLE PRIORITYENCODING
LOGIC AND CIRCUITS“