Anode LCT 2000 Design Abstract
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Anode LCT 2000 Design UCLA High Energy Physics Version 2.1 October 4, 2000 Abstract This document describes the UCLA Anode Local Charged Track board, version 2000. Signals to and from the other modules that comprise the system are specified in detail, including all data bits and connector pins that involve the ALCT2000 board. Information is also included for the modified LCT99Passthru module that provides temporary connections to the existing pre-backplane versions of the Clock and Control Board (CCB), Trigger Motherboard (TMB), and DAQ Motherboard (DAQMB). The Cathode LCT99 module that reads Cathode Front-End-Board data and performs CLCT pattern finding is described elsewhere.1 ALCT2000 Functionality The ALCT2000 board is a 3rd generation design that finds Anode Local Charged Tracks in a Cathode Strip Chamber. This board is an interim design that is close to the final production version. The main differences from the production version have to do with the data output cable and connector, associated driver/receiver chips, and radiation upset recovery. General Features ALCT2000-384 CSC Coverage Per Module 24 ADB (Full CSC) FEB Data Signals CLCT99 5 CFEB (Full CSC) Discrete LVDS LVDS C-Link Module Form Factor Circuit-board 9U VME 400 Computer Interface JTAG Altera 10K100E Ball Grid Array None Altera 10K200E Pin Grid Array ALCT2000-384 CLCT99 FEB Data Compression None 4-to-1 Pattern Finding Logic FPGA FPGA Muons Per Trigger Per CSC Best 2 Best 2 Yes Link To DAQMB and via JTAG 1 Event Yes Link To DAQMB None None FPGA Technology Performance Features Seamless FEB Boundaries Raw Hits Dump Event Buffer2 3 Radiation Damage Recovery 1 Event 1 UCLA High Energy Physics Group, 'LCT99 Prototype Design', 9/23/99, ftp://cos.physics.ucla.edu/pub/cms/ The production version will have 4 event buffers. 3 Singe Event Upset radiation damage will be cured by periodic FPGA refresh from on-board FlashRAM. 2 Page 1 of 104 11/01/00 10:05 AM Table of Contents ABSTRACT....................................................................................................................................................................... 1 ALCT2000 FUNCTIONALITY ............................................................................................................................................ 1 TABLE OF CONTENTS ....................................................................................................................................................... 2 LIST OF FIGURES .............................................................................................................................................................. 6 LIST OF TABLES ............................................................................................................................................................... 7 SYSTEM OVERVIEW ..................................................................................................................................................... 9 SYSTEM DIAGRAM ........................................................................................................................................................... 9 ADB......................................................................................................................................................................... 10 CFEB ....................................................................................................................................................................... 10 ALCT 2000.............................................................................................................................................................. 10 LCT99-Passthru ....................................................................................................................................................... 10 CLCT99................................................................................................................................................................... 10 CCB......................................................................................................................................................................... 11 DAQMB .................................................................................................................................................................. 11 TMB ........................................................................................................................................................................ 11 ALCT2000 OVERVIEW................................................................................................................................................. 12 ALCT2000 COMPONENTS.............................................................................................................................................. 12 ADB I/O Connector.................................................................................................................................................. 13 Delay ASIC.............................................................................................................................................................. 13 LCT[0-3] FPGAs...................................................................................................................................................... 13 LCT Data Bus .......................................................................................................................................................... 13 FIFO Address Bus .................................................................................................................................................... 13 FIFO Data Bus ......................................................................................................................................................... 13 Concentrator FPGA .................................................................................................................................................. 13 CFG EEPROM......................................................................................................................................................... 13 Slow Control FPGA ................................................................................................................................................. 13 ALCT Control Bus ................................................................................................................................................... 13 Altera FlashRAMs.................................................................................................................................................... 14 Channel Links .......................................................................................................................................................... 14 DACs ....................................................................................................................................................................... 14 ADCs ....................................................................................................................................................................... 14 Test Pulse Generator................................................................................................................................................. 14 Power Supply ........................................................................................................................................................... 14 Configuration JTAG Connector ................................................................................................................................ 14 Altera Programming JTAG Connector ...................................................................................................................... 14 ANODE DISCRIMINATOR BOARD ............................................................................................................................ 15 ADB OVERVIEW ........................................................................................................................................................... 15 ADB CHANNEL MAPPING .............................................................................................................................................. 15 Mapping CSC Wire Groups to LCT Bit Number ....................................................................................................... 15 ADB Card Wire Groups............................................................................................................................................ 16 ADB-ALCT2000 Signals.......................................................................................................................................... 17 DELAY ASIC .................................................................................................................................................................. 18 OVERVIEW .................................................................................................................................................................... 18 Programming............................................................................................................................................................ 18 Delay ASIC Signals.................................................................................................................................................. 18 ALCT2000 LOGIC AND ALGORITHMS ..................................................................................................................... 19 LCT FPGA LOGIC......................................................................................................................................................... 19 ADB......................................................................................................................................................................... 19 Delay ASIC.............................................................................................................................................................. 19 Latch Mask .............................................................................................................................................................. 19 Pattern Injector ......................................................................................................................................................... 20 Page 2 of 104 11/01/00 10:05 AM WG One-Shot........................................................................................................................................................... 21 FEB Exchange.......................................................................................................................................................... 21 Plane OR.................................................................................................................................................................. 21 Pattern Hits .............................................................................................................................................................. 22 Priority Encoder ....................................................................................................................................................... 22 LCT FIFO ................................................................................................................................................................ 23 FIFO Mux ................................................................................................................................................................ 23 ALCT JTAG ............................................................................................................................................................ 23 Logic Cells............................................................................................................................................................... 24 LCT I/O Signals ....................................................................................................................................................... 25 CONCENTRATOR FPGA LOGIC ....................................................................................................................................... 26 Resolver ................................................................................................................................................................... 27 Priority Encoder ....................................................................................................................................................... 27 Best 2 of 3 ................................................................................................................................................................ 27 Best 2 of 4 ................................................................................................................................................................ 27 Pattern Pre-Trigger ................................................................................................................................................... 27 Sequencer................................................................................................................................................................. 28 FIFO Control............................................................................................................................................................ 30 CCB......................................................................................................................................................................... 30 Defaulter .................................................................................................................................................................. 31 JTAG Acon .............................................................................................................................................................. 31 JTAG FIFO .............................................................................................................................................................. 31 EEPROM ................................................................................................................................................................. 31 Logic Cells............................................................................................................................................................... 32 Concentrator I/O Signals........................................................................................................................................... 33 SLOW CONTROL FPGA............................................................................................................................................... 35 SLOW CONTROL OVERVIEW ........................................................................................................................................... 35 SLOW CONTROL FPGA LOGIC ....................................................................................................................................... 36 Serial Bus................................................................................................................................................................. 36 JTAG Functions ....................................................................................................................................................... 36 Slow Control I/O Signals .......................................................................................................................................... 37 LATENCY....................................................................................................................................................................... 38 ADB......................................................................................................................................................................... 38 LCT + Concentrator ................................................................................................................................................. 38 DAQMB Transmission............................................................................................................................................. 38 DATA FORMATS........................................................................................................................................................... 39 TMB DATA FORMAT ..................................................................................................................................................... 39 TMB Data Summary................................................................................................................................................. 39 TMB Channel Link Bits ........................................................................................................................................... 40 DAQMB DATA FORMAT ............................................................................................................................................... 42 Transmission Sequence............................................................................................................................................. 42 FIFO Dump Modes................................................................................................................................................... 42 DAQMB FIFO Control............................................................................................................................................. 43 DDU Special Words ................................................................................................................................................. 43 LCT Special Words .................................................................................................................................................. 43 Header Frames ......................................................................................................................................................... 44 Time Bin Frames...................................................................................................................................................... 45 Trailer Frames .......................................................................................................................................................... 45 DAQMB Data Format Example................................................................................................................................ 46 DAQMB Channel Link............................................................................................................................................. 47 DAQMB Channel Link Bits...................................................................................................................................... 48 CLOCK & CONTROL BOARD DATA FORMAT ................................................................................................................... 49 CCB Signal Summary............................................................................................................................................... 49 PROGRAMMING........................................................................................................................................................... 50 Page 3 of 104 11/01/00 10:05 AM MANUAL CONFIGURATION ............................................................................................................................................. 50 JTAG CONFIGURATION ................................................................................................................................................. 51 CONCENTRATOR JTAG PROGRAMMING.......................................................................................................................... 52 TAP Controller......................................................................................................................................................... 52 JTAG TAP States ..................................................................................................................................................... 53 Concentrator Instruction Register.............................................................................................................................. 54 Concentrator ID Register .......................................................................................................................................... 54 Concentrator Control Register................................................................................................................................... 55 Concentrator Trigger Register................................................................................................................................... 57 Concentrator CSC ID Register .................................................................................................................................. 57 Concentrator Raw Hits Status Register...................................................................................................................... 57 Concentrator Raw Hits Data Register........................................................................................................................ 58 Concentrator Bypass Register ................................................................................................................................... 58 LCT JTAG PROGRAMMING ........................................................................................................................................... 59 LCT Instruction Register .......................................................................................................................................... 59 LCT ID Register....................................................................................................................................................... 59 LCT Control Register ............................................................................................................................................... 60 LCT Hot Channel Mask............................................................................................................................................ 60 LCT Arbitrary Test Pattern Register ......................................................................................................................... 61 LCT Inject Test Pattern ............................................................................................................................................ 61 LCT Bypass Register................................................................................................................................................ 61 SLOW CONTROL JTAG PROGRAMMING .......................................................................................................................... 62 Slow Control Instruction Register ............................................................................................................................. 62 Slow Control ID Register.......................................................................................................................................... 63 Reset Threshold DAC............................................................................................................................................... 63 Reset Delay ASIC..................................................................................................................................................... 63 Write Test Pulse DAC .............................................................................................................................................. 63 Write Threshold DAC(i, i=0..3)................................................................................................................................ 63 Read Threshold ADC(i, i=0..4)................................................................................................................................. 64 Write Delay ASIC Group(i, i=0..6)........................................................................................................................... 66 Write Test Pulse Group............................................................................................................................................. 66 Read Test Pulse Group ............................................................................................................................................. 66 Write Test Pulse Strip............................................................................................................................................... 66 Read Test Pulse Strip................................................................................................................................................ 67 Write Standby Register............................................................................................................................................. 67 Read Standby Register.............................................................................................................................................. 67 Write TP Power Down.............................................................................................................................................. 67 Read TP Power Down .............................................................................................................................................. 67 Bypass Scan ............................................................................................................................................................. 67 ALTERA DEVICE PROGRAMMING .......................................................................................................................... 68 ALTERA FPGAS ............................................................................................................................................................ 68 ALTERA FLASH MEMORY ............................................................................................................................................... 68 ALTERA PROGRAMMING JTAG CHAIN ........................................................................................................................... 68 CONFIGURATION JUMPERS...................................................................................................................................... 69 DIAGNOSTICS ............................................................................................................................................................... 70 LED DISPLAY ............................................................................................................................................................... 70 TEST POINTS.................................................................................................................................................................. 71 POWER REQUIREMENTS ........................................................................................................................................... 74 ALCT2000 CONNECTORS............................................................................................................................................ 75 J1-J6 Strip Test Pulse Outputs................................................................................................................................... 75 J7 Power Connector.................................................................................................................................................. 75 J8 Altera LVDS ByteBlaster..................................................................................................................................... 76 J9 Configuration LVDS JTAG.................................................................................................................................. 76 Page 4 of 104 11/01/00 10:05 AM J10 TMB Channel Link ............................................................................................................................................ 77 J11 DAQMB Channel Link ...................................................................................................................................... 78 J12 Analog Test Pulse Trigger Input ......................................................................................................................... 78 J13-J36 ADB I/O...................................................................................................................................................... 79 LCT99-PASSTHRU MODULE ...................................................................................................................................... 80 LCT99 OVERVIEW......................................................................................................................................................... 80 LCT99 LOGIC ................................................................................................................................................................ 81 LCT99-Passthru Mod ............................................................................................................................................... 81 Shadow Sequencer.................................................................................................................................................... 81 TMB ........................................................................................................................................................................ 81 DAQMB .................................................................................................................................................................. 82 CCB......................................................................................................................................................................... 82 Level 1 Accept ......................................................................................................................................................... 82 ECL Inputs............................................................................................................................................................... 83 ECL Outputs ............................................................................................................................................................ 85 LCT99 CONFIGURATION............................................................................................................................................ 86 Configuration DIP-Switch SW14.............................................................................................................................. 86 CCB Mode Switch [SW11 Board ID] ....................................................................................................................... 87 L1A Delay Switches [SW4=MSB, SW3=LSB] ......................................................................................................... 87 L1A Output Source Switch [SW5 L1A_Window] ..................................................................................................... 87 LED Display Mode Switch [SW12 CSC ID} ............................................................................................................ 88 LED Display ............................................................................................................................................................ 88 LCT99 Configuration Shunts .................................................................................................................................... 89 LCT99 Circuit Board Probe Points............................................................................................................................ 90 LCT99-PASSTHRU MODULE CONNECTORS........................................................................................................... 91 FEB0 ßà ALCT2000 J10....................................................................................................................................... 91 FEB4 ßàALCT2000 J11 ....................................................................................................................................... 92 J5 DAQMB .............................................................................................................................................................. 93 J6 TMB.................................................................................................................................................................... 94 J7 CCB..................................................................................................................................................................... 95 J8 ECL Out .............................................................................................................................................................. 96 Table 80: LCT99 ECL Output Connector.................................................................................................................. 96 J9 ECL In................................................................................................................................................................. 96 J10 ByteBlaster ........................................................................................................................................................ 97 OPERATING PROCEDURES ....................................................................................................................................... 98 SYSTEM CABLES ............................................................................................................................................................ 98 LCT99-PASSTHRU CONFIGURATION ............................................................................................................................... 98 LCT99 Switch Settings............................................................................................................................................. 98 LCT99 Shunt Settings............................................................................................................................................... 99 ALCT2000 CONFIGURATION ........................................................................................................................................100 Switch Settings........................................................................................................................................................100 LEVEL 1 ACCEPT ..........................................................................................................................................................101 L1A Source .............................................................................................................................................................101 L1A Time-in Procedure ...........................................................................................................................................102 FAQS ..............................................................................................................................................................................103 KNOWN PROBLEMS ...................................................................................................................................................104 REVISION HISTORY ...................................................................................................................................................104 Page 5 of 104 11/01/00 10:05 AM List of Figures Figure 1: System Diagram ......................................................................................................................9 Figure 2: ALCT2000 Components........................................................................................................12 Figure 3: LCT FPGA Logic ..................................................................................................................19 Figure 4: Injector Test Pattern Cell with 6 Collision Muon Hits on Wire-Group 5: ...............................20 Figure 5: Injector Test Pattern Cell with 6 Accelerator Muon Hits on Wire-Group 5: ...........................20 Figure 6: Wire-Groups Exchanged by Adjacent LCT Chips:.................................................................21 Figure 7: Collision-Muon Pattern Cell: .................................................................................................21 Figure 8: Accelerator-Muon Pattern Cell: .............................................................................................22 Figure 9: Concentrator FPGA Logic .....................................................................................................26 Figure 10: Slow Control Serial Bus.......................................................................................................35 Figure 11: Raw Hits Readout Sequence ................................................................................................45 Figure 12: Configuration JTAG Chain ..................................................................................................51 Figure 13: TAP State Machine..............................................................................................................52 Figure 14: Programming JTAG Chains.................................................................................................68 Figure 15: ALCT2000 Power Connector ..............................................................................................75 Figure 16: LCT99 Overview.................................................................................................................80 Figure 17: Level 1 Accept Signals On ALCT2000 PCB......................................................................102 Page 6 of 104 11/01/00 10:05 AM List of Tables Table 1: Mapping CSC Wire Groups to LCT Bit Number.....................................................................15 Table 2: ADB Card Wire Groups..........................................................................................................16 Table 3: ADB-ALCT2000 Signals........................................................................................................17 Table 4: Delay ASIC Signals ................................................................................................................18 Table 5: Injector Test Pattern Modes ....................................................................................................20 Table 6: Priority Encoder Modes ..........................................................................................................22 Table 7: ALCT Control Bus..................................................................................................................23 Table 8: LCT Logic Cells .....................................................................................................................24 Table 9: LCT I/O Signals......................................................................................................................25 Table 10: Pattern Pre-Trigger Modes ....................................................................................................28 Table 11: Anode Quality Number .........................................................................................................28 Table 12: Sequencer States ...................................................................................................................30 Table 13: JTAG FIFO Time Bin Limits ................................................................................................31 Table 14: Concentrator Logic Cells ......................................................................................................32 Table 15: Concentrator I/O Signals.......................................................................................................33 Table 16: Concentrator I/O Signals [Continued] ...................................................................................34 Table 17: Slow Control I/O Signals ......................................................................................................37 Table 18: ALCT2000-to-TMB [via LCT99-Passthru] Data Summary ...................................................39 Table 19: ALCT2000–To-TMB [Via LCT99-Passthru] LVDS Channel Link0 Bits ..............................40 Table 20: ALCT2000–To-TMB [Via LCT99-Passthru] LVDS Channel Link0 Bits ..............................41 Table 21: Anode LCT FIFO Full-Dump Bit Count ...............................................................................43 Table 22: DAQMB: FIFO Control Bits.................................................................................................43 Table 23: DDU Special Words .............................................................................................................43 Table 24: LCT Special Words...............................................................................................................43 Table 25: Header Frame Data ...............................................................................................................44 Table 26: Time Bin Format...................................................................................................................45 Table 27: Trailer Frame Data................................................................................................................45 Table 28: Full-Dump Mode Data Format Example ...............................................................................46 Table 29: DAQMB Channel Link Summary .........................................................................................47 Table 30: ALCT2000–To-DAQMB [Via LCT99-Passthru] LVDS Channel Link Bits ..........................48 Table 31: Clock & Control Board Signal Summary ..............................................................................49 Table 32: Configuration JTAG Chain ...................................................................................................51 Table 33: TAP Controller States ...........................................................................................................53 Table 34: Concentrator JTAG Instruction Op Codes.............................................................................54 Table 35: Concentrator ID Register ......................................................................................................54 Table 36: Concentrator Control Register...............................................................................................55 Table 37: Concentrator Trigger Register...............................................................................................57 Table 38: Concentrator Raw Hits Status Register..................................................................................57 Table 39: Concentrator Raw Hits Status Register..................................................................................58 Table 40: LCT JTAG Instruction Op Codes..........................................................................................59 Table 41: LCT ID Register ...................................................................................................................59 Table 42: LCT Control Register............................................................................................................60 Table 43: LCT Hot Channel Mask [1=enable a WG] ............................................................................60 Table 44: LCT Arbitrary Test Pattern Register [1=enable a WG]..........................................................61 Table 45: Slow Control JTAG Instruction Op Codes ............................................................................62 Table 46: Slow Control ID Register......................................................................................................63 Page 7 of 104 11/01/00 10:05 AM Table 47: Threshold DAC Channel Assignments ..................................................................................64 Table 48: ADC0 Channel Assignments.................................................................................................64 Table 49: ADC1 Channel Assignments.................................................................................................65 Table 50: ADC2 Channel Assignments.................................................................................................65 Table 51: Delay ASIC Group Assignments...........................................................................................66 Table 52: Analog Test Pulse ADB Group Assignments ........................................................................66 Table 53: Programming JTAG Chain Modes ........................................................................................68 Table 54: ALCT2000 PCB Jumpers......................................................................................................69 Table 55: Concentrator LED Displays ..................................................................................................70 Table 56: Power Supply LED Displays.................................................................................................70 Table 57: Test Points ............................................................................................................................71 Table 58: Power Supply Current [ALCT2000-384]...............................................................................74 Table 59: Power Estimate for ALCT2000 Variants...............................................................................74 Table 60: ALCT2000 Connectors .........................................................................................................75 Table 61: J8 Altera LVDS ByteBlaster Connector ................................................................................76 Table 62: J9 Configuration LVDS ByteBlaster Connector ....................................................................76 Table 63: J10 TMB Channel Link Connector........................................................................................77 Table 64: AMP SCSI Connector 26HD Pin Locations [View From PCB Top]......................................77 Table 65: J11 DAQMB Channel Link Connector..................................................................................78 Table 66: J13-J36 ADB I/O Connector .................................................................................................79 Table 67: LCT99 Configuration Switch SW14 .....................................................................................86 Table 68: LCT99 CCB Mode Switch [SW11].......................................................................................87 Table 69: L1A Output Source [SW5]....................................................................................................87 Table 70: LED Display Mode Switch [SW12] ......................................................................................88 Table 71: LCT99 LED Display.............................................................................................................88 Table 72: LCT99-Passthru Configuration Shunts..................................................................................89 Table 73: LCT99-Passthru Circuit Board Probe Points .........................................................................90 Table 74: FEB0 ßà ALCT2000 J10 Connector ................................................................................91 Table 75: AMP SCSI Connector 26HD Pin Locations [View From PCB Top]......................................91 Table 76: FEB4 ßà ALCT2000 J11 Connector ................................................................................92 Table 77: LCT99-to-DAQMB LVDS Channel Link Connector ............................................................93 Table 78: LCT99-to-TMB LVDS Channel Link Connector ..................................................................94 Table 79: LCT99 Clock & Control Board Connector............................................................................95 Table 80: LCT99 ECL Output Connector .............................................................................................96 Table 81: ECL Input Connector............................................................................................................96 Table 82: LCT99 ByteBlaster Connector ..............................................................................................97 Table 83: LCT99 SW14 Normal Settings..............................................................................................98 Table 84: LCT99 Hex Switch Normal Settings .....................................................................................98 Table 85: LCT99 Normal Shunt Settings ..............................................................................................99 Table 86: ALCT2000 Normal SW11 Switch Settings .........................................................................100 Table 87: ALCT2000 PCB Jumpers Normal Setting ...........................................................................100 Page 8 of 104 11/01/00 10:05 AM System Overview System Diagram Figure 1: System Diagram 1st LCT[27..0] ALCT2000 40 MHz Clock ECL Ext_Trig Test Pulse ECL Ext_Inject Active FEB Flag Active FEB[6..0] FIFO[20..0] BX0 BXReset L1Accept Ext_Inject Ext_Trig LCT99 Passthru ECL Test_Pulse -------------- FEB4 -------------- ADB23 18,23,41 ECL Clock 2nd LCT[27..0] --------------- J11 --------------- ADB0 16-Wire Groups +5.5V -4.3V Vthreshold Test Pulse /Standby Out[15..0] ECL Test_Pulse ECL xDAQMB ECL L1Accept ECL DAQMB/wr ECL xTMB ECL InvPat ECL SeqBusy ECL Active FEB Rear Panel Channel Links Active aFEB[6..0] ---- J5 ---aFEB Flag 2nd aLCT[27..0] -- J6 -- 1st aLCT[27..0] J7 CCB 40MHz Clock L1Accept BxReset Bx0 TMB 96 Strips = 48 ½-Strip Triads cFEB[4..0] ECL Clock ECL Ext_Inject Triad[23..0] ECL Cmp_Reset Triad[47..24] ECL Ext_Trig CLCT99 CFEB4 [3,4] cFEB Flag Rear Panel Channel Links Reset Front Panel ECL I/O CFEB0 aLCT[27..0] VME Backplane aLCT[27..0] 40 MHz Clock DAQMB ECL xTMB ECL L1A Window ECL L1Accept ECL InvPat ECL Seq Busy ECL Pretrig ECL Halt ECL xDAQMB Page 9 of 104 11/01/00 10:05 AM System Overview (Continued) ADB Anode Discriminator Boards indicate which CSC anode wire-groups have signals over threshold. Each board outputs 16 asynchronous, uncompressed bits. Depending on the size of the CSC there are between 18 and 42 ADB boards mounted along the chamber edge. CFEB Cathode Front End Boards indicate which CSC cathode strips have signals over threshold. Chargecluster center-finding and data compression are performed by an on-board ASIC. Each board outputs 48 synchronous bits compressed into triad serial-data streams. ALCT 2000 The ALCT board receives ADB discriminator signals from a Cathode Strip Chamber and attempts to identify the location (eta coordinate) and quality of the best-two muon track stubs transiting the chamber. A single ALCT2000 board can accept all of the signals from an entire CSC. There are 3 versions of the ALCT2000, having either 288, 384 or 672 channels that correspond to different CSC sizes. Results from the muon pattern-finder logic are formatted into 28-bit Local-Charged-Track data frames for each muon found. LCT frames are transmitted via two Channel Links to the Trigger Mother Board and by one Channel Link to the DAQ Motherboard. In addition, the DAQMB receives FIFO data consisting of raw CSC wire-group hits that have been stored and serialized by the ALCT2000. FIFO data can also be read out via a JTAG interface. LCT99-Passthru LCT99-Passthru is a temporary module that serves as the interface between the ALCT2000 and existing non-backplane versions of the TMB and DAQMB. It copies LCT data words from the two ALCT2000 TMB channel links and retransmits them unaltered to the rear-panel TMB ribbon cable connector. Similarly, the ALCT2000 FIFO data and Active FEB bits are copied and sent to the DAQMB connector. Clock and Bunch-Crossing signals from the CCB are sent from the LCT99-Passthru to the ALCT2000 as discrete LVDS signals on the channel link cables. Logic in the LCT99-Passthru reconstructs the presumed state of the ALCT2000s Sequencer state-machine, and displays the ALCT status on its frontpanel LEDs. CLCT99 The Cathode LCT99 module receives Comparator signals from the Cathode Front End Boards and attempts to identify the location (phi coordinate), bend angle, and quality of the best-two muon track stubs transiting the chamber. A single CLCT99 board can accept all of the signals from an entire CSC. Results from the muon pattern-finder logic are formatted into 28-bit Local-Charged-Track data frames for each muon found. LCT frames are transmitted via two Channel Links to the Trigger Mother Board and by one Channel Link to the DAQ Motherboard. The DAQMB also receives FIFO data consisting of raw CSC strip hits that have been stored and serialized by the CLCT99. Page 10 of 104 11/01/00 10:05 AM CCB The Clock and Control Board (CCB) distributes the 40MHz system clock, Level 1 Accept signal, and Bunch Crossing signals to all the VME modules in the system. LCT99-Passthru forwards these signals to the ALCT2000 board. DAQMB The Data Acquisition Motherboard receives raw-hits FIFO data via Channel Links from the ALCT2000 and from the Cathode LCT99 module. It also receives an Active FEB Flag bit from each LCT unit that indicates a muon track-stub had been found. The Active FEB[3..0] bits indicate which of the Cathode Front End Boards have data for that muon. Data from the DAQMB are sent via optical link to a computer for readout. TMB The Trigger Mother Board receives LCT data for the 2 best muons found in the CSC on every clock cycle. It gets 2 anode LCTs from ALCT2000 and 2 cathode LCTs from CLCT99, and tries to correlate the anode and cathode views of the muon track-stub by comparing LHC Bunch Crossing Numbers contained in the LCT frames. Successful matches are forwarded to the Muon Port Card for input to the muon trigger system. Page 11 of 104 11/01/00 10:05 AM ALCT2000 Overview ALCT boards may contain 3, 4 or 7 LCT FPGAs4, depending on the type of CSC. Each LCT FPGA inputs discriminator bits for 16 anode wire-groups from 6 CSC layers, for a total of 96 input bits. The function of the LCT logic is to recognize anode hit-patterns and quantify the best muon track-stub (a Local Charged Track) that transits the CSC within its scope of 16 wire-groups. ALCT2000 Components Figure 2: ALCT2000 Components ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC 20 Shared 0-15 ADB I/O Delay ASIC 20 Shared ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC 20 Shared 16-31 ADB I/O Delay ASIC 20 Shared ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC 4 Power Supply LCT Data Bus LCT0 FPGA CFG JTAG Bus Configuration Key Wire Groups CFG EEPROM LCT1 FPGA JTAG LVDS ByteBlaster Altera JTAG LVDS ByteBlaster Test Pulse In Channel Link Tx Key Wire Groups Concentrator LCT2 FPGA ADB I/O Delay ASIC ADB I/O Delay ASIC 20 Shared32-47 ADB I/O Delay ASIC 20 Shared ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC ADB I/O Delay ASIC Channel Link Tx Channel Link Tx Key Wire Groups LVDS Inputs LCT3 FPGA Key Wire Groups 48-63 Low Volatge Distribution Board ALCT Control Bus Altera FIFO Address Bus FIFO Data Bus Flash RAMs Test Pulse Trigger 1st LCT to TMB 2nd LCT to TMB Dump to DAQMB Clock,Ext_trig BX0,BxReset, Ext_inject, Test Pulse Serial Bus Analog Test Pulse Generator 4 Threshold DACs ADCs Temp Sensor Slow Control FPGA Sadly, LCT0-LCT3 FPGAs are numbered as LCT1-LCT4 on the ALCT2000-384 circuit board. Page 12 of 104 11/01/00 10:05 AM ADB I/O Connector receives 16 discriminator output signals, and supplies power (+5.5V, -4.3V) and control signals (/stand_by, Vthr, test_pulse) to the ADB cards Delay ASIC is a full-custom Application-Specific Integrated Circuit that receives 16 differential LVDS inputs from an ADB and outputs 16 single-ended TTL outputs to the LCT chip. It has a programmable propagation delay, and provides fixed-width output pulses. LCT[0-3] FPGAs find muon-stub Local Charged Tracks for 16 wire-groups in 6 CSC layers and output their results to the Concentrator FPGA. Each LCT FPGA outputs data for 1 muon-stub every clock cycle. The FPGAs also store raw-hits in an on-chip FIFO structure for subsequent readout after Level 1 Accept. LCT Data Bus carries pattern finding results (key wire-group and number of layers hit) from each LCT FPGA to the Concentrator FPGA. This 9-bit bus operates point-to-point at 40MHz. FIFO Address Bus carries raw-hits-FIFO write and read addresses from the Concentrator to the LCT FPGAs. The 18-bit bus operates at 40MHz, and drives all LCT FPGAs in parallel. The LCT FPGAs all write data to the same FIFO address, but the chips are selected individually during read-out. FIFO Data Bus carries raw-hits-FIFO data from the LCT FPGAs to the Concentrator. The 16-bit 40MHz tri-state bus connects one LCT FPGA at a time to the Concentrator Concentrator FPGA receives muon track-stub LCT data every clock cycle from up to 7 LCT FPGAs. When a valid track-stub pattern is found, the Concentrator formats and forwards the data for the best 2-of-7 muons to the Trigger Mother Board (TMB) via 2 LVDS Channel Links. When a Level 1 Accept arrives, the Concentrator controls the FIFO Address Bus and transfers raw-hits data from the FIFO Data Bus to the DAQ Mother Board (DAQMB) via an LVDS Channel Link. CFG EEPROM stores JTAG configuration data for the volatile control registers in the FPGAs. This feature is not yet implemented. Its intended use is to reload the FPGA JTAG configuration register at power-up. Slow Control FPGA writes the DACs (ADB threshold, Test Pulse amplitude), reads the ADCs (DAC read-back, power supply voltages and currents, and on-board temperature), and controls Test Pulse distribution. ALCT Control Bus carries configuration data from the Concentrator to the LCT FPGAs. This 8-bit bus operates at slow speed (usually it is DC) and supplies trigger mode data to the LCT FPGAs. Page 13 of 104 11/01/00 10:05 AM Altera FlashRAMs contain non-volatile configuration programming for the FPGAs. They automatically reload the FPGAs at power-up. Channel Links transmit LCT data for the 2 best muon track-stubs to the TMB and send raw-hits data to the DAQMB. These devices clock 28 bits in at 40 MHz, then serialize 7 bits into a single bit-stream, then send 4 streams out at 280MHz. Because of their high speed, the Channel Links require special "Skewclear" cables. DACs provide discriminator threshold voltages for the ADBs. These 12-channel, 8-bit serial DACs can not be read-back directly, so their outputs are connected to ADCs that can be read via JTAG. The DAC voltages are set via JTAG commands to the Slow Control FPGA. ADCs digitize the threshold DACs for read-back. The 12-channel, 8-bit ADCs also digitize power supply voltages and currents as well as the on-board temperature sensor. They are read via JTAG commands to the Slow Control FPGA. Test Pulse Generator produces test pulses for the ADB cards and for the CSC test pulse strips. The pulse amplitude is determined by an 8-bit DAC that is set by JTAG commands to the Slow Control FPGA. A JTAG register selects the ADBs and strips to be pulsed. The test pulse is initiated by either JTAG command to the Concentrator chip or by a TTL pulse to the LEMO input (selected by a jumper). Power Supply consists of on-board voltage regulators and monitoring circuits. Voltages and currents are buffered and scaled for read-back by the ADCs. In addition, the ALCT2000 board supplies power to the ADB cards. Configuration JTAG Connector drives a JTAG bus for configuring the various user control registers in the FPGAs. External signals are LVDS levels, which requires an LVDS-Byteblaster connection to a PC parallel port. Altera Programming JTAG Connector drives 2 JTAG buses. One bus programs new FPGA logic bits into the Altera FlashRAMs (non-volatile memory). The other bus programs the Altera FPGAs (volatile memory) directly. The buses my be operated as 2 independent chains or as one long chain, depending on the jumper settings. Page 14 of 104 11/01/00 10:05 AM Anode Discriminator Board ADB Overview The ALCT2000 board receives 16 bits of data from each of 24 Anode Discriminator Boards (ADBs). Logic levels are compatible with standard LVDS (Low Voltage Differential Signaling), and represent the anode-wires having signal amplitudes above threshold. DACs on the ALCT2000 supply the ADB threshold voltage via the ADB-ALCT cables. Typical threshold voltages are around +1.28 volts. Higher threshold voltages correspond to lower actual ADB thresholds, and the threshold response of each ADB ASIC needs to be individually calibrated. ADB output pulse widths are proportional to timeover-threshold. ADB Channel Mapping A 16-channel ADB card covers 2 CSC layers, with 8 wire-groups per layer. For example, cards 0,1, and 2 span wire groups 0-to-7 on layers 0-to-5, and cards 3,4,5 span wire groups 8-to-15. Six ADB cards supply a total of 96 discriminator bits to one LCT chip on the ALCT2000 board. Wire Groups on odd-numbered CSC layers are on the "strip-side5" of those layers. The table below is for the first 6 ADB cards, starting at the end of the CSC closest to the beam axis. The pattern repeats for the remaining 3 LCT chips. Mapping CSC Wire Groups to LCT Bit Number Table 1: Mapping CSC Wire Groups to LCT Bit Number First 6 ADB cards [Table entry = LCT chip input bit 0-95] WG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADB0 Ly0 0 1 2 3 4 5 6 7 Ly1 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 ADB3 24 25 26 27 28 29 30 31 ADB1 Ly2 32 33 34 35 36 37 38 39 Ly3 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 56 57 58 59 60 61 62 63 ADB4 ADB2 Ly4 64 65 66 67 68 69 70 71 Ly5 80 81 82 83 84 85 86 87 72 73 74 75 76 77 78 79 88 89 90 91 92 93 94 95 ADB5 5 CSC layers have cathode strips milled into only one of the two panels that form the gas gap. The other side is an uncut copper plane. Page 15 of 104 11/01/00 10:05 AM ADB Card Wire Groups Table 2: ADB Card Wire Groups LCT Chip LCT0 LCT1 LCT2 Card Wire Side Strip Side ADB0 ADB1 ADB2 Ly0 WG 0-7 Ly2 WG 0-7 Ly4 WG 0-7 Ly1 WG 0-7 Ly3 WG 0-7 Ly5 WG 0-7 ADB3 ADB4 ADB5 Ly0 WG 8-15 Ly2 WG 8-15 Ly4 WG 8-15 Ly1 WG 8-15 Ly3 WG 8-15 Ly5 WG 8-15 ADB6 ADB7 ADB8 Ly0 WG 16-23 Ly2 WG 16-23 Ly4 WG 16-23 Ly1 WG 16-23 Ly3 WG 16-23 Ly5 WG 16-23 ADB9 ADB10 ADB11 Ly0 WG 24-31 Ly2 WG 24-31 Ly4 WG 24-31 Ly1 WG 24-31 Ly3 WG 24-31 Ly5 WG 24-31 ADB12 ADB13 ADB14 Ly0 WG 32-39 Ly2 WG 32-39 Ly4 WG 32-39 Ly1 WG 32-39 Ly3 WG 32-39 Ly5 WG 32-39 ADB15 ADB16 ADB17 Ly0 WG 40-47 Ly2 WG 40-47 Ly4 WG 40-47 Ly1 WG 40-47 Ly3 WG 40-47 Ly5 WG 40-47 ADB18 ADB19 ADB20 Ly0 WG 48-55 Ly2 WG 48-55 Ly4 WG 48-55 Ly1 WG 48-55 Ly3 WG 48-55 Ly5 WG 48-55 ADB21 ADB22 ADB23 Ly0 WG 56-63 Ly2 WG 56-63 Ly4 WG 56-63 Ly1 WG 56-63 Ly3 WG 56-63 Ly5 WG 56-63 LCT3 Page 16 of 104 11/01/00 10:05 AM ADB-ALCT2000 Signals Table 3: ADB-ALCT2000 Signals +Outsn, -Outsn +Out_n, -Out_n /Stand_By Vthr Test_Pulse +5.5VA -4.3VA GND Discriminator Outputs, LVDS, for strip-side Anode wires Discriminator Outputs, LVDS, ADB voltage regulator shut-down Discriminator threshold voltage ADB Test Pulse. Falling edge triggers all 16 channels +5.5V Analog Power -4.3V Analog Power Power Return Page 17 of 104 11/01/00 10:05 AM Delay ASIC Overview The Delay ASIC is a full-custom Application-Specific Integrated Circuit that receives 16 differential LVDS inputs from an ADB and outputs16 single-ended TTL to an LCT FPGA. It has a programmable propagation delay for the outputs, and provides fixed-width output pulses. Programming The 4-bit delay shift-register is written by an SPI-like Serial Bus and is common to all 16 channels. One delay step is approximately 2ns, which is determined by the external Idelay resistor6. The output-pulse width is determined by the Iwidth resistor, and is the same for all 16 channels. Iwidth resistors are chosen to give output pulses in the range of 35ns to 40ns. Delay ASIC Signals Table 4: Delay ASIC Signals +Inn, -Inn Outn Iwidth Idelay /CS CLK Din Dout /RS Vdd GND LVDS inputs from ADB card TTL Outputs to LCT chip, fixed width, programmable delay Output width program current (selected by a resistor to Gnd) In-to-Out delay program current (selected by a resistor to Gnd) Chip Select input for programming Serial data clock input Serial data input Serial data output Reset input, sets delay register to 0 +3.3V Power input Power Return 6 Current ALCT2000 boards have Idelay chosen to give a 32ns full-scale delay, which makes the step size 2.1ns. The current Delay ASICs have a bi-linear delay, so the actual step size depends on the particular programmed delay. Page 18 of 104 11/01/00 10:05 AM ALCT2000 Logic and Algorithms LCT FPGA Logic ALCT boards may contain 3, 4 or 7 LCT FPGAs, depending on the type of CSC. Each LCT FPGA inputs discriminator bits for 16 anode wire-groups from 6 CSC layers, for a total of 96 input bits. The function of the LCT logic is to recognize anode hit-patterns and quantify the best muon track-stub (a Local Charged Track) that transits the CSC within its scope of 16 wire-groups. Discriminator bits are shared between LCT chips to allow for seamless pattern finding across chip boundaries. The LCT FPGA outputs an LCT data frame every clock cycle that represents the best muon stub found on that cycle. Discriminator bits ("raw hits") are also stored in a FIFO every clock cycle, and can be read out to provide a history of anode hits for times both before and after muon track-stub is found. An on-chip hitpattern generator can "inject" any pattern of 96 bits into the LCT FPGA data stream. The JTAG interface configures the LCT logic by setting various internal registers such as the "hot-channel" mask, injector mode, and accelerator muon mode. Figure 3: LCT FPGA Logic To/From N+1 LCT Chip ADB Latch Mask Delay ASIC Pattern Injector WG OneShot Plane OR Pattern Hits Collision µ Plane OR Accelerator µ Pattern Hits Priority Encoder Best 1-of-32 1 LCT To Concentrator To/From N-1 LCT Chip Ch Mask ALCT JTAG FEB Exchange Test Pattern Accelerator/Collision Muon JTAG Bus Concentrator Bus LCT FIFO FIFO MUX Raw Hits To FIFO Bus ADB Anode Discriminator Boards on the CSC digitize anode wire-group signals. They output an LVDS-level bit for every wire-group having a signal amplitude over threshold. The output pulse widths are proportional to time-over-threshold. Delay ASIC converts 16 differential LVDS inputs from the ADB to 16 single-ended TTL outputs for the LCT chip. It has a programmable propagation delay (0-32ns), and provides 35ns fixed-width output pulses. Latch Mask latches 96 ADB discriminator bits on the rising edge of every 25ns clock cycle, and synchronizes them to the local 40MHz clock. Individual discriminator channels may be disabled by the Hot Channel Mask register. All channels may be disabled by the Mask-All register bit. These registers can be set either via JTAG commands to a specific LCT chip or by the Concentrator Bus, which affects all LCT chips. Page 19 of 104 11/01/00 10:05 AM Pattern Injector injects an anode-hits-test-pattern into the discriminator bit stream. The type of test pattern is set via JTAG command to a specific LCT chip, or by the Concentrator Bus (which affects all LCT chips). The two types of predefined internal patterns result in a 6-hit (Quality=3) LCT being found on Key Wire-Group 5. The actual Key WG number depends on the range of CSC wires spanned by a given LCT chip: LCT chip number n (where n=0..6) outputs Key Wire-Group number 16n+5. The Collision Muon pattern produces a slanting track-stub that is similar to a muon trajectory originating at the CMS interaction region, while the Accelerator Muon pattern produces a track-stub parallel to the beam axis. An Arbitrary Hit Pattern can be written via JTAG that has any combination of the 96 anode wire-groups being hit. Table 5: Injector Test Pattern Modes Tmode[1..0] Test Pattern 0 1 2 Collision muon with 6 hits on key wire-group 5 Accelerator muon with 6 hits on key wire-group 5 Arbitrary 96-bit hits shifted in via JTAG Figure 4: Injector Test Pattern Cell with 6 Collision Muon Hits on Wire-Group 5: WG n+2 n+1 n n-1 n-2 | | * Ly0 | * | * | WG * 7 | 6 | 5 4 3 5 | * * 1 2 3 4 ↑ Key WG= Wire-Group 5 On Ly2 Figure 5: Injector Test Pattern Cell with 6 Accelerator Muon Hits on Wire-Group 5: WG n+2 n+1 n n-1 n-2 * | | Ly0 | * | | * WG | 7 | 6 * 5 4 3 5 * | * 1 2 3 4 ↑ Key WG= Wire-Group 5 On Ly2 Page 20 of 104 11/01/00 10:05 AM WG One-Shot performs digital pulse stretching for the wire-group discriminator bits from the ADBs. Pulses from the ADB may be as short as 35ns, and are typically longer than 100ns (time over threshold). The Wire-Group one-shot logic produces a fixed output width of 150ns regardless of the duration of the ADB pulse. The pulse must return to 0 for at least 1 clock cycle before the one-shot can be re-triggered. The 150ns-output width was chosen to ensure 100% efficiency for finding muon track-stubs that have the extreme possible range of drift delays. The pulse width can be changed by re-compiling the design. FEB Exchange sends and receives wire-group bits across LCT boundaries. Because the Pattern Cell is designed for non-parallel muon trajectories, 8 wire-group bits must be shared between adjacent LCT chips for seamless pattern-finding. Figure 6: Wire-Groups Exchanged by Adjacent LCT Chips: WG n+2 n+1 n n-1 n-2 | | | Ly0 | | | | | | | | 2 hits to right adjacent 3 hits to right adjacent | | | 1 2 3 4 5 ↑ Key WG= Wire-Group 5 On Ly2 LCT chip LCT chip 2 hits from left adjacent LCT chip 1 hit from left adjacent LCT chip Plane OR constructs a logical OR of the wire-group bits on a single CSC layer that can belong to a valid hit-pattern for a given Key Wire-Group. For instance, the 3 bits (wg3, wg4, wg5) on Layer 0 are OR'd together to form a single bit that represents Layer 0 for Key Wire-Group 5. The process is repeated for each of the 6 layers and for each of the 16 Key Wire-Groups seen by an LCT chip. Key Wire-Groups are the wires located on the third CSC layer from the Interaction Region (i.e. Layer 2). The result of the Plane-OR is 16 of these 6-bit numbers (i.e. 1 bit per layer) representing all the Key Wire-Groups. ALCT2000 recognizes two different types of pattern-cells. The Collision muon pattern cell detects CSC-hits that line up to point back to the interaction region. ALCT2000 is programmed for the highest muon-angle-of-incidence and includes all lower angles. Production ALCT versions will be programmed for the specific angle-of-incidence appropriate for each 16-wire-group section of their CSC7. Figure 7: Collision-Muon Pattern Cell: WG n+2 n+1 n n-1 n-2 | | | Ly0 | | | | | 1 2 3 | | | | | | 4 5 wg7 wg6 wg5 wg4 wg3 ↑ Key = Wire-Group 5 On Ly2 7 The current ALCT design requires re-compiling the Altera logic for each type of pattern-cell. Page 21 of 104 11/01/00 10:05 AM Plane OR (Continued) Accelerator muons do not originate from the interaction region, and travel parallel to the beam axis. The ALCT2000 Accelerator-muon pattern cell detects CSC-hits that line up parallel to the beam axis, within the angular range of 1 wire group over the thickness of the CSC.. Plane-OR logic outputs 6-bit numbers for Accelerator Muon patterns and Collision-muon patterns simultaneously. Figure 8: Accelerator-Muon Pattern Cell: n+2 n+1 n n-1 n-2 | | | wg7 wg6 wg5 wg4 wg3 | | | Ly0 1 2 3 4 5 ↑ Key = Wire-Group 5 On Ly2 Pattern Hits counts the number of non-zero bits in a 6-bit number. Its inputs are the 6-bit pattern ORs from the Plane OR sub-design. The resulting output is a 3-bit binary "pattern number" in the range of 0 to 6 for each possible Key Wire-Group that corresponds to the number of layers hit within the pattern cell. ALCT2000 has 2 separate Pattern Hits units that operate simultaneously on Acceleratormuon and Collision-muon pattern bits. Priority Encoder receives 16 Collision-muon and 16 Accelerator-muon 3-bit pattern numbers from the Pattern Hits unit. The encoder logic chooses the one "best" muon (for this LCT Chip) according to its pattern number and constructs the key-wire-group number for transmission to the Concentrator Chip. Before selecting the best pattern, the 3-bit pattern numbers are converted to 4-bits. A new high-order "Promotion" bit (B"1000") is applied to either the Accelerator-muon patterns or to the Collision muon patterns according to the Amode[1..0] register. Table 6: Priority Encoder Modes Amode[1..0] Action 0 1 2 3 Ignore Accelerator-muons Prefer Collision-muons by adding Promotion bit to them Prefer Accelerator-muons by adding Promotion bit to them Ignore Collision-muons For example, if Accelerator-muon patterns are preferred (Amode=2), and a 6-hit Accelerator-muon was found, its pattern number is promoted from 6 (B"0110") to 6+8=14 (B"1110"), so it will have priority over all Collision-muon patterns. Priority encoding is accomplished by a 3-stage tree-decision logic structure that compares all 16 of the 4-bit pattern numbers and chooses the highest one found. If two or more equal patterns numbers are found, the one with the highest key-wire-group number (i.e. farthest from the beam axis) is preferred. Page 22 of 104 11/01/00 10:05 AM LCT FIFO stores anode discriminator "raw hits" in a dual-port 96x32x4 RAM every clock cycle. The 96 data bits from the ADBs are not altered or interpreted before being stored in RAM. The RAM is organized as 4 banks of 32 addresses each (called "time bins"), that can be written and read independently. By switching the bank address, the RAM can store 32 time-bins of ADB hits for up to 4 separate events. The bank address, write address, and read address are received from the Concentrator chip via FIFO MUX sub-design. FIFO Mux receives and pipelines RAM address bits from the Concentrator chip. During a RAMwrite phase, the address bits from the Concentrator chip are passed on to the RAM array. During a RAM-read phase, which occurs during a raw-hits dump, the FIFO Multiplexer logic selects an 8-bit data "slice" from the 96 parallel output bits from the RAM. The 8 raw hits as well as the LCT chip ID and time-bin number are sent to the Concentrator chip via the FIFO-bus. ALCT JTAG contains logic and registers for such LCT chip functions as: ID Register, Control Register, Hot-Channel Mask, Arbitrary Test Pattern, and Inject Test Pattern, which are described later in the programming section. The Control Register, which selects Test Pattern Mode, Accelerator Muon Mode, and Mask All, can operate under direct JTAG command or it can be configured by the Concentrator chip via the ALCT Control Bus. The ALCT Control bus connects the Defaulter logic in the Concentrator to all the LCT FPGAs to allow the Concentrator to assert control over all chips simultaneously. Table 7: ALCT Control Bus CTL[] # Bits Function [0] [2..1] [4..3] [5] [7..6] Total 1 2 2 1 2 8 1=Concentrator asserts alt_ctl[1..7], 0=Use JTAG ctl[1..7] Tmode[1..0] LCT Chip Trigger mode Amode[1..0] LCT Chip Accelerator muon mode Mask all wire group inputs [Automatic during inject] Unassigned Page 23 of 104 11/01/00 10:05 AM Logic Cells in the Altera FPGA are used to implement all of the LCT functions except for raw hits data storage. Raw hits are stored in the LCT FIFO dual-port RAM, which uses the FPGA embedded RAM arrays (Altera EABs). Table 8: LCT Logic Cells Logic Section Latch Mask Injector WG One-Shot FEB Exchange Plane OR Pattern Hits, Collision Pattern Hits, Accelerator Priority Encoder LCT FIFO FIFO Mux JTAG Total (Sum of Logic Sections) Optimized fit into Altera 10K100E device Logic Cells FPGA Usage RAM bits 192 117 768 114 192 128 128 531 96 147 534 7% 4% 26% 4% 7% 4% 4% 18% 3% 5% 18% 0 0 0 0 0 0 0 0 12,288 0 0 2,947 100% 12,288 2547 51% 12,228 (25%) Page 24 of 104 11/01/00 10:05 AM LCT I/O Signals Table 9: LCT I/O Signals Pattern Finder Bits Dir Function ly_in[5..0][15..0] pat[3..0] key[3..0] amu Radj_in[4..0] Radj_out[4..0] Ladj_in[4..0] Ladj_out[4..0] clock clock2 96 4 4 1 5 5 5 5 1 1 In Out Out Out In Out In Out In In ADB discriminator bits Best muon pattern number Key wire-group for best pattern Best pattern is an Accelerator-muon ADB bits from right adjacent LCT ADB bits to right adjacent LCT ADB bits from left adjacent LCT ADB bits to left adjacent LCT 40MHz system clock Phase shifted system clock (future use) Bits Dir Function 16 1 2 5 1 2 5 3 1 Out Out In In In In In In In 8 bits of Raw hits + time bin number /Enables FIFO bus-driver chip RAM-write bank address RAM-write time bin Chip select enables /fifo_oe RAM-read bank address RAM-read time bin RAM-read CSC layer RAM-read slice (high or low 8 bits) Bits Dir Function 1 1 1 1 4 4 In In In Out Out Out Test Clock Test Mode Select Test Data In Test Data Out Current JTAG opcode Current JTAG state Bits Dir Function 4 8 1 In In In Bits Dir Function 3 Out Unassigned debug pins FIFO fifo_out[15..0] /fifo_oe wr_bank[1..0] wr_tbin[4..0] chip_sel rd_bank[1..0] rd_tbin[4..0] rd_layer[2..0] rd_slice JTAG tck tms tdi tdo opcode[3..0] state[3..0] Control chip_id[3..0] alct_ctl[7..0] inject_in Debug future[2..0] Total I/Os LCT Chip number 0 to 6, hardwired on PCB Concentrator-bus Test pattern inject command 191 Page 25 of 104 11/01/00 10:05 AM Concentrator FPGA Logic The Concentrator Chip receives pattern numbers and Key Wire-Group bits from all of the LCT chips. It is designed to accept inputs from up to 7 LCT chips, and it is compatible with the 3 or 4 LCT chip versions of the ALCT boards. The Concentrator's main function is to choose the best 2 muon-trackstubs presented by the LCT chips. When a hit-pattern is found with enough CSC layers hit, the Concentrator's Sequencer state machine begins a processing cycle. If a valid hit pattern still exists after waiting for the CSC drift-time, the Sequencer sends LCT data about the best 2 muon track-stubs to the Trigger Mother Board (TMB). When a Level 1 Accept signal is received from the Clock and Control Board (CCB), the Sequencer logic sends serialized raw-hits data to the DAQ Mother Board (DAQMB). Figure 9: Concentrator FPGA Logic Priority Encoder LCT6 Best 2 of 3 LCT5 LCT4 LCT3 Resolver LCT2 LCT1 Sequencer Best 2 of 4 Best 2 of 4 2nd LCT to TMB LCT0 Pattern PreTrigger External Trigger FIFO Bus CCB CCB Defaulter EEPROM Dump to DAQMB FIFO Control Concentrator Bus JTAG Bus 1st LCT to TMB LCT Chip Pattern Injectors JTAG ACon JTAG FIFO EEPROM Page 26 of 104 11/01/00 10:05 AM Resolver receives pattern numbers and key wire-group data from up to 7 LCT chips. It merges overlapping LCT boundary-patterns having Key Wire-Groups within 2 WGs of either side of the chip boundary to provide seamless pattern finding. For example, if LCT chip 0 found a 6-hit track-stub on Key Wire-Groups 14 (or 15), then LCT chip 1 would find the same track-stub, but will see it as a 4-hit track-stub on wire-groups 16 (or 17). The Resolver logic recognizes that there is actually only 1 real track-stub, so it deletes one of them. In this case, the LCT for wire group 16 would be deleted because it has fewer CSC layers hit, even though it has a higher wire-group number. The selection rules for deciding which track-stub to keep are: 1) The higher pattern number always prevails. 2) If two pattern numbers are equal, the pattern with the higher WG number (i.e. lower eta) is preferred. Note there is an asymmetry in how close 2 track-stubs can be with this algorithm. In the LCT chips, only the 1 best track-stub within 16 wire-groups is retained. In the Resolver logic, 2 track-stubs may be as close as 4 wire-groups. The number of overlap WGs is adjustable by recompiling the Concentrator logic, but not by JTAG programming. There is no distinction made between collision and accelerator muons in the Resolver. The promotion bit added by the LCT chips automatically prioritizes the preferred type of muon. Priority Encoder receives 7 LCT pattern numbers and key wire-groups from the Resolver. The highest 2-of-7 pattern numbers are selected, and forwarded to the Sequencer logic. The Priority Encoder logic consists of 3 parallel encoder blocks (Best 2-of-3 and Best 2-of-4) arranged in a tree-structure. This was done because a full-parallel best-2-of-7 construct would not be able to run at 40MHz using current FPGA devices. Best 2 of 3 receives 3 LCT pattern numbers and key wire-groups from the Resolver. The best 2 pattern numbers are forwarded to the next stage. Best 2 of 4 receives 4 LCT pattern numbers and key wire-groups from the Resolver. The best 2 pattern numbers are forwarded to the next stage. Pattern Pre-Trigger instructs the Sequencer to start processing an event if any one of the 7 LCT pattern numbers is above the pre-trigger threshold. Usually, this threshold requires at least 2 CSC layers hit, which gives a good correlation between the muon arrival time and the LHC bunch crossing time, while rejecting single-hit backgrounds. The Tmode register, programmed via JTAG, determines which types of LCT patterns may pre-trigger the Sequencer. Page 27 of 104 11/01/00 10:05 AM Table 10: Pattern Pre-Trigger Modes Tmode[1..0] 0 1 2 3 Test Pattern Either a collision pattern or an accelerator muon pattern may pre-trigger Only an accelerator muon pattern may pre-trigger Only a collision muon pattern may pre-trigger Accelerator muon vetoes pre-trigger Besides pre-triggering on a hit-pattern, the logic can also initiate a pre-trigger sequence when it receives an external trigger or an external test-pulse signal. When any of the external trigger sources are enabled, pattern triggers are automatically disabled. The external test pulse (ext_tp) input fires the on-board analog pulse generator (tp_trigger), and initiates a self-made external trigger. Sequencer controls and organizes all of the Concentrator functions. It is implemented as a "one-hot" state machine having 16 defined states8. At power-up time, the Sequencer waits for the LCT patternnumber pipelines to clear out. It then enters the Idle state waiting for a pre-trigger signal to arrive. Before being output to the TMB and DAQMB, the LCT pattern numbers are converted to pattern quality numbers to conserve bits in the trigger data path. The "promotion" bit is removed, and the number of layers hit is converted to a Pattern Quality number by subtracting 3, and suppressing patterns with less than 4 hits: Table 11: Anode Quality Number Anode Layers Hit Within a Pattern Cell Pattern Quality 6 5 4 3 2 1 0 3 2 1 0 0 0 0 Event processing is initiated when an LCT pattern above the pre-trigger-threshold (usually 2 layers) is detected. Active FEB bits are sent immediately to the DAQMB to let it know that an event is being processed9, and the LHC Bunch Crossing number is latched for this new event. Because the CSC drift times can be 0 to 60ns, the Sequencer waits for up to 3 clocks (75ns, programmable) to allow for more layers to record hits. At the end of the drift delay, an LCT pattern above the pattern-threshold (usually 4 8 "One-hot" means there is 1 flip-flop for each state. The Sequencer has 16 defined states, but the 16 flip-flops could inadvertently end up in any of the 216-16 remaining states due to an upset. The "Others" state returns the Sequencer to Idle if an upset occurs. 9 This is a potential problem for the DAQMB because the Sequencer may reject the pre-trigger if it does not find a valid pattern after the drift delay. Page 28 of 104 11/01/00 10:05 AM layers) must exist. If a valid pattern (Quality ≥1) was not found, the Sequencer flushes the LCT pipelines and returns to the Idle state to wait for a new pre-trigger10. An exception is if external triggers are enabled, in which case there is no requirement for a valid pattern to exist, and event processing continues as if a valid pattern had been found. The Sequencer enters the Xtmb state for 1 clock-cycle and sends formatted LCT data frames for the 2 best muons to the TMB. After transmitting to the TMB, the Sequencer waits 3.2us (programmable) for a Level 1 Accept to arrive from the Global Trigger System. If an L1A does not arrive within the L1A window (typically 3 clocks wide), the event is flushed and the Sequencer returns to the Idle state. External signals are provided on the ALCT2000 circuit board to facilitate timing the L1A delay. Once the Level 1 Accept arrives, the Sequencer asserts the DAQMB FIFO /Write Enable bit and begins a transmission to the DAQ Motherboard. First, 8 header frames are sent that contain LCT data for the best 2 muons, and various event data such as the Bunch Crossing Number and Event Number. Then, if enabled, the raw hits-data from the LCT chip are sent, packed 8 bits per frame along with the LCT chip ID and the Time Bin number. The number of raw-hits frames depends on the number of Time Bins requested for readout. After the last raw-hits frame, an "evener" frame is sent, which is needed to make the total frame count an even number. The last frame ("trailer") contains the word count. The Sequencer then enters the Flush state to clear out the pipelines, and returns to the Idle state to await the next pre-trigger. If the pre-trigger-and-halt mode is selected, the Sequencer enters the Halt state after sending the trailer frame and waits for a JTAG resume command before returning to Idle. This allows JTAG readout of the raw-hits data without having new pre-triggers overwrite the current event. The Sequencer also contains the Injector state machine that controls the test pattern signals to the LCT chips. In the normal mode, the state machine sends one inject command to the LCT chips and returns to its idle state. The source of the inject command may be either JTAG or an external signal. In the continuous-inject mode, the state machine issues the inject signal to the LCT chips, then monitors the Sequencer state, and issues another inject command as soon as the previous inject process is completed. 10 ALCT2000 and the LCT99-passthru module recognize this situation and flashes the "InvPat" Invalid Pattern LED Page 29 of 104 11/01/00 10:05 AM Table 12: Sequencer States State Clock Function s Startup Idle Pretrig Encode Drift Xtmb Flush 6 1 1 0-to-3 1 15 Wait for power-up debris to clear Wait for pre-trigger (indefinitely) Start processing a pre-trigger event, latch Bunch Crossing Number Wait for Priority Encoder to process LCT, send Active FEBs to DAQMB Wait for CSC drift (programmable) If valid pattern exists after drift, output LCTs to TMB, go to L1Adelay If valid pattern does not exist after drift, flush buffers, go to Idle L1Adelay L1AWindow NoL1A 122 3 1 Wait for Level 1 Accept (programmable, typically 3.2µs) Level 1 Accept must arrive during this window Level 1 Accept did not arrive in L1A window, go to Flush Xdaqmb Xheader Xdump Xevener Xtrailer 1 8 336 1 1 Level 1 Accept arrived in window, begin DAQMB sequence Output header frames to DAQMB Output raw hits frames to DAQMB (programmable # of tbins) Output "evener" frame to DAQMB (makes word count always even) Output "trailer" frame to DAQMB, go to Flush then Idle Halt Others 1 Stop processing events, wait for Resume command from JTAG Sequencer entered an undefined state, go to Idle FIFO Control sends read and write addresses to the LCT chip RAMs for storing raw-hits data. When the Sequencer is in the Idle state, FIFO Control increments the RAM write-address every clock cycle, so raw-hits are stored in successive RAM locations. When the Sequencer senses a pre-trigger, FIFO Control stops incrementing the RAM write-address, and waits for a start-readout signal, which arrives after Level 1 Accept11. The beginning RAM read-address is calculated based on the last writeaddress and the number of Time Bins to be read out. During the readout phase, the FIFO Control state machine loops over LCT chips to be read out, and selects one chip at a time by asserting a /chip_enable bit12. For each LCT chip, the RAM read-address is incremented on each clock cycle. Raw-hits data from the selected LCT RAM are forwarded to the Sequencer's data frame logic for transmission to the DAQMB. CCB constructs the 12-bit Bunch Crossing Number (BXN) and the 4-bit Level 1 Accept Number. Every clock cycle, the BXN is incremented by 1. When the Concentrator detects a pre-trigger, the current BXN is latched and stored for that event. When the CCB logic receives BxReset from the CCB VME module, it stops incrementing the BXN and presets it to the pre-defined BXN Offset value (4 bits). When the BX0 signal arrives, the BXN counter resumes counting, starting from the preset value. The L1A counter is incremented for every pre-trigger that has a valid pattern after the drift delay. The 11 Future designs are expected to store up to 4 events before incurring any dead time. The current design stores only 1 event. 12 The current design can only read out all or none of the LCT chips. Future designs are intended to have a "local dump" mode that reads out only the LCT chips that contain a valid LCT hit-pattern. Page 30 of 104 11/01/00 10:05 AM counter is preset to the L1A Offset value (4 bits) along with the BXN when BxReset and BX0 arrive. Both L1A and BXN counters have one-shot logic to prevent double-counting if the CCB signals are too wide or too noisy. Defaulter provides power-up default values for all the programmable Concentrator configuration bits. These defaults can only be changed by re-compiling the Concentrator chip design, but they can all be over-ridden by JTAG programming, and some are over-ridden by the DIP-Switch. See the programming section for more details. The Defaulter values are not used if the JTAG registers are enabled. The Defaulter also drives the ALCT Control bus signals that connect to all of the LCT chips. See the ALCT JTAG section for a description of this bus. JTAG Acon contains the Concentrator ID Register, Control Register, Trigger Register, and JTAG FIFO Register. If enabled, the Control Register overrides the Defaulter settings. At power-up, this register is cleared, but it still overrides the Defaulter, so it needs to be initialized by JTAG before the Concentrator can function. The Trigger Register can instruct the Pre-Trigger logic to initiate a selftrigger, and it can fire the test pattern injector logic in the Sequencer. Raw hits data stored in the JTAG FIFO can be read out through a JTAG register. See the programming section for more information about the JTAG registers. JTAG FIFO stores a copy of the data sent to the DAQMB for later readout via JTAG. The header frame, raw-hits frames, and trailer frames are included. Because of the limited number of RAM cells in the FPGA, only DAQMB bits [18..0], and only up to 2048 frames can be stored. On readout, 12 sequential frame-number bits and a data-available bit are attached to the DAQMB frames, making them into 32-bit words. The maximum number of raw-hits time bins that can be stored depends on the number of LCT chips on the ALCT board: 96/8 x Nchips x Ntbins + 10header = 2048 frames. The LCT chip RAMs only store up to 32 tbins, which limits the maximum number of frames. The current design wraps around and overwrites frames, if the programmed number of time bins exceeds the limit. Table 13: JTAG FIFO Time Bin Limits # LCT Chips 3 4 7 Maximum JTAG Readable Time Bins 32 32 24 EEPROM is intended to initialize the Concentrator, and perhaps the LCT chips after a power-up reset. It would function like the Defaulter, but have the added ability to be written via JTAG. The current design contains an empty logic block with all expected connections to an on-board EEPROM device. Page 31 of 104 11/01/00 10:05 AM Logic Cells in the Altera FPGA are used to implement all of the Concentrator functions except for the FIFO data storage. The JTAG FIFO dual-port RAM uses the FPGA embedded RAM arrays. Table 14: Concentrator Logic Cells Logic Section Resolver Best 2 of 3 Best 2 of 4 Best 2 of 4 Pattern Pre-Trigger Sequencer CCB FIFO Control Defaulter JTAG Acon JTAG FIFO EEPROM Total (Sum of Logic Sections) Optimized fit into Altera 10K100E device Logic Cells FPGA Usage RAM bits 190 106 164 164 128 914 58 144 159 381 129 1 8% 4% 6% 6% 5% 36% 2% 6% 6% 15% 6% 0% 0 0 0 0 0 0 0 0 0 0 38,912 0 2,538 100% 38,912 2329 46% 38,912 (79%) Page 32 of 104 11/01/00 10:05 AM Concentrator I/O Signals Table 15: Concentrator I/O Signals Resolver Bits Dir 28 28 7 In In In Bits Dir Function 1 1 1 1 In In In Out External trigger, 25ns minimum width External test pattern inject command, 25ns min External test pulse command, 25ns minimum Test Pulse trigger to analog pulser Bits Dir Function 16 7 2 5 2 5 3 1 In Out Out Out Out Out Out Out 8 bits of Raw hits + time bin number /Enables FIFO bus-driver chip RAM-write bank address RAM-write time bin RAM-read bank address RAM-read time bin RAM-read CSC layer RAM-read slice (high or low 8 bits) EEPROM Bits Dir Function eep_cs eep_clk eep_di eep_do eep_nu eep_org /jtag_enable 1 1 1 1 1 1 1 Out Out Out In Out Out Out Chip select EEPROM Clock Data to EEPROM Data from EEPROM Not used EEPROM organization Tri-state JTAG LVDS receiver Bits Dir Function 1 1 1 1 4 4 1 1 1 1 4 In In In Out In Out Out Out Out Out Out Test Clock Test Mode Select Test Data In Test Data Out ID number for Concentrator = 7=B"0111" JTAG State machine state LED display TCK LED display TMS LED display TDI LED display TDO LED display Current JTAG Opcode pat[6..0][3..0] key[6..0][3..0] amu[6..0] Pattern PreTrigger ext_trig ext_inject ext_tp tp_trigger FIFO fifo_in[15..0] chip_sel[6..0] wr_bank[1..0] wr_tbin[4..0] rd_bank[1..0] rd_tbin[4..0] rd_layer[2..0] rd_slice JTAG tck tms tdi tdo chip_id[3..0] /led_jstate[3..0] /led_tck /led_tms /led_tdi /led_tdo opcode[3..0] Function Best muon pattern number, 1 per LCT Chip Key wire-group for best pattern Best pattern is an Accelerator-muon Page 33 of 104 11/01/00 10:05 AM Table 16: Concentrator I/O Signals [Continued] CCB Bits Dir 1 1 1 1 In In In In Bits Dir Function csc_id[3..0] sw[11..0] alct_ctl[7..0] 4 12 8 In In Out Chamber ID, Hex Switch Manual Configuration Switches ALCT Control bus Sequencer Bits Dir Function tmb0[27..0] tmb1[27..0] daqmb[27..0] 28 28 28 Out Out Out 1st Best muon LCT data output to TMB 2nd Best muon LCT data output to TMB Dump frames to DAQMB /led_pretrig /led_l1a_intime /led_nol1a_flush /led_invpat /led_amu /led_halt /led_feb[6..0] 1 1 1 1 1 1 7 Out Out Out Out Out Out Out Sequencer Pre-Triggered LED Level 1 Accept arrived in L1A window LED L1A did not arrive in window, event flushed Invalid Pattern LED (LCT invalid after drift) Accelerator Muon pattern LED Sequencer halted Active FEBs [i.e. LCT chips with hits] stat_pretrig stat_invpat stat_halt stat_tmb stat_l1a_window stat_l1a stat_daqmb stat_seq_busy 1 1 1 1 1 1 1 1 Out Out Out Out Out Out Out Out Sequencer Pre-Triggered LED Invalid Pattern LED (LCT invalid after drift) Sequencer halted LCTs sent to TMB Level 1 Accept window Level 1 Accept signal (should be in window) Transmitting to DAQMB Sequencer is processing an event inject_out[6..0] 7 Out Test pattern inject command to LCT chips Bits Dir Function 8 Out Unassigned debug pins clock bx0 bxreset l1accept Defaulter Debug future[7..0] Function 40MHz system clock Bunch Crossing Zero Bunch Crossing Reset Level 1 Accept Total I/Os 283 Page 34 of 104 11/01/00 10:05 AM Slow Control FPGA Slow Control Overview Figure 10: Slow Control Serial Bus Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC /cs_write_dly0 /cs_write_dly1 /cs_write_dly2 /cs_write_dly3 Slow Control FPGA DAC0 /cs_write_thr0 DAC1 /cs_write_thr1 ADC0 /cs_read_thr0 ADC1 /cs_read_thr1 ADC2 /cs_read_thr2 Analog Test Pulse DAC /cs_test_pulse JTAG TDO JTAG TCI JTAG TCK Serial Data In Serial Data Out Serial Clock [to all chips] Page 35 of 104 11/01/00 10:05 AM Slow Control FPGA Logic The Slow Control FPGA supports the operation of the ADBs, Delay ASICs, and Analog Test Pulse Generator. It is designed to operate from the Analog power supplies to minimize coupling 40MHz digital noise from the 3.3V and 2.5V power sections. The only clock signal in the Slow Control FPGA is the JTAG TCK. The 40MHz LCT clock is not used, to help minimize noise on the analog side of the ALCT2000 board. Serial Bus is an extension of the Configuration JTAG bus. When the Slow Control FPGA receives a JTAG instruction that involves transferring data from the DACs, ADCs, or Delay ASICs, it connects the JTAG signals TCK,TDI, and TDO to the Serial Bus The Serial Bus Clock is connected to all the devices on the bus. Only one device (or group of devices) is enabled at a time by the /cs chip select signals. Serial data is shifted in from JTAG TDI and is shifted out via JTAG TDO. Some devices, such as the DACs do not have data output. JTAG Functions of the Slow Control FPGA are described in detail in Slow Control JTAG Programming section on page 62, below. Page 36 of 104 11/01/00 10:05 AM Slow Control I/O Signals Table 17: Slow Control I/O Signals Serial Bus d_in d_out clk Serial Bus Selects /cs_test_pulse /cs_write_thr[3..0] /cs_read_thr[4..0] /cs_write_dly[6..0] /dly_reset /thr_reset Test Pulse tp_group[6..0] tp_strip[5..0] Power Control /standby[41..0] /tp_pd JTAG tck tms tdi tdo opcode[5..0] state[3..0] chip_id[3..0] Debug future[7..0] Total I/Os Bits Dir Function 1 1 1 Out In Out Serial data into DAC,Delay,ADC Serial data out of Delay,ADC Serial bus clock Bits Dir Function 1 4 5 7 1 1 Out Out Out Out Out Out Select Test Pulse DAC chip Select Threshold DAC chip Select ADC chip Select Delay chip group (6 chips per group) Clear Delay chips Preset DACs to mid-range Bits Dir Function 7 6 Out Out Enable Test Pulse buffer amps for group n Enable Test Pulse buffer amps for strip n Bits Dir Function 42 1 Out Out Shut down ADB power regulators Shutdown Test Pulse power Bits Dir Function 1 1 1 1 6 4 4 In In In Out Out Out In Test Clock Test Mode Select Test Data In Test Data Out Current JTAG opcode Current JTAG state LCT Chip number 0 to 6, hardwired on PCB Bits Dir Function 8 Out Unassigned debug pins 104 Page 37 of 104 11/01/00 10:05 AM Latency ADB Time Description 80ns 0ns 15ns ADB Response to Test Pulse ADB Cable propagation Delay ASIC throughput [Delay set to 0] 95ns [4bx] Subtotal: Analog Processing LCT + Concentrator Time Description 150ns 25ns 75ns 75ns 50ns LCT FPGA Processing time [from ADB bits latched to Pattern and Key output] LCT-to-Concentrator [bus transit] Active FEB flag from Concentrator Drift Delay [programmable 0 to 75ns] xTMB LCT frame transmitted to TMB 375ns [15bx] Subtotal: LCT + Concentrator Processing DAQMB Transmission Time 3000ns 150ns 200ns 8400ns 50ns 375ns Description Level 1 Accept [time from BX to Global Trigger and back to ALCT2000] Level 1 Accept to First DAQMB Header word transmission Header Transmission [8 words] Raw Hits Transmission: 4 LCTs x 6 Layers x 2 Slices x 7 Time Bins =336 frames Trailer frames [EOD + Word Count] Flush Cycle 12175ns Subtotal: DAQMB Transmission Page 38 of 104 11/01/00 10:05 AM Data Formats TMB Data Format Two LVDS Channel Links (DS90CR285 3.3V) are used to transmit the 28-bit LCT data words for the 2 best muon track-stubs every 25nS to the Trigger Mother Board (TMB). Channel Link 0 sends the best muon LCT found, and Link 1 sends the second best muon LCT, if one exists. The Valid Pattern Flag indicates the presence of LCT data. TMB Data Summary Table 18: ALCT2000-to-TMB [via LCT99-Passthru] Data Summary 1st Best Muon LCT Data Name # Bits lct[0][0] lct[0][2..1] lct[0][3] lct[0][10..4] lct[0][15..11] lct[0][27..16] Total 1 2 1 7 5 12 28 Function Valid Pattern Flag Pattern Quality Accelerator Muon Key Wire Group Number 0-111 Bunch Crossing Number Reserved (set to 0) 2nd Best Muon LCT Data Name lct[1][0] lct[1][2..1] lct[1][3] lct[1][10..4] lct[1][15..11] lct[1][27..16] Total # Bits 1 2 1 7 5 12 28 Function Valid Pattern Flag Pattern Quality Accelerator Muon Key Wire Group Number 0-111 Bunch Crossing Number Reserved (set to 0) Page 39 of 104 11/01/00 10:05 AM TMB Channel Link Bits Table 19: ALCT2000–To-TMB [Via LCT99-Passthru] LVDS Channel Link0 Bits 1st Best Muon LCT Bit Bit ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 first_valid first_quality[7..0] first_amu first_key[6..0] first_bxn[4..0] first_res[11..0] Bit Description first_valid first_quality0 first_quality1 first_amu first_key0 first_key1 first_key2 first_key3 first_key4 first_key5 first_key6 first_bxn0 first_bxn1 first_bxn2 first_bxn3 first_bxn4 first_res0 first_res1 first_res2 first_res3 first_res4 first_res5 first_res6 first_res7 first_res8 first_res9 first_res10 first_res11 Anode Valid Pattern Flag: 1=1st LCT is valid Pattern Quality 0-3 Accelerator Muon Flag: 1=Accelerator, 0=Collision muon. Key Wire Group ID Number 0-111 Bunch-Crossing ID number 0-31 Reserved Page 40 of 104 11/01/00 10:05 AM Table 20: ALCT2000–To-TMB [Via LCT99-Passthru] LVDS Channel Link0 Bits 2nd Best Muon LCT Bit Bit ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 second_valid second_quality[7..0] second_amu second_key[6..0] second_bxn[4..0] second_res[11..0] Bit Description second_valid second_quality0 second_quality1 second_amu second_key0 second_key1 second_key2 second_key3 second_key4 second_key5 second_key6 second_bxn0 second_bxn1 second_bxn2 second_bxn3 second_bxn4 second_res0 second_res1 second_res2 second_res3 second_res4 second_res5 second_res6 second_res7 second_res8 second_res9 second_res10 second_res11 Anode Valid Pattern Flag: 1=1st LCT is valid Pattern Quality 0-3 Accelerator Muon Flag: 1=Accelerator, 0=Collision muon. Key Wire Group ID Number 0-111 Bunch-Crossing ID number 0-31 Reserved Page 41 of 104 11/01/00 10:05 AM DAQMB Data Format Transmission Sequence An LVDS Channel Link is used to transmit 28 bits every 25nS from the ALCT2000 board to the Data Acquisition Motherboard (DAQMB) via the LCT99-Passthru module. Since the DAQMB transmits its own output data over an optical link to a PCI card (DDU), the data width is restricted to 16 bits, and the number of words must be even. One of the 16 bits is used by the DAQMB and DDU as a special-word-flag, leaving only 15 bits for LCT data. ALCT2000 serializes and formats its information before transmission, so the DAQMB does not need to examine the contents of the data frames. FIFO control signals from the ALCT2000 allow the DAQMB to write only relevant Channel Link frames, and to count the number of frames in an event. Data transmission to the DAQMB occurs in 3 phases. The first phase begins as soon as ALCT2000 finds any potential 2-hit pattern, but before the priority-encoder selects the best 2 track-stubs. An Active FEB Flag bit and a 7-bit Active FEB word is sent indicating which LCT chips contain data relevant to the 2 muons. If a valid LCT hit-pattern is found after waiting for the 75ns CSC drift delay, LCT data bits are sent to the Trigger Mother Board, which may cause a Level 1 Accept by the Global Trigger System. At CMS, only a fraction of the ALCT2000 triggers will result in a Level 1 Accept. The second DAQMB transmission phase occurs if a Level 1 Accept arrives in a 75ns window about 3.2uS after the phase 1 TMB transmission. First, the header words are sent, followed by the 2 28-bit LCT data words serialized into 4 cycles of 14 bits. The header and LCT data words also assert the FIFO-write bit, so they will be stored by the DAQMB. If the Level 1 Accept does not arrive in the L1A window, the event is flushed, and there is no transmission to the DAQMB. The third transmission phase occurs after the LCT words have been sent. Raw wire-group hits in several time-bins may be read out in one of the FIFO Dump Modes. The mode is selected via JTAG configuration. FIFO Dump Modes There are 3 operating modes for transmitting raw-hits data to the DAQMB: ‘No Dump’, ‘Local Dump’, and ‘Full Dump’. In ‘No Dump' mode, the ALCT2000 sends the same 2 28-bit muon LCT words to the DAQMB and TMB, except that the DAQMB words are sent in 4 sequential frames. The data transmission consists of 8 header words that contain the 2 LCT words, CSC ID, LCT ID, trigger mode, hit AFEB bits, etc. The transmission is terminated by a 2-word trailer that also contains a count of all frames that were sent. The total word count needs to be an even number to satisfy the PCI interface on the DDU board, so ALCT2000 adds an "evener" (hex E0D) frame ahead of the word count frame. ‘Local Dump’ mode includes the same header and trailer frames as 'No Dump Mode' and also inserts 8bit raw-hits frames for the LCT chips that have hits belonging to the 2 best muons. This will be the same set of LCT chips that have their ‘Active FEB’ bits set. The FIFO bit count is 16 wire-groups x 6 layers = 96 bits (i.e. 12 frames) per time bin per LCT chip. 'Localized FIFO Dump' mode is not currently implemented in the ALCT2000 logic. Page 42 of 104 11/01/00 10:05 AM ‘Full Dump’ mode includes the same header and trailer information as 'No Dump Mode' and also inserts 8-bit raw-hits data frames every LCT chip. For a full dump of a 64-wire-group CSC the FIFO bit count is 4 LCT chips x 16 wire-groups x 6 layers = 384 bits (i.e. 48 frames) per time bin. In general, the frame count is (16 wire-groups x 6 layers) / (8 bits per frame) = 12 frames per LCT chip per time bin. Table 21: Anode LCT FIFO Full-Dump Bit Count Wire-Groups Per Layer 48 64 96 112 LCT Chips 3 4 6 7 Bits Per Time-bin 288 384 576 672 Frames Per Time-bin 36 48 72 84 Frames Per 5 Time bins 180 240 360 420 Total Frames 8 Header + 2 Trailer 190 250 370 430 Transmission Time 4.750uS 6.250uS 9.250uS 10.750uS DAQMB FIFO Control The DAQMB module stores the LCT data it receives in a FIFO for every 25nS clock cycle that has the /Write Enable bit asserted. The FIFO chip stores ALCT2000 data bits [14..0] when /Write Enable is a logical 0. Table 22: DAQMB: FIFO Control Bits Flag Bit Last Frame Flag First Frame Flag /Write Enable FIFO Bit # 16 17 18 Remarks Last frame in a transmission sequence. First frame in a transmission sequence. (Sync’d to L1A arrival) 0=DAQMB writes Channel Link bits 0-15 into FIFO. DDU Special Words The Device Dependent Unit is a PCI card that receives data from the DAQMB via an optical link. Bit 15 is reserved as a DDU Special Word Flag by the DAQMB. ALCT2000 has been assigned 1 DDU Special Word to separate events in the DAQMB FIFO. Table 23: DDU Special Words Flag Bit Bits Description DDU Special Word Flag DDU Special Word Field [15] DDU Special word flag. [14..12] B'101' LCT Last Frame LCT Special Words First and last word bits are included to aid in decoding a raw hits dump. Table 24: LCT Special Words Flag Bit Bit Description LCT Special Word Flag First Frame Flag Last Frame Flag Abort Flag 14 13 12 11 Special LCT word flag: Bits 13-11 identify word type First frame in a transmission sequence Last frame in a transmission sequence Last frame in sequence, transmission aborted due to new event Page 43 of 104 11/01/00 10:05 AM Header Frames ALCT2000 collects information about the triggering event, and packs it into an 8-frame header sequence. To initiate a header sequence, ALCT2000 asserts the LCT Special Word Flag, and the First Frame Flag. If it is a 'No Dump' mode transmission, ALCT2000 sends a trailer word that has the LCT Special Word Flag and the Last Frame Flag set and includes the frame count. If it is a Local Dump or Full Dump transmission, ALCT2000 first sends the 8-frame header, then the raw-hits in groups of 8 bits, followed by the 2 trailer words. If another trigger arrives before the raw hit transmission is complete, the raw hit dump is aborted13, and the trailer word sent with the Abort Flag bit set. If an event dump is aborted, at least the full header will always be sent. If another muon arrives while ALCT2000 is busy processing an event (whether pattern-finding, waiting for L1A , dumping or flushing), the new muon is ignored14. Table 25: Header Frame Data Header 13 14 Bits Data Description [0][3..0] [0][7..4] [0][10..8] [0][15..11] 4 4 3 5 L1A Number CSC ID Board ID B'01100' Level 1 Accept counter. Chamber ID number ALCT2000 Board ID First Word Flag [1][1..0] [1][6..2] [1][7] [1][8] [1][9] [1][10] [1][13..11] [1][15..14] 2 5 1 1 1 1 3 2 FIFO Mode # Time bins L1A Match Ext Trig 1st Promote 2nd Promote Reserved B'00' 0=No Dump, 1=Full Dump, 2=Local Dump # 25ns time bins in raw hits dump External L1A arrived in L1A window Trigger source was external Promotion bit for 1st LCT pattern Promotion bit for 2nd LCT pattern Reserved, set to 0 DDU+LCT Special Word flags [2][11..0] [2][13..12] [2][15..14] 12 2 2 BXN Count Reserved B'00' Full Bunch Crossing Number Set to 0 DDU+LCT Special Word flags [3][6..0] [3][13..7] [3][15..14] 7 7 2 LCT Chips Read Active FEBs B'00' LCT chips read out in raw-hits dump LCT chips with ADB hits DDU+LCT Special Word flags [4][13..0] [4][15..14] 14 2 LCT[0][13..0] B'00' 1st LCT lower 14 bits DDU+LCT Special Word flags [5][13..0] [5][15..14] 14 2 LCT[0][27..14] B'00' 1st LCT upper 14 bits DDU+LCT Special Word flags [6][13..0] [6][15..14] 14 2 LCT[1][13..0] B'00' 2nd LCT lower 14 bits DDU+LCT Special Word flags [7][13..0] [7][15..14] 14 2 LCT[1][27..14] B'00' 2nd LCT upper 14 bits DDU+LCT Special Word flags Not yet implemented in ALCT2000 This is a temporary limitation. Future versions will accept up to 4 successive events before having to ignore new events. Page 44 of 104 11/01/00 10:05 AM Time Bin Frames In 'Full Dump' mode, Anode raw hits are read from each LCT chip in sequence: LCT0-to-LCTn. The Concentrator FIFO Control logic then 'loops' over the number of time bins requested. Within an LCT chip, the 6 CSC layers are read in order Ly0-to-LY5. The 16 bits per layer are broken up into two 8-bit 'slices'. One time bin for one LCT chip takes (2 slices x 8 bits per slice x 6 layers) / (8 bits per frame) = 12 frames. In FORTRAN the sequence would look like: Figure 11: Raw Hits Readout Sequence do lct=0,3 !Loop over LCT chips do tbin=0,N !Loop over time bins do layer=0,5 !Loop over CSC layers do slice=0,1 !Loop over 8 bit slices per layer 0=[7..0], 1=[15..8] read() rawhits(lct, tbin, layer, slice) !Read 8 hits per slice end do end do end do end do To aid in debugging, the LCT chip number and time bin number are attached to the 8-bits of raw hits by the LCT chip logic. There are insufficient bits available to store all the time bin bits and LCT ID bits, so the Concentrator Sequencer ORs the Chip ID [2..0] bits [2] and [1] and puts the result in [1]. Table 26: Time Bin Format Field Bits [7..0] [12..8] [14..13] [15] 8 5 2 1 Description Raw hits for ½ of a layer Time Bin Number LCT Chip ID[2..0], OR of [1]+[2] For use by DDU Trailer Frames The Trailer Frames consist of the 'evener' frame and the last frame. The last frame contains the total frame count (including itself) and the DDU special end-of-LCT-data word. Table 27: Trailer Frame Data Trailer Bits Data Description [0][11..0] [0][15..12] 12 4 H'EOD' B'0000' 'Evener' frame (makes frame count even) Special word field [1][9..0] [1][10] [1][11] [1][14..12] [1][15] 10 1 1 3 1 Frame Count Module Type B'0' B101' B'1' Number frames including header and trailers 1=Cathode, 0=Anode. Set to 0 for ALCT2000 Abort flag (not implemented) DDU Type Code DDU Special word flag Page 45 of 104 11/01/00 10:05 AM DAQMB Data Format Example Table 28: Full-Dump Mode Data Format Example [8 Header Frames + 5 Time Bins * 4 LCT chips + 2 Trailer Frames] Frm # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 /wr first last ddu spcl d13 first d12 last d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - - - - FIFO Control 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - LCT Ctrl + Data 1 0 0 0 0 0 0 0 1 237 238 239 240 241 242 243 244 245 246 247 248 249 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 0 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 LCT Chip 3 0 1 - 0 Reserved Reserved -236 d11 abrt 0 - 0 LCT Data - - - Board ID [2..0] 2nd 1st Ext - - - - CSC ID [3..0] L1A Number [3..0] L1A FIFO Mode # Time Bins [4..0] Full BXN [11..0] Active LCT chips [6..0] LCT chips Read Out [6..0] LCT0 [13..0] LCT0 [27..14] LCT1 [13..0] LCT1 [27..0] Tbin 0 Ly0[7..0] Tbin 0 Ly0[15..8] Tbin 0 Ly1[7..0] Tbin 0 Ly1[15..8] Tbin 0 Ly2[7..0] Tbin 0 Ly2[15..8] Tbin 0 Ly3[7..0] Tbin 0 Ly3[15..8] Tbin 0 Ly4[7..0] Tbin 0 Ly4[15..8] Tbin 0 Ly5[7..0] Tbin 0 Ly5[15..8] --Tbin 4 Ly0[7..0] Tbin 4 Ly0[15..8] Tbin 4 Ly1[7..0] Tbin 4 Ly1[15..8] Tbin 4 Ly2[7..0] Tbin 4 Ly2[15..8] Tbin 4 Ly3[7..0] Tbin 4 Ly3[15..8] Tbin 4 Ly4[7..0] Tbin 4 Ly4[15..8] Tbin 4 Ly5[7..0] Tbin 4 Ly5[15..8] 0 Evener: "E0D" Hexadecimal [11..0] A=0 1 0 Frame Count [9..0] - Page 46 of 104 11/01/00 10:05 AM DAQMB Channel Link The 28 LVDS Channel Link bits are shared for 3 separate functions. Bits [15..0] are data bits to be stored in the DAQMB FIFO. Bits [18..16] are provided for use by the DAQMB to aid in storing LCT data. Bits [27..20] are the Active FEB flags that indicate which LCT chips contain hits. Table 29: DAQMB Channel Link Summary LCT Data Handling: Bits Description LCT or FIFO Data LCT Special word flag DDU Special word flag 14 1 1 Bits for FIFO control: Last word flag First word flag /DAQMB FIFO Write Enable Reserved Active ALCT Flags: LCT, Raw Hit data, and header data. LCT special word [first frame and last frame] Flag word that effects Event Builder processing Bits Description 1 1 1 1 Last word for this event from ALCT2000 First word for this event from LCT cards Write-enables DAQMB FIFO. Indicates valid LCT. Set to 0 by ALCT2000. Bits Description Active FEB flag LCT chip with valid LCT Total 1 7 At least one LCT chip has a valid LCT. Persists 25nS. Flags set for all LCT chips with hits. Persists 25nS. 28 Page 47 of 104 11/01/00 10:05 AM DAQMB Channel Link Bits Table 30: ALCT2000–To-DAQMB [Via LCT99-Passthru] LVDS Channel Link Bits Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bit ID data[13..0] data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 Special lct_special Word Flags ddu_special last_frame DAQMB FIFO first_frame Control /write_fifo Reserved reserved0 active_feb_flag active_feb_flag active_feb[6..0] active0 active1 active2 active3 active4 active5 active6 Bit Description Data Bits [13..0] contain header or raw-hits or trailer DAQMB FIFO stores LDATAb0-LDATAb14 LCT Special word flag DDU Special word flag. Last frame in a transmission First frame in a transmission /DAQMB-FIFO-Write Enable Reserved for future use Active FEB Flag: At Least 1 LCT chip has an LCT. LCT chip 0 has hits Page 48 of 104 11/01/00 10:05 AM Clock & Control Board Data Format The 40MHz system-clock, the Level 1 Accept bit, and Bunch Crossing control bits from the Clock & Control Board (CCB) are sent to the ALCT2000 via the LCT99-passthru module. ALCT2000 latches the CCB bits on the rising edge of the 40MHz clock. The CCB arranges the timing of the data bits so they meet the set-up and hold requirements of the FPGA input cells. The BxReset pulse (25ns) stops the ALCT2000 Bunch Crossing Counter and the Event Counter, and loads them with their preset values. Counting resumes from the preset values with the arrival of BX0 (25ns). The Cathode LCT module and ALCT2000 have appropriate BXN preset values that compensate for their different processing times so that their BXNs for a given muon will match. The ALCT2000 BXN preset value is written by a JTAG command. CCB Signal Summary Table 31: Clock & Control Board Signal Summary Signal Function Clock BxReset BX0 L1Accept 40MHz LHC Clock (Square Wave) Stop counting, preset BXN & Event #. Resume counting Level 1 Accept from Global Trigger System Page 49 of 104 11/01/00 10:05 AM Programming The ALCT2000 board is designed to be controlled primarily by register bits set by the ConfigurationJTAG chain. Some inputs to the Concentrator logic and LCT chips can also be set manually with configuration switches on the circuit board. Manual Configuration These switches are intended for stand-alone testing of the ALCT2000 board. SW11-1 over-rides JTAG programming and asserts the bits set by the remaining switch positions 2-to-1215. For normal operation with JTAG, all switches should be in the ON position. Concentrator Configuration Dip-Switch [SW11] SW11 -n ON [Logic 0] OFF [Logic 1] 1 Use JTAG Configuration Data Register Use Defaulter Settings + Ignore SW11-2,SW11-4 to SW11-12 ON 2 Normal running mode Inject LCT test pattern ON 3 Inject 1 test pattern [only if SW11-2 is ON] Continuous inject [only if SW11-2 is ON] + Un-Invert ADB Test Pulse ON 4 Normal pre-trigger sequencing Pre-Trigger & Halt. Toggle to resume ON 5 Use CCB Level 1 Accept Internal Level 1 Accept [ignore CCB] ON 6 Inputs from CCB enabled [L1A,BX0,BXReset] Ignore CCB inputs [L1A,BX0,BXReset] ON 7 Disable External Triggers Enable External Triggers ON 8 9 10 11 12 15 Normal Setting Function ALCT-Bus: LCT Chip Test Pulse mode Tmode[1..0], ON=0: ON 00 Inject Collision muon with 6 hits on key wire-group 5 01 Inject Accelerator muon with 6 hits on key wire-group 5 10 Inject Arbitrary 96-bit hits shifted in via JTAG 11 Not implemented ON ALCT -Bus LCT Chip Accelerator Muon mode Amode[1..0], ON=0: ON 00 Ignore Accelerator-muons 01 Prefer Collision-muons by adding Promotion bit to them 10 Prefer Accelerator-muons by adding Promotion bit to them 11 Ignore Collision-muons Normal running mode ON CSC_ID Hex switch selects ALCT for inject, masks all Wire Group inputs. ON SW11-3 is a temporary exception. It changes the ADB test pulse polarity regardless of the SW11-1 setting. Page 50 of 104 11/01/00 10:05 AM JTAG Configuration The FPGA devices are connected to a "private" JTAG chain that is used to configure various internal registers. This chain is separate from the Altera JTAG chains that are used to write logic into the FPGA s and FlashRAMs. An "LVDS ByteBlaster" is used to connect the ALCT2000 to a PC parallel port. Each FPGA has custom TAP Controller logic that decodes JTAG instructions and reads or writes configuration registers. The ALCT2000 has 6 devices in the chain: Concentrator, Slow Control, LCT0, LCT1, LCT2, LCT3. The 3-LCT and 7-LCT versions of the ALCT design will have their LCT chips added to the chain in the same order. The EEPROM chip is intended to store JTAG sequences for rapid re-initialization of the FPGAs, but is not yet implemented. Figure 12: Configuration JTAG Chain TCK LVDS ByteBlaster Interface TDO TMS Concentrator TDI InstReg=4 ID=7 DevOrder=0 Slow Control InstReg=6 ID=8 DevOrder=1 LCT0 IR=4 ID=0 Order=2 LCT1 IR=4 ID=1 Order=3 LCT2 IR=4 ID=2 Order=4 LCT3 IR=4 ID=3 Order=5 TDO EEPROM TDI Table 32: Configuration JTAG Chain FPGA Concentrator Slow Control LCT 0 LCT 1 LCT 2 LCT 3 LCT 416 LCT 5 LCT 6 16 Order In Chain 0 1 2 3 4 5 6 7 8 Chip ID 7 8 0 1 2 3 4 5 6 Instruction Register Length 4 6 4 4 4 4 4 4 4 The number of LCT chips on the board depends on the CSC chamber type Page 51 of 104 11/01/00 10:05 AM Concentrator JTAG Programming The Concentrator chip is configured by writing to the instruction register to select an op code, then by reading or writing the selected register. At power-up, the register bits are all set to 0, which puts the Concentrator logic into an unusable state. The chip must be configured via JTAG or set to manual mode (SW11-1) before operating. All of the JTAG readable registers are implemented as two sets of identical shift-registers to allow nondestructive readout. The actual shift-register is used to store JTAG-write data, and is used to carry out the selected function. A "shadow" shift-register copies the output bits from its matching actual register. The "shadow" register is shifted-out to TDO during a JTAG read operation, and is over-written by TDI. The actual register remains unaffected. TAP Controller is a custom state machine with 16 states that correspond to the JTAG standard Test Access Port states. This state machine is implemented in AHDL logic and is not associated with the Altera FPGA built-in TAP controller used for loading the SRAM. Figure 13: TAP State Machine Page 52 of 104 11/01/00 10:05 AM JTAG TAP States The JTAG TAP state machines used in the LCT, Concentrator, and Slow Control FPGAs have 4-bit binary codes assigned to each state. The S0..S3 test points on the PCB indicate the current state of the TAP controller for each FPGA. Table 33: TAP Controller States State 0 1 2 3 4 5 6 7 8 9 A B C D E F Description Test Logic Reset Run Test Idle Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Page 53 of 104 11/01/00 10:05 AM Concentrator Instruction Register stores a 4-bit JTAG instruction. Instruction bits are shifted in LSB first from TDI. A fixed bit pattern of B"1001" is shifted out on TDO during the Shift-IR JTAG state to aid in software debugging. Concentrator instructions select which one of the configuration registers is placed between TDI and TDO during JTAG data cycles. Table 34: Concentrator JTAG Instruction Op Codes Op Code Binary Hex 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1111 F Op Code Name RdID RdCfg WrCfg RdTrig WrTrig RdCSC RdFStat RdFData Bypass Description Selected Register Length Read ID Register Read Control Register Write Control Register Read Trigger Register Write Trigger Register Read CSC ID Hex Switch Read Raw Hits Status Register Read Raw Hits Data Register Bypass Scan ID Register Control Register Shadow Control Register Trigger Register Shadow Trigger Register Hex Switch Status Register Data Register Bypass Register 40 69 69 2 2 4 14 32 1 Concentrator ID Register is a 40-bit read-only register that contains fixed information about the Concentrator chip, Altera logic, and chip ID number. Typical values are shown below, but the date and version fields can change value whenever the Altera logic is re-compiled. The chip ID number is hardwired on the printed circuit board. Table 35: Concentrator ID Register Field Bits Default [3..0] [7..4] [23..8] [31..24] [39..32] 4 4 16 8 8 7 C 1999 10 12 Total 40 [Hex] Description Chip ID number, fixed at 7 Software Version ID [0-F] Year: 4 BCD digits Day: 2 BCD digits Month: 2 BCD digits Page 54 of 104 11/01/00 10:05 AM Concentrator Control Register is a read/write shift-register that contains all of the programmable configuration bits for the Concentrator logic. Table 36: Concentrator Control Register Field Bits Default Name [Hex] Description Concentrator Trigger Modes [1..0] 2 0 trig_mode[1..0] [2] 1 0 ext_trig_en [3] 1 0 pretrig_halt Concentrator Trigger Mode: 0 = Pre-Trigger on either Collision muon or Accelerator muon pattern 1 = Only Pre-Trigger on Accelerator muon patterns 2 = Only Pre-Trigger on Collision muon patterns 3 = Pre-Trigger on Collision muons, accelerator muon vetoes Pre-Trigger External Trigger Enable: 0 = Ignore external trigger 1 = Enable external trigger (disables internal trigger) Pre-Trigger and Halt mode 0 = Normal run mode 1 = Pre-Trigger and Halt mode (toggle to resume from halt) Test Pattern Injector Modes [4] 1 0 inject [5] 1 0 inject_mode [12..6] 7 7F Inject_mask[6..0] Inject Test Pattern 0 = Do not inject test pattern 1 = Inject Test Pattern. See LCT inject mask & repeat mode, blocks ext_inject Injector Repeat Mode [requires Inject Test Pattern = 1] 0 = Continuous inject 1 = Inject 1 pulse Injector LCT Chip Mask [6..0]. Bit n maps to LCT chip n: 0 = LCT chip n ignores Test Pattern Inject command 1 = Enable LCT chip n to receive Test Pattern Inject command Pre-Trigger Controls [15..13] 3 2 nph_thresh[2..0] Number of Planes Hit Threshold for Pre-Trigger [18..16] 3 4 nph_pattern[2..0] Pattern hits required after drift delay to allow an LCT-trigger [20..19] 2 3 drift_delay[1..0] Drift delay after pre-trigger, 25n steps Range = 0 to 6 CSC layers Range = 0 to 6 CSC layers Range = 0 to 3 [0 to 75ns] Raw Hits FIFO Controls [25..21] 5 7 fifo_tbins[4..0] Total number of FIFO time bins per wire group [30..26] 5 1 fifo_pretrig[4..0] FIFO time bins before pre-trigger [included in total] [32..31] 2 1 fifo_mode[1..0] [35..33] 3 3 fifo_lastlct[2..0] Range = 0 to 31 decimal [25ns steps] Range = 0 to 31 decimal [25ns steps] FIFO Mode 0 = No raw hits dump 1 = Full dump [all LCT chips] 2 = Local dump [only LCT chips with hits] (not yet implemented) FIFO: Last LCT chip to be read out Allowed values: 3,4,6,7 [corresponding to the different ALCT board types] Page 55 of 104 11/01/00 10:05 AM Table 36: Concentrator Control Register (Continued) Field Bits Default [Hex] Name Description Level 1 Accept [43..36] 8 78h l1a_delay[7..0] Level 1 Accept delay after pre-trigger [47..44] [51..48] 4 4 3 0 l1a_window[3..0] l1a_offset[3..0] Level 1 Accept window width [25ns steps] Level 1 Accept counter Pre-Load value [arbitrary value] [52] 1 0 l1a_internal L1A generated internally during L1A window Range = 0 to 255 decimal Range = 0 to F hex 0 = L1A comes from CCB 1 = L1A generated automatically in L1A window Board ID, BXN, CCB [55..53] 3 5 board_id[2..0] ALCT2000 circuit board ID [arbitrary value] [59..56] 4 0 bxn_offset[3..0] Bunch Crossing Counter Offset [set to match Cathode LCT bxn] 0 ccb_enable [60] 1 Range = 0 to 7 Range = 0 to 255 decimal CCB Disable [Ignores CCB signals L1A, BXN, BxReset] 0 = Use CCB signals 1 = Ignore CCB signals [set CCB L1A,BXN,BxReset to 0] ALCT-Bus [61] 1 1 alct_jtag_ds [63..62] 2 0 alct_tmode[1..0] [65..64] 2 0 alct_amode[1..0] [66] 1 0 alct_mask_all [68..67] 2 0 alct_spare[1..0] Total ALCT-bus enable [affects all LCT chips] 0 = Individual ALCT JTAG control registers over-ride ALCT-bus 1 = Concentrator asserts ALCT-bus [LCT chips ignore their control registers] ALCT Test Pattern Mode [affects all LCT chips if alct_jtag_ds=1] 0 = Injector creates collision muon with 6 hits on wire-group 5 1 = Injector creates accelerator muon with 6 hits on wire-group 5 2 = Injector uses arbitrary test pattern register 3 = Not implemented [don't use it, Lisa!] ALCT Accelerator Muon Mode [affects all LCT chips] 0 = Ignore accelerator muons [give them pattern 0] 1 = Prefer Collision-muons by adding Promotion bit to them 2 = Prefer Accelerator-muons by adding Promotion bit to them 3 = Ignore Collision muons [give them pattern 0] Mask All Wire Group inputs to LCT chips [affects all LCT chips] 0 = Use LCT chip hot-channel mask registers to disable WG inputs 1 = Disable all LCT chip wire-group inputs [sets them to 0] ALCT-bus spare signals [not currently used, set to 0] 69 Page 56 of 104 11/01/00 10:05 AM Concentrator Trigger Register is a 2-bit read/write shift-register that generates various internal triggers. During a register-read instruction, the "shadow" copy of the actual Trigger Register is shifted out on JTAG TDO, so the read operation is non-destructive. Table 37: Concentrator Trigger Register Data Binary 00 01 10 11 Hex 0 1 2 3 Description Do Nothing Self-generate External Trigger Self-generate External Inject (test pattern) Self-generate External Test Pulse (ADB) Concentrator CSC ID Register is a 4-bit read-only register that contains the current position of the on-board hexadecimal-encoding rotary switch. This is intended to identify the CSC chamber number, but can be used for other purposes. Concentrator Raw Hits Status Register is 14-bit read-only "shadow" register that contains the status of the raw-hits JTAG FIFO sub-design. When the Concentrator's Sequencer state machine processes an event, the JTAG FIFO stores a copy of part of each data frame as it is transmitted to the DAQMB. When the transmission is completed, the "Data Available" bit goes high, and the "Data Frame Count" contains the number of frames available for read out. The current design stores up to 2048 frames. The frames are read out by issuing successive JTAG read commands to the Raw Hits Data Register. When the last frame has been read, the FIFO Empty bit goes high, and the Data Available bit returns to low. Table 38: Concentrator Raw Hits Status Register Field Bits [11..0] [12] [13] 12 1 1 Description Data Frame Count FIFO Empty Data Available Page 57 of 104 11/01/00 10:05 AM Concentrator Raw Hits Data Register is a 32-bit read-only register that contains 1 frame of DAQMB data. The frame number and a data-available flag are attached to aid in debugging. The dataavailable flag is high when more frames are ready for readout, and goes low in last frame. Table 39: Concentrator Raw Hits Status Register Field [18..0 ] [30..19] [31] Bits 19 12 1 Description DAQMB Data Frame Frame Number Data Available Flag Concentrator Bypass Register is a 1-bit read/write shift-register that is inserted between TDI and TDO when no other registers have been selected, or when the Bypass instruction is selected. Page 58 of 104 11/01/00 10:05 AM LCT JTAG Programming LCT Instruction Register stores a 4-bit JTAG instruction. Instruction bits are shifted in LSB first from TDI. A fixed bit pattern of B"1001" is shifted out on TDO during the Shift-IR JTAG state to aid in software debugging. LCT-chip instructions select which one of the configuration registers is placed between TDI and TDO during JTAG data cycles. Table 40: LCT JTAG Instruction Op Codes Op Code Binary Hex 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1111 F Op Code Name RdID RdCTL WrCTL RdHCM WrHCM RdATP WrATP Inject Bypass Description Read ID Register Read Control Register Write Control Register Read Hot Channel Mask Write Hot Channel Mask Read Arbitrary Test Pattern Write Arbitrary Test Pattern Inject Test Pattern Bypass Scan Selected Register ID Register Control Register Shadow Control Register Hot Channel Shadow Hot Channel Mask Arbitrary Test Shadow Arbitrary Test Pattern Bypass Bypass Length 40 8 8 96 96 96 96 1 1 LCT ID Register is a 40-bit read-only register that contains fixed information about the LCT chip, Altera logic, and chip ID number. Typical values are shown below, but the date and version fields can change value whenever the Altera logic is re-compiled. The chip ID number is hard-wired on the printed circuit board. Table 41: LCT ID Register Field Bits Default [3..0] [7..4] [23..8] [31..24] [39..32] 4 4 16 8 8 01,2,or 3 A 1999 08 12 Total 40 [Hex] Description Chip ID number depends on LCT chip Software Version ID [0-F] Year: 4 BCD digits Day: 2 BCD digits Month: 2 BCD digits Page 59 of 104 11/01/00 10:05 AM LCT Control Register is an 8-bit read/write shift-register that over-rides the ALCT-bus (i.e. Test Pattern Mode and Accelerator Muon mode) bits asserted by the Concentrator chip. Normally, the Concentrator Control Register ALCT-bus bits are connected by PCB traces to the LCT Control Register. In this case, ALCT JTAG Disable is logic 1, and the LCT chips use the Concentrator settings. If ALCT JTAG Disable is logic 0, the LCT chips use their independent Control Register values that can be set by a JTAG write to each LCT. During a JTAG register-read, a copy of the actual register is shifted out on TDO, so the read is non-destructive. Table 42: LCT Control Register Field Bits Default Description [0] 1 1 LCT JTAG Disable [read-only, set by Concentrator] 0 = Individual ALCT JTAG control registers over-ride ALCT-bus 1 = Concentrator asserts ALCT-bus [LCT chips ignore their control registers] [2..1] 2 0 Test Pattern Mode [ignored if alct_jtag_ds=1] 0 = Injector creates collision muon with 6 hits on wire-group 5 1 = Injector creates accelerator muon with 6 hits on wire-group 5 2 = Injector uses arbitrary test pattern register 3 = Not implemented [don't use it, Lisa!] [4..3] 2 0 ALCT Accelerator Muon Mode [ignored if alct_jtag_ds=1] 0 = Ignore accelerator muons [give them pattern 0] 1 = Prefer Collision-muons by adding Promotion bit to them 2 = Prefer Accelerator-muons by adding Promotion bit to them 3 = Ignore Collision muons [give them pattern 0] [5] 1 0 Mask All Wire Group inputs to this LCT chip [ignored if alct_jtag_ds=1] 0 = Disable all wire-group inputs [sets them to 0] 1 = Use hot-channel mask register to disable individual WG inputs [7..6] Total 2 0 ALCT-bus spare signals [not currently used, set to 0] 8 LCT Hot Channel Mask is a 96-bit read/write shift-register that disables individual Anode Wire Groups when their corresponding mask bits are set to logic 0. All wire-group inputs may be disabled by setting the mask-all bit to 0. Disabled WGs are not used for LCT pattern finding. During a register-read instruction, a copy of the actual Hot Channel Mask register is shifted out on JTAG TDO, so the read operation is non-destructive. The absolute wire group number is the local WG [0 to 15] plus 16 x LCT number [0 to 6]. Table 43: LCT Hot Channel Mask [1=enable a WG] Default Field [15..0] [31..16] [47..32] [63..48] [79..64] [95..80] Binary Ly0 Ly1 Ly2 Ly3 Ly4 Ly5 1111111111111111 1111111111111111 1111111111111111 1111111111111111 1111111111111111 1111111111111111 Description Layer 0 Wire Groups [15..0] Layer 1 Wire Groups [15..0] Layer 2 Wire Groups [15..0] Layer 3 Wire Groups [15..0] Layer 4 Wire Groups [15..0] Layer 5 Wire Groups [15..0] Page 60 of 104 11/01/00 10:05 AM LCT Arbitrary Test Pattern Register is a read/write shift-register that turns on a simulated hit for individual Anode Wire Groups when their corresponding register bits are set to logic 1. The simulated WG hits are used for LCT pattern finding, and can be read out from the Raw-Hits FIFO. During a register-read instruction, the "shadow" register copy of the actual Arbitrary Test Pattern register is shifted out on JTAG TDO, so the read operation is non-destructive. The absolute wire group number is the local WG [0 to 15] plus 16 x LCT number [0 to 6]. Table 44: LCT Arbitrary Test Pattern Register [1=enable a WG] Field [15..0] [31..16] [47..32] [63..48] [79..64] [95..80] Default 6 hits key 5 Binary [msb..lsb] Ly0 Ly1 Ly2 Ly3 Ly4 Ly5 0000000000100000 0000000000100000 0000000000100000 0000000000100000 0000000000100000 0000000000100000 Description Layer 0 Wire Groups [15..0] Layer 1 Wire Groups [15..0] Layer 2 Wire Groups [15..0] Layer 3 Wire Groups [15..0] Layer 4 Wire Groups [15..0] Layer 5 Wire Groups [15..0] LCT Inject Test Pattern is a 1-bit read/write shift-register that causes the LCT logic to assert the selected test pattern during the JTAG Update_DR state. The type of pattern is determined by the Test Pattern Mode bits in the Control Register. LCT Bypass Register is a 1-bit read/write shift-register that is inserted between TDI and TDO when no other registers have been selected. Page 61 of 104 11/01/00 10:05 AM Slow Control JTAG Programming Slow Control Instruction Register stores a 6-bit JTAG instruction. Instruction bits are shifted in LSB first from TDI. A fixed bit pattern of B"100001" is shifted out on TDO during the Shift-IR JTAG state to aid in software debugging. Slow Control instructions select either one of the configuration registers or the Serial Bus to be placed between TDI and TDO during JTAG data cycles. Table 45: Slow Control JTAG Instruction Op Codes Op Code Op Code Binary Octal 000 000 00 RdID Read ID Register None Selected Register ID Register 000 001 000 010 000 100 01 02 03 WThrs DRst WTp Reset Threshold DAC Reset Delay ASIC Write Test Pulse DAC /thr_reset /dly_reset /cs_test_pulse Bypass Bypass Serial Bus 1 1 8 001 000 001 001 001 010 001 011 10 11 12 13 WThr0 WThr1 WThr2 WThr3 Write Threshold DAC 0 Write Threshold DAC 1 Write Threshold DAC 2 Write Threshold DAC 3 /cs_write_thr0 /cs_write_thr1 /cs_write_thr2 /cs_write_thr3 Serial Bus Serial Bus Serial Bus Serial Bus 12 12 12 12 010 000 010 001 010 010 010 011 010 100 20 21 22 23 24 RThr0 RThr1 RThr2 RThr3 RThr4 Read Threshold ADC 0 Read Threshold ADC 1 Read Threshold ADC 2 Read Threshold ADC 3 Read Threshold ADC 4 /cs_read_thr0 /cs_read_thr1 /cs_read_thr2 /cs_read_thr3 /cs_read_thr4 Serial Bus Serial Bus Serial Bus Serial Bus Serial Bus 8 8 8 8 8 011 000 011 001 011 010 011 011 011 100 011 101 011 110 30 31 32 33 34 35 36 WDly0 WDly1 WDly2 WDly3 WDly4 WDly5 WDly6 Write Delay ASIC Grp0 Write Delay ASIC Grp1 Write Delay ASIC Grp2 Write Delay ASIC Grp3 Write Delay ASIC Grp4 Write Delay ASIC Grp5 Write Delay ASIC Grp6 /cs_write_dly0 /cs_write_dly1 /cs_write_dly2 /cs_write_dly3 /cs_write_dly4 /cs_write_dly5 /cs_write_dly6 Serial Bus Serial Bus Serial Bus Serial Bus Serial Bus Serial Bus Serial Bus 24 24 24 24 24 24 24 100 000 100 001 100 010 100 011 100 100 100 101 100 110 100 111 40 41 42 43 44 45 46 47 WTpg RTpg WTps RTps WSbr RSbr WTpd RTpd Write Test Pulse Group Read Test Pulse Group Write Test Pulse Strip Read Test Pulse Strip Write Standby Register Read Standby Register Write TP Power Down Read TP Power Down None None None None None None None None tp_group[] tp_group[] tp_strip[] tp_strip[] /standby[] /standby[] /tp_pd[] /tp_pd[] 7 7 6 6 42 42 1 1 111 111 77 Bypass Bypass Scan None Bypass 1 Description Chip Select Length 40 Page 62 of 104 11/01/00 10:05 AM Slow Control ID Register is a 40-bit read-only register that contains fixed information about the Slow Control chip, Altera logic, and chip ID number. Typical values are shown below, but the date and version fields can change value whenever the Altera logic is re-compiled. The chip ID number is hardwired on the printed circuit board. Table 46: Slow Control ID Register Field Bits Default [3..0] [7..4] [23..8] [31..24] [39..32] 4 4 16 8 8 8 B 1999 10 12 Total 40 [Hex] Description Chip ID number, fixed at 8 Software Version ID [0-F] Year: 4 BCD digits Day: 2 BCD digits Month: 2 BCD digits Reset Threshold DAC pulses /thr_reset to send a 1 TCK-wide pulse to reset the threshold DACs to their mid-range setting (127 counts = 1.240V). The 1-bit Bypass Register is inserted between TDI and TDO. Reset Delay ASIC pulses /dly_reset to send a 1 TCK-wide pulse to reset the Delay ASICs to 0 delay time. The 1-bit Bypass Register is inserted between TDI and TDO. Write Test Pulse DAC asserts /cs_test_pulse and connects the JTAG bus to the Slow Control Serial Bus. The Serial Bus is inserted between TDI and TDO. This 8-bit DAC controls the amplitude of the Analog Test Pulse sent to the ADBs. 1 LSB = 2.500V/256 = 9.8mV and V(n)=2.500V * n/256,where n=0..255. Write Threshold DAC(i, i=0..3) asserts /cs_write_thr(i) and connects the JTAG bus to the Slow Control Serial Bus. The Serial Bus is inserted between TDI and TDO. These 8-bit DACs control the amplitude of the ADB threshold voltage. 1 LSB = 2.500V/256 = 9.8mV and V(n)=2.500V * n/256, where n=0..255. The DACs are organized as 12 channels of 12 data bits per DAC-chip. The 12 data bits contain 8 DAC data bits [7..0] and 4 DAC address bits [11..8]. The DACs use the SPI data format, which sends the MSB first (JTAG is LSB first). See the manufacturers data sheet for more detail (Texas Instruments, www.ti.com, device TLC542DW) Page 63 of 104 11/01/00 10:05 AM Table 47: Threshold DAC Channel Assignments17 DAC Chip DAC0 DAC0 DAC0 DAC0 DAC0 DAC0 DAC0 DAC0 DAC0 DAC0 DAC0 DAC0 Ch ADB 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 DAC Chip DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 Ch ADB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DAC Chip DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 Ch ADB 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 DAC Chip DAC3 DAC3 DAC3 DAC3 DAC3 DAC3 DAC3 DAC3 DAC3 DAC3 DAC3 DAC3 Ch ADB 0 1 2 3 4 5 6 7 8 9 10 11 36 37 38 39 40 41 Read Threshold ADC(i, i=0..4) asserts /cs_read_thr(i) and connects the JTAG bus to the Slow Control Serial Bus. The Serial Bus is inserted between TDI and TDO. These 8-bit ADCs read-back digitized ADB threshold voltages, power supply voltages, currents, and the on-board temperature. 1 LSB = 2.500V/256 = 9.8mV and V(n)=2.500V * n/256, where n=0..255. The ADCs are organized as 12 channels of 8 data bits per ADC-chip. Only 11 channels are available for ALCT voltages, the 12th channel reads the ADC internal reference voltage. As the 8 data bits are shifted out to the Serial Bus (MSB first), the 4-bit address for the next channel to be read is shifted in (along with 4 dummy bits. The ADCs use the SPI data format, which sends the MSB first (JTAG is LSB first). For more detail, see the manufacturers data sheet (Analog Devices, www.analogdevices.com, device AD8802AR). ADC chips 3 and 4 are not implemented on ALCT2000-384, and their signals are not defined. Table 48: ADC0 Channel Assignments 17 Chip Ch ADC0 ADC0 ADC0 ADC0 ADC0 ADC0 ADC0 ADC0 ADC0 ADC0 ADC0 ADC0 0 1 2 3 4 5 6 7 8 9 10 11 Function ADB 23 Threshold ADB 22 Threshold ADB 21 Threshold ADB 20 Threshold ADB 19 Threshold ADB 18 Threshold ADB 17 Threshold ADB 16 Threshold ADB 15 Threshold ADB 14 Threshold ADB 13 Threshold Internal Reference Conversion 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV Expect 127±1 counts Only DAC0 and DAC1 are implemented on ALCT2000-384 Page 64 of 104 11/01/00 10:05 AM Table 49: ADC1 Channel Assignments Chip Ch ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 0 1 2 3 4 5 6 7 8 9 10 11 Function ADB 12 Threshold ADB 11 Threshold ADB 10 Threshold ADB 9 Threshold ADB 8 Threshold ADB 7 Threshold ADB 6 Threshold ADB 5 Threshold ADB 4 Threshold ADB 3 Threshold ADB 2 Threshold Internal Reference Conversion 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV Expect 127±1 counts Table 50: ADC2 Channel Assignments Chip Ch ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 0 1 2 3 4 5 6 7 8 9 10 11 Function ADB 1 Threshold ADB 0 Threshold Current +2.5V Current +3.3V Current -4.3V Current +5.5V Voltage +2.5V Voltage +3.3V Voltage +5.5V Voltage -4.3V Temperature Internal Reference Conversion 1 ADC mV = 1 DAC mV 1 ADC mV = 1 DAC mV Tc=25+100*(Vadc-0.750V) Expect 127±1 counts Page 65 of 104 11/01/00 10:05 AM Write Delay ASIC Group(i, i=0..6) asserts /cs_write_dly(i) and connects the JTAG bus to the Slow Control Serial Bus. The Serial Bus is inserted between TDI and TDO, and writes delay times into the Delay ASICs. The ASICs have 4-bit serial registers that use the same MSB-first SPI data format as the DACs and ADCs. Groups of 6 Delay ASICs make up a 24-bit serial chain, with the lowest numbered chip at the start of the chain. The full-scale delay is determined by external resistors, and is nominally 32ns. The output pulse width also is determined by external resistors, and is about 35ns. Table 51: Delay ASIC Group Assignments18 24-bit Group 0 1 2 3 4 5 6 ADBs In Group ADB 0-5 ADB 6-11 ADB 12-17 ADB 18-23 ADB 24-29 ADB 30-35 ADB 36-41 Write Test Pulse Group stores the bits tp_group[] to specify which groups are enabled for the Analog Test Pulse. The Analog Test pulse is initiated either by an external TTL signal or by a command to the Concentrator Chip (for synchronization to the 40MHz clock). Individual ADBs can not be selected to receive the Test Pulse, but instead are arranged in groups of 6: Table 52: Analog Test Pulse ADB Group Assignments Group 0 Group 1 Group 2 Group 3 Group 4-6 ADBs 00,01,02, 12,13,14 ADBs 03,04,05, 15,16,17 ADBs 06,07,08, 18,19,20 ADBs 09,10,11, 21,22,23 Not implemented on ALCT2000-384 Read Test Pulse Group is a non-destructive readout of a copy of the bits stored in the tp_group[] register. Bits shifted in by JTAG TDI are ignored. Write Test Pulse Strip stores the bits tp_strip[] to specify which CSC Anode strips are enabled for the Analog Test Pulse. The register bits are mapped one-to-one with the Pulse Strips. 18 Only groups 0..3 are implemented on ALCT2000-384 Page 66 of 104 11/01/00 10:05 AM Read Test Pulse Strip is a non-destructive readout of a copy of the bits stored in the tp_strip[] register. Bits shifted in by JTAG TDI are ignored. Write Standby Register stores the bits /standby[]. Logic 0 shuts down the Anode Discriminator Board power regulator for the selected boards. The register bits are mapped one-to-one with the ADB cards. Read Standby Register is a non-destructive readout of a copy of the bits stored in the /standby[] register. Bits shifted in by JTAG TDI are ignored. Write TP Power Down stores the Test Pulse Generator control bit /tp_pd[]. Logic 0 shuts down the Test Pulse Generator. Read TP Power Down is a non-destructive readout of a copy of the bit stored in the /tp_pd[] register. Bits shifted in by JTAG TDI are ignored. Bypass Scan is a 1-bit read/write shift-register that is inserted between TDI and TDO when no other registers have been selected. Page 67 of 104 11/01/00 10:05 AM Altera Device Programming The Altera FPGAs and FlashRAMs can be programmed via JTAG. They use a separate connector on the PCB for this purpose. An LVDS-Byteblaster19 is required to connect the ALCT2000 to a PC parallel port. Altera's MAX+Plus II software is used to program the FPGAs and FlashRAMs. Altera FPGAs The Altera FPGA devices detect power-up, and automatically load their programming data from the FlashRAMs in about 250 milliseconds. It is possible to write new programming data to Altera FPGAs via JTAG, but that feature is not functional on the current ALCT2000-384 boards. Jumpers on the ALCT circuit board select whether the FPGAs are included in the programming JTAG chain. Altera Flash Memory The Flash Memory devices contain non-volatile programming data for the FPGAs. These devices are written using the LVDS Byteblaster. The current ALCT2000-384 boards have only these devices enabled in the Programming JTAG chain. Altera Programming JTAG Chain Jumpers on the ALCT circuit board select 1 of 3 modes for operating the Altera JTAG chain: Table 53: Programming JTAG Chain Modes Mode JTAG Chain 0 1 2 6 FPGAs only [Short Chain] 6 FlashRAMs only [Short Chain] 6 FPGAs + 6 FlashRAMs [Whole Chain] Figure 14: Programming JTAG Chains20 LVDS TDI ByteBlaster Interface TDI Concentrator FPGA Slow Control FPGA LCT0 FPGA LCT1 FPGA LCT2 FPGA LCT3 FPGA TDO Concentrator Flash RAM Slow Control Flash RAM LCT0 Flash RAM LCT1 Flash RAM LCT2 Flash RAM LCT3 Flash RAM TDO 19 A custom designed version of Altera Byteblaster. It functions exactly like a ByteBlaster, but the I/O levels are translated to LVDS. 20 Switches and JTAG signals (TMS, TCK) have been suppressed for simplicity. See the ALCT2000 schematic for details. Page 68 of 104 11/01/00 10:05 AM Configuration Jumpers Various configuration options can be selected with the 3-pin PCB jumpers. Shorting plugs ("shunts") are used to connect either pins 1 and 2 or pins 2 and 3: Table 54: ALCT2000 PCB Jumpers Jumper SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 Section Test Pulse Test Pulse Test Pulse JTAG JTAG JTAG JTAG JTAG Test Pulse Short 1-2 Disable Strip Test Pulse Disable ADB Group Test Pulse Power Down Test Pulse Generator FlashRAMs included in JTAG chain FlashRAMs included in JTAG chain Short JTAG chain (FPGA or Flash) Short JTAG chain (FPGA or Flash) FPGAs included in JTAG chain Select External Test Pulse from J12 Short 2-3 [Normal Position] Enable Strip Test Pulse Enable ADB Group Test Pulse Slow Control controls Test Pulser Power FlashRAMs out of JTAG chain FlashRAMs out of JTAG chain Whole JTAG chain (FPGA or Flash) Whole JTAG chain (FPGA or Flash) FPGAs out of JTAG chain Select Concentrator Test Pulse Page 69 of 104 11/01/00 10:05 AM Diagnostics Some functions of the ALCT2000 board can be checked by monitoring the test points and LED displays. Most of these diagnostics require a computer connected to the Configuration JTAG chain. LED Display Table 55: Concentrator LED Displays LED Color Function PreTrig L1A_OK No_L1A InvPat AMu Halt TCK TDI TDO TMS FEB0 FEB1 FEB2 FEB3 FEB4 FEB5 FEB6 JState3 JState2 JState1 JState0 blue green red red green red green green green green green green green green green green green green green green green Sequencer pre-triggered Level 1 Accept arrived in L1A window Level 1 Accept did not arrive in L1A window Insufficient number of layers hit after drift delay Accelerator muon caused pre-trigger Sequencer is in Halt state JTAG TCK JTAG TDI to Concentrator JTAG TDO from Concentrator JTAT TMS LCT Chip 0 has a valid pattern LCT Chip 1 has a valid pattern LCT Chip 2 has a valid pattern LCT Chip 3 has a valid pattern LCT Chip 4 has a valid pattern LCT Chip 5 has a valid pattern LCT Chip 6 has a valid pattern JTAG State bit 3 [msb]. See Table 33 for decoding JTAG State bit 2 JTAG State bit 1 JTAG State bit 0 [lsb] Table 56: Power Supply LED Displays LED Color Function +5.5VA -4.3VA +3.3VD +5VD +5VA -3.5VA +3.3VD +2.5VD red green red red red green red red +5.5VA_in, Input voltage -4.3VA_in, Input voltage +3.3VD_in, Input voltage +5V Digital, regulator output voltage +5V Analog, regulator output voltage -3.5V Analog, regulator output voltage +3.3V Digital, regulator output voltage +2.5V Digital, regulator output voltage Page 70 of 104 11/01/00 10:05 AM Test Points Table 57: Test Points TP Name Section Function TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 +2.5VD +3.3VD -3.5VA -4.3VA +5VA +5.5VA +5VD +3.3VD_in Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply +2.5V Digital, regulator output voltage +3.3V Digital, regulator output voltage -3.5V Analog, regulator output voltage -4.3V Analog, high-side shunt voltage +5V Analog, regulator output +5.5V Analog, low side shut voltage +5.5V Digital, regulator output +3.3V Digital, input voltage TP9 TP10 TP11 TP12 TP13 TP14 TP15 SC_F0 SC_F1 SC_F2 SC_F3 SC_F4 SC_F5 SC_F6 Slow Control Slow Control Slow Control Slow Control Slow Control Slow Control Slow Control Future0 Future-use pin, no permanent assignment Future1 Future2 Future3 Future4 Future5 Future6 TP16 +5.5VA_in TP17 -4.3VA_in Power Supply Power Supply +5.5VAnalog input voltage -4.3VAnalog input voltage TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 SC_F7 R0 R1 R2 R3 R4 R5 R6 R7 Slow Control Concentrator Concentrator Concentrator Concentrator Concentrator Concentrator Concentrator Concentrator Future7 Future0 Future-use pin, no permanent assignment Future1 Future2 Future3 Future4 Future5 Future6 Future7 TP27 TP28 TP29 TP30 S0 S1 S2 S3 LCT1 LCT1 LCT1 LCT1 JTAG State 0. See Table 33: TAP Controller States p53 for decoding JTAG State 1 JTAG State 2 JTAG State 3 TP31 TP32 TP33 TP34 OC0 OC1 OC2 OC3 LCT1 LCT1 LCT1 LCT1 Op Code 0. See Table 40: LCT JTAG Instruction Op Codes p59 for decoding Op Code 1 Op Code 2 Op Code 3 Page 71 of 104 11/01/00 10:05 AM Table 57: Test Points (Continued) TP35 TP36 TP37 TP38 S0 S1 S2 S3 LCT2 LCT2 LCT2 LCT2 JTAG State 0. See Table 33: TAP Controller States p53 for decoding JTAG State 1 JTAG State 2 JTAG State 3 TP39 TP40 TP41 TP42 OC0 OC1 OC2 OC3 LCT2 LCT2 LCT2 LCT2 Op Code 0. See Table 40: LCT JTAG Instruction Op Codes p59 for decoding TP43 TP44 TP45 TP46 S0 S1 S2 S3 LCT3 LCT3 LCT3 LCT3 JTAG State 0. See Table 33: TAP Controller States p53 for decoding JTAG State 1 JTAG State 2 JTAG State 3 TP47 TP48 TP49 TP50 OC0 OC1 OC2 OC3 LCT3 LCT3 LCT3 LCT3 Op Code 0. See Table 40: LCT JTAG Instruction Op Codes p59 for decoding TP51 TP52 TP53 TP54 S0 S1 S2 S3 LCT4 LCT4 LCT4 LCT4 JTAG State 0. See Table 33: TAP Controller States for p53 decoding JTAG State 1 JTAG State 2 JTAG State 3 TP55 TP56 TP57 TP58 OC0 OC1 OC2 OC3 LCT4 LCT4 LCT4 LCT4 Op Code 0. See Table 40: LCT JTAG Instruction Op Codes p59 for decoding TP59 TP60 TP61 TP62 TP63 TP64 TP65 TP66 Stat_PreTrig Stat_InvPat Stat_Halt Stat_TMB Stat_L1A_Win Stat_L1A Stat_DAQMB Stat_Seq_Busy Concentrator Concentrator Concentrator Concentrator Concentrator Concentrator Concentrator Concentrator Sequencer Pre-Trigger Sequencer found invalid pattern after drift delay Sequencer halted Sequencer transmitting LCTs to TMB Level 1 Accept Window Level 1 Accept Signal (must appear in the L1A Window) Sequencer transmitting data to DAQMB Sequencer busy processing an event TP67 TP68 TP69 TP70 OC0 OC1 OC2 OC3 Concentrator Concentrator Concentrator Concentrator Op Code 0. See Table 34: Concentrator JTAG Instruction Op Codes p54 Op Code 1 Op Code 2 Op Code 3 Op Code 1 Op Code 2 Op Code 3 Op Code 1 Op Code 2 Op Code 3 Op Code 1 Op Code 2 Op Code 3 Page 72 of 104 11/01/00 10:05 AM Table 57: Test Points (Continued) TP71 TP72 TP73 TP74 S0 S1 S2 S3 Slow Control Slow Control Slow Control Slow Control JTAG State 0. See Table 33: TAP Controller States p53 for decoding JTAG State 1 JTAG State 2 JTAG State 3 TP75 TP76 TP77 TP78 TP79 TP80 OC0 OC1 OC2 OC3 OC4 OC5 Slow Control Slow Control Slow Control Slow Control Slow Control Slow Control Op Code 0. See Table 45: Slow Control JTAG Instruction Op Codes p62 TP81 F0 TP82 F1 TP83 F2 LCT1 LCT1 LCT1 Future0 Future-use pin, no permanent assignment Future1 Future 2 TP84 F0 TP85 F1 TP86 F2 LCT2 LCT2 LCT2 Future0 Future-use pin, no permanent assignment Future1 Future 2 TP87 F0 TP88 F1 TP89 F2 LCT3 LCT3 LCT3 Future0 Future-use pin, no permanent assignment Future1 Future 2 TP90 F0 TP91 F1 TP92 F2 LCT4 LCT4 LCT4 Future0 Future-use pin, no permanent assignment Future1 Future 2 TP93 +2.5VD_in Power Supply +2.5V Digital, input voltage TCK Altera TMS Altera TDI Altera TDO Altera LVDS Receiver LVDS Receiver LVDS Receiver LVDS Receiver JTAG TCK for the Altera JTAG chain (TTL levels) JTAG TMS for the Altera JTAG chain JTAG TDI for the Altera JTAG chain JTAG TDO for the Altera JTAG chain TCK Config TMS Config TDI Config TDO Config LVDS Receiver LVDS Receiver LVDS Receiver LVDS Receiver JTAG TCK for the Configuration JTAG chain (TTL levels) JTAG TMS for the Configuration JTAG chain JTAG TDI for the Configuration JTAG chain JTAG TDO for the Configuration JTAG chain Test Pulse Ext Inject Ext Trig BX0 BxReset L1Accept Clock Clock2 LVDS Receiver LVDS Receiver LVDS Receiver LVDS Receiver LVDS Receiver LVDS Receiver LVDS Receiver LVDS Receiver External Test Pulse input signal (TTL level) External Inject command input External Trigger input Bunch Crossing 0 input Bunch Crossing Reset input U27-11 U27-5 U27-3 U28-1 U29-11 U29-5 U29-3 U28-7 U37-11 U36-13 U37-3 U36-3 U35-5 U36-11 U37-13 U37-5 Op Code 1 Op Code 2 Op Code 3 Op Code 4 Op Code 5 Level 1 Accept input (do not use this for timing, use tp63 & Tp64) 40MHz clock 40MHz clock2 (may not be present on ALCT2000-384) Page 73 of 104 11/01/00 10:05 AM Power Requirements The DC power required by ALCT2000 depends on the number of LCT FPGAs and the number of ADB cards installed. It also depends somewhat on the choice of programmed JTAG configuration options. However, power consumption is the same whether the LCT logic is idle or whether it is processing events at a high rate. Table 58: Power Supply Current [ALCT2000-384] Supply Voltage +5.5V22[24 ADBs] +5.5V [no ADBs] +3.3V +2.5V -4.3V ALCT Power 2.56A 0.16A 1.52A 0.40A 0.045A Idle After JTAG Configuration 2.68A 0.28A 1.53A 0.43A 0.12A 7.1W 8.2W At Power Up [Excludes ADBs] Inject Test Pattern21 1KHz 10KHz 2.68A 2.68A 0.30A 0.30A 1.54A 1.54A 0.43A 0.43A 0.12A 0.12A 8.3W 8.3W Test Pulse ADBs 1KHz 10KHz 2.68A 2.68A 0.30A 0.30A 1.52A 1.48A 0.43A 0.43A 0.12A 0.12A 8.3W 8.1W Table 59: Power Estimate for ALCT2000 Variants Wire Groups (per layer) LCT FPGAs ADBs 3 4 7 18 24 42 48 64 112 ADB Current -4.3V +5.5V ADB Power ALCT2000 Current -4.3V +2.5V +3.3V +5.5V ALCT2000 Power 1.80A23 2.40A 4.20A 14.8W 13.2W 23.1W 1.27A 0.32A 1.15A 0.23A 0.12A 0.43A 1.53A 0.30A 0.12A 0.75A 2.68A 0.52A 6.4W 8.3W 14.1W 1.15A - 21 Collision muon test patterns and all-wire-groups-hit test patterns gave the same results for power consumption ADB boards each use 0.1A± 5% @+5.5V based on measuring the first 100 boards at FNAL. ALCT2000 uses 0.30 Amperes of +5.5V with no ADB cards connected. 23 ADB current from the +5.5V supply is not known at the time of writing. 22 Page 74 of 104 11/01/00 10:05 AM ALCT2000 Connectors Table 60: ALCT2000 Connectors ID Pins Type J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 1 1 1 1 1 1 8 10 10 26 26 1 40 LEMO Coax LEMO Coax LEMO Coax LEMO Coax LEMO Coax LEMO Coax Power Header Header Header SCSI SCSI LEMO Coax Header | | | J36 40 Header Function Strip 0 Analog Test Pulse Output Strip 1 Analog Test Pulse Output Strip 2 Analog Test Pulse Output Strip 3 Analog Test Pulse Output Strip 4 Analog Test Pulse Output Strip 5 Analog Test Pulse Output Power Supply Input Altera LVDS ByteBlaster Configuration LVDS JTAG TMB Channel Link DAQMB Channel Link External Test Pulse Trigger Input ADB-0 I/O ADB-23 I/O J1-J6 Strip Test Pulse Outputs Function: Outputs Analog Test Pulse to CSC Strip Pulse Inputs. Connector Type: PCB: LEMO FPL.00.250.NTL J7 Power Connector Function: Power supply inputs. Connector Type: PCB: Molex-Waldom 39-29-1088 [Digikey WM3903]24 Cable: Molex-Waldom 39-01-2080 [Digikey WM3703] Figure 15: ALCT2000 Power Connector View As Seen By Cable On-Board Regulator Version 24 Low Voltage Distribution Board Version Pin 8 GND Pin 5 GND Pin 3 GND Pin 1 GND Pin 8 GND Pin 5 GND Pin 3 GND Pin 1 GND Pin 8 N/C Pin 6 +4.0 Pin 4 -4.3 Pin 2 +5.5 Pin 8 +2.5 Pin 6 +3.3 Pin 4 -4.3 Pin 2 +5.5 The production version will use a gold-plated connector. Page 75 of 104 11/01/00 10:05 AM J8 Altera LVDS ByteBlaster Function: Connects ALCT2000 to LVDS ByteBlaster for programming FPGAs. The signals on this connector are NOT compatible with the standard Altera ByteBlaster. Connector Type: PCB: 3M 3793-5002 Cable: 3M 3473-6600 Table 61: J8 Altera LVDS ByteBlaster Connector +TCK +TDO +TMS +5V +TDI 1 3 5 7 9 2 4 6 8 10 -TCK -TDO -TMS GND -TDI J9 Configuration LVDS JTAG Function: Connects ALCT2000 to LVDS ByteBlaster for configuring ALCT2000 logic registers. The signals on this connector are NOT compatible with the standard Altera ByteBlaster. Connector Type: PCB: 3M 3793-5002 Cable: 3M 3473-6600 Table 62: J9 Configuration LVDS ByteBlaster Connector +TCK +TDO +TMS +5V +TDI 1 3 5 7 9 2 4 6 8 10 -TCK -TDO -TMS GND -TDI Page 76 of 104 11/01/00 10:05 AM J10 TMB Channel Link Function: Transmits channel link outputs to TMB [via LCT99-Passthru]. Receives clock and Test Pulse from LCT99-Passthru Connector Type: PCB: AMP 787190-2 Cable: AMP 1-749111-0 Shell: AMP 749608-1 Table 63: J10 TMB Channel Link Connector Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal Link ID TxOUT0+ TxOUT0TxOUT1+ TxOUT1TxOUT2+ TxOUT2TxCLKOUT+ TxCLKOUTTxOUT3+ TxOUT3TxOUT0+ TxOUT0TxOUT1+ TxOUT1TxOUT2+ TxOUT2TxCLKOUT+ TxCLKOUTTxOUT3+ TxOUT3Clock+ ClockTestPulse+ TestPulseGnd Gnd+Drain TMB0 LVDS Channel Link TMB1 LVDS Channel Link Reserved Terminated in 100 ohms on ALCT2000 Ground Table 64: AMP SCSI Connector 26HD Pin Locations [View From PCB Top] 1 • 3 5 • 9 • 13 • 17 • 21 • 25 • 7 11 15 19 23 2 • 6 • 10 • 14 • 18 • 22 • 26 • • • • • • • 4 • 8 • 12 • 16 • 20 • 24 • Page 77 of 104 11/01/00 10:05 AM J11 DAQMB Channel Link Function: Transmits channel link outputs to DAQMB [via LCT99-Passthru]. Receives CCB and Front-panel ECL signals from LCT99-Passthru Connector Type: PCB: AMP 787190-2 Cable: AMP 1-749111-0 Shell: AMP 749608-1 See Table 64: AMP SCSI Connector 26HD Pin Locations [View From PCB Top for connector pin locations, on page 77 above. Table 65: J11 DAQMB Channel Link Connector Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal TxOUT0+ TxOUT0TxOUT1+ TxOUT1TxOUT2+ TxOUT2TxCLKOUT+ TxCLKOUTTxOUT3+ TxOUT3BX0+ BX0BxReset+ BxResetL1Accept+ L1AcceptExtInject+ ExtInjectExtTrig+ ExtTrigClock2+ Clock2Reserved1+ Reserved1Gnd Gnd+Drain Link ID DAQMB0 LVDS Channel Link LVDS Signals From LCT99-Passthru: Terminated in 100 ohms on ALCT2000. Ground J12 Analog Test Pulse Trigger Input Function: Signal to Concentrator to trigger Analog Test Pulse generator. Fires Analog Test Pulse directly if Jumper SW9 is on position 1-2. Connector Type: PCB: LEMO FPL.00.250.NTL Page 78 of 104 11/01/00 10:05 AM J13-J36 ADB I/O Function: Receives 16 LVDS discriminator signal pairs from ADB cards. Sends power, test pulse, and regulator control signals to ADB cards. Connector Type: PCB: AMP 102153-9 Ejector: AMP 102320-1 Cable: AMP 746285-9 Table 66: J13-J36 ADB I/O Connector +Outs0 +Outs1 +Outs2 +Outs3 +Out_0 +Out_1 +Out_2 +Out_3 +Outs4 +Outs5 +Outs6 +Outs7 +Out_4 +Out_5 +Out_6 +Out_7 GND /Stand_By +5.5VA Test_Pulse 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 -Outs0 -Outs1 -Outs2 -Outs3 -Out_0 -Out_1 -Out_2 -Out_3 -Outs4 -Outs5 -Outs6 -Outs7 -Out_4 -Out_5 -Out_6 -Out_7 GND Vthr -4.3VA GND Page 79 of 104 11/01/00 10:05 AM LCT99-Passthru Module LCT99 Overview A modified LCT99 module is used to connect ALCT2000 to existing versions of the TMB, DAQMB, and CCB. Ribbon cables from these modules connect to the rear of the LCT99. Two Skewclear cables connect from the front of LCT99 to ALCT2000. Figure 16: LCT99 Overview LCT99-Passthru Module ----- J10 ----- 1st LCT[27..0] ALCT2000 FEB0 J6 TMB 2nd LCT[27..0] 1st LCT[27..0] 2nd LCT[27..0] TMB 40 MHz Clock Test Pulse Active FEB Flag Active FEB[6..0] FEB4 J5 DAQMB Active FEB Flag Active FEB[6..0] DAQMB FIFO[20..0] FIFO[20..0] J7 CCB BX0 BX0 CCB BXReset BXReset L1Accept L1Accept Ext_Inject 40MHz Clock 40MHz Clock L1Accept BxReset Bx0 Ext_Trig J9 ECL In ECL Clock 7,8 ECL Ext_Trig 5,6 ECL Ext_Inject ECL Test Pulse ECL Test Pulse 3,4 1,2 SW14-5 J8 ECL Out 13,14 ECL L1Accept 11,12 ECL DAQMQ /wr 9,10 ECL xTMB 7,8 ECL InvPat 5,6 ECL Active FEB SH18 321 15,16 ECL xDAQMB ECL Seq Busy SH19 SW14-4 321 3,4 1,2 Page 80 of 104 11/01/00 10:05 AM LCT99 Logic The main function of the LCT99-Passthru module is to provide cable connections between ALCT2000 and the existing CCB, TMB, and DAQMB modules. Communication to ALCT2000 takes place over the two 8-meter Skewclear cables that connect to the LCT99 front panel SCSI connectors. Connections to the CCB, TMB, and DAQMB take place over rear-module ribbon cables that are compatible with the old CLCT99 and ALCT99 units. LCT99-Passthru Mod Modified ALCT99/CLCT99 modules serve as LCT99-Passthru's. The LCT99s front-panel ECL inputs are used to send Test Pulse, External Inject, and External Trigger signals to ALCT2000 over the FEB4 Skewclear cable. To accommodate these and other signals, the LCT99 circuit boards have to be modified. One FEB4 channel link receiver is disconnected, a discrete LVDS transmitter chip is added, and several jumper wires are installed. Silkscreen labels on the LCT99-Passthru LEDs and switches are not changed, so the label names may not always match the new functions. Shadow Sequencer The LCT99 ECL-Output signals provide information about the state of the ALCT2000 Sequencer logic. ALCT2000 does not send all of these signals to LCT99 as discrete bits. Instead, a "Shadow Sequencer" in the LCT99 FPGA examines the LCT and raw-hits signals that ALCT2000 sends to the TMB and DAQMB, and infers the current status of the ALCT2000 Sequencer state machine resident in the Concentrator FPGA. The Shadow sequencer creates the ECL-Outputs and drives the LCT99 LED display. TMB LCT data for the best 2 muons are received from ALCT2000 by LCT99 via 2 LVDS channel links on the FEB0 Skewclear connector. Logic in LCT99 latches the data each clock cycle and forwards it unaltered to the TMB via 2 LVDS channel link transmitters on the J6 ribbon connector. If the valid pattern flag is set in the LCT data words, LCT99 latches the TMB data for display on the front panel LEDs. The Shadow Sequencer recognizes that the ALCT2000 Sequencer must have just been in the XTMB state, and changes its own state to match. LCT99 was originally designed to receive data from Cathode Front End Boards, which only use 24 of the 28 available LVDS channel link bits. Only the first 24 bits [23..0] from the ALCT TMB channel links are read into the LCT99 FPGA. The remaining 4 bits [27..24] are set to 0 in the full 28-bit frames transmitted to the TMB. The current ALCT2000 design does not use these 4 bits, so no data bits are lost by LCT99. Page 81 of 104 11/01/00 10:05 AM DAQMB Raw-hits data are received from ALCT2000 by LCT99 via an LVDS channel link on the FEB4 Skewclear connector. Logic in LCT99 latches the data each clock cycle and forwards it unaltered to the DAQMB via an LVDS channel link transmitter on the J5 ribbon connector. If the DAQMB data stream contains a first-header-word flag, the Shadow Sequencer recognizes that the ALCT2000 Sequencer must have just been in the XDAQMB state, and changes it's own state to match. The DAQMB data stream requires the first 25 channel link data bits [24..0], but the LCT99 circuit board only connects 24 bits [23..0] to the FPGA. The 24th bit is brought into the FPGA by a jumper wire on the LCT99-Passthru module. CCB The Clock and Control Board distributes the 40MHz clock, BX0, BxReset, and Level 1 Accept signals to the LCT99, TMB, and DAQMB modules. LCT99 receives these signals on the J7 rear-module ribbon connector and transmits them to ALCT2000 on the FEB4 Skewclear cable. The LCT99 FPGA can also generate it's own BX0 and BxReset signals for debugging ALCT2000s CCB logic. Level 1 Accept LCT99 contains logic to generate Level 1 Accept for use by the CCB. The L1A signal may be initiated from one of several sources (SW5). It is then delayed an adjustable length of time (SW3, SW4), in precise 25ns steps, before being sent to the ECL Output connector. LCT99 does not use this L1A for its own logic or for transmission to ALCT2000. Instead, it relies on the L1A signal it receives from the CCB ribbon cable, even though that CCB L1A may have been originated in LCT99! The L1A ECL Output comes from the signal source selected by SW5 "L1A_Window" (this name is left over from CLCT99). In general, changing the source of L1A will require re-adjusting the delay in LCT99 (SW3, SW4) and may require re-loading the L1A delay value in the ALCT2000 Concentrator FPGA. See the section "L1A Output Source Switch [SW5 L1A_Window]" on page 87 for the L1A source options. ALCT2000 can be programmed to generate an internal L1A. However, this L1A is not sent to the CCB, so other modules, such as the DAQMB will not receive it. Page 82 of 104 11/01/00 10:05 AM ECL Inputs Test Pulse Input sends a Test_Pulse signal to the ALCT2000 Concentrator. The Concentrator FPGA generates a 200ns signal to the ALCT2000 Analog Pulse Generator. The source of the Test Pulse may be either the ECL input or the Configuration DIP-Switch. The ECL Test Pulse input must be at least 25ns wide to be recognized by the ALCT2000 Concentrator. It should be less than 200ns wide to avoid re-triggering the Concentrator Test Pulse logic. For a Configuration DIP-Switch Test Pulse, set SW14-2 to select the LCT99 10KHz oscillator. Since the ALCT2000 Test Pulse signal does not pass through the LCT99 FPGA, an external wire-pair jumper is needed from ECL Output pins [15,16] to ECL Input pins [1,2]. Although the Test Pulse input can be an asynchronous signal, it will be latched by the Concentrator FPGA on the rising edge of the ALCT2000s 40MHz clock. The subsequent Analog Test Pulse output will be synchronized to the 40MHz clock also. To supply a completely asynchronous Analog Test Pulse, the LEMO connector on the ALCT2000 must be used as the Test Pulse trigger input [ALCT Shunt SW9 must be moved to the 1-2 position]. External Inject Input sends an ext_inject signal to the ALCT2000 Concentrator. The Concentrator FPGA then issues an inject command to the LCT FPGAs. The source of the External Inject may be either the ECL input or the Configuration DIP-Switch. For an ECL External Inject, set shunt SH18 to position 2-3 to select the ECL input. The ECL signal must be at least 25ns wide to be recognized by LCT99. It should be less than 60ns wide to avoid retriggering ALCT2000 injector logic. For a Configuration DIP-Switch External Inject, set SH18 to position 1-2 to select SW14 as the source. Setting SW14-5 will issue one ext_inject pulse to ALCT2000. If SW14-3 is also set, ext_inject will be pulsed continuously at 10KHz. See Table 72: LCT99-Passthru Configuration Shunts on page 89, and Table 67: LCT99 Configuration Switch SW14 on page 86. ALCT2000 will ignore the External Inject unless the Concentrator FPGA has been configured via JTAG to be in one of the Pattern Trigger Modes (i.e. not in External Trigger Mode). See Table 36: Concentrator Control Register on page 55. An External Inject command may or may not cause a ALCT2000 pre-trigger, depending on the pattern injector configuration. The LCT FPGAs must be programmed via JTAG to select the type of anode hitpattern to be inserted in the ADB data stream, and the Concentrator FPGA must be programmed to select which LCT FPGAs will receive the inject command. See Table 5: Injector Test Pattern Modes on page 20, Table 36: Concentrator Control Register on page 55, and Table 42: LCT Control Register on page 60. Page 83 of 104 11/01/00 10:05 AM External Trigger Input sends an ext_trig signal to the ALCT2000 Concentrator. The source of the External Trigger may be either the ECL input or the Configuration DIP-Switch. For an ECL External Trigger, set shunt SH19 to position 2-3 to select the ECL input. The ECL signal must be at least 25ns wide to be recognized by LCT99. It should be less than 100ns wide to avoid retriggering ALCT2000. For a Configuration DIP-Switch External Trigger, set SH19 to position 1-2 to select SW14 as the source. Setting SW14-4 will issue one ext_trig pulse to ALCT2000. If SW14-3 is also set, ext_trig will be pulsed continuously at 10KHz. See Table 72: LCT99-Passthru Configuration Shunts on page 89, and Table 67: LCT99 Configuration Switch SW14 on page 86. ALCT2000 will ignore the External Trigger unless the Concentrator FPGA has been configured via JTAG to be in External Trigger Mode. See Table 36: Concentrator Control Register on page 55. When the ECL External Trigger is correctly timed-in, the ADB raw hits should appear in time bin 1 in the DAQMB dump. The LCT pattern finding results to the TMB will not be correct if ext_trig is out of time. ECL Clock Input can be used instead of the CCB clock or the LCT99 40MHz crystal clock. See Table 72: LCT99-Passthru Configuration Shunts,on page 89, [set SH15 to 1-2]. Page 84 of 104 11/01/00 10:05 AM ECL Outputs Active FEB Flag is a 25ns pulse that indicates the ALCT Sequencer has pre-triggered and is processing an event. The pre-trigger may or may not result in a subsequent LCT data transmission to the TMB and raw hits data to the DAQMB. If the Sequencer pre-triggers but fails to find a valid LCT hit-pattern after waiting for the CSC drift delay, it returns to the Idle state and does not output an LCT to the TMB. Sequencer Busy is a variable width pulse that is asserted as soon as the Sequencer pre-triggers. It stays asserted until the Sequencer returns to the Idle state. New events can not be processed while the Sequencer is busy. New triggers from any source are ignored until the Sequencer returns to the Idle state. The length of the busy signal depends on whether a valid pattern is found, and on the number of raw-hits time bins sent to the DAQMB. Invalid Pattern is a 25ns pulse that indicates the Sequencer failed to find a valid LCT hit-pattern after the CSC drift delay. This signal is inferred from observing that an Active FEB flag was not soon followed by a TMB Transmission bit. The frequency of the Invalid Pattern condition depends on the choice of pattern-trigger threshold and the CSC drift delay. TMB Transmission is a 25ns pulse that indicates ALCT2000 is transmitting an LCT data frame to the TMB. This occurs if the Sequencer pre-triggers and finds a valid LCT hit-pattern after the CSC drift delay. LCT data bits are latched by the LCT99 display logic when this signal is detected. DAQMB FIFO /write_enable is an active-low signal that indicates a raw-hits dump to the DAQMB is in progress. The width of the signal depends on the number of raw-hits time bins in the dump. The DAQMB writes the raw-hits data while /write_enable is low. Level 1 Accept Output is a 25ns pulse that can be routed to the CCB for distribution to the DAQMB, TMB, and ALCT2000 [via the LCT99-Passthru]. The Level 1 Accept Output may be derived from one of several sources. See the section "Level 1 Accept" on page 82 above. DAQMB Transmission is 25ns pulse that indicates ALCT2000 is sending the first raw-hits header frame to the DAQMB. Test Pulse Output is a 50ns pulse from the LCT99 FPGA that can be used to send a Test_Pulse signal to the ALCT2000 Concentrator. The source of the Test Pulse may be either the ECL input or the Configuration DIP-Switch (see Test Pulse Input, above). Page 85 of 104 11/01/00 10:05 AM LCT99 Configuration Configuration DIP-Switch SW14 SW14-1 CCB Source: Selects the source of CCB signals sent to the ALCT2000. Usually this will be set to select the CCB. It can also be set to select LCT99 logic as the source to aid in testing the CCB state machines in the ALCT2000. SW14-2 ADB Test Pulse: Generates a 2-clock-wide ADB Test Pulse that triggers the ALCT2000 Analog pulse generator at 10KHz. SW14-3 Pulse Ext_Trig or Ext_Inject Continuously: Generates a 10KHz clock signal for pulsing either ext_trig or ext_inject. Which signal is pulsed depends on the positions of SW14-4 and SW14-5. SW14-4 External Trigger: Enables ext_trig for pulsing. The source of the pulse may be a 10KHz oscillator (SW14-3) or the ECL input. An ext_trig pulse starts the ALCT Concentrator's Sequencer state machine to begin processing as if a pattern pre-trigger had been found by an LCT chip. SW14-5 External Inject: Enables ext_inject for pulsing. The source of the pulse may be a 10KHz oscillator (SW14-3) or the ECL input. An ext_inject pulse fires the LCT chip pattern injectors that insert a test pattern into the wire-group data stream. A pre-trigger may or may not ensue depending on the type of test pattern injected. SW14-6 40MHz Clock: Normally this will be enabled, as none of the ALCT FPGAs can function without a clock. Table 67: LCT99 Configuration Switch SW14 Setting On=0 [Normal] SW Label SW14-1 /enx ALCT CCB signal source Source = LCT99 Logic Source = CCB SW14-2 il1a ADB Test Pulse Fire at 10KHz No Test Pulse SW14-3 halt Pulse External Trigger or Pulse External Inject External Trigger ALCT Fire at 10KHz No Pulse SW14-4 [Ignore] resu Function Setting Off=1 SW14-4, SW14-5 select trig or inject Fire ext_trig Do nothing May be DC or pulsed or from ECL In SW14-5 injp External Inject ALCT Fire ext_inject Do nothing may be DC or pulsed from ECL In SW14-6 /fck - ALCT Clock Enable Turn off ALCT clock Enable ALCT 40MHz SW14-7 Not used SW14-8 Not used Page 86 of 104 11/01/00 10:05 AM CCB Mode Switch [SW11 Board ID] SW11 is hexadecimal rotary switch that controls LCT99 logic that internally generates CCB signals. SW14-1 DIP-Switch selects either the CCB or the LCT99 FPGA as the source of the CCB signals sent to ALCT2000. Table 68: LCT99 CCB Mode Switch [SW11] [Normal running position shown in bold] Hex 0 1 Function Normal running. Asserts BX0 after BxReset to resume running. Asserts BxReset [stops ALCT BXN counter] L1A Delay Switches [SW4=MSB, SW3=LSB] SW3 and SW4 are hexadecimal rotary switches that form an 8-bit binary number for the LCT99 internal Level 1 Accept delay. Delay steps are 25ns clock ticks. The delay count starts after LCT99 logic detects the "xtmb" state in the ALCT2000 [i.e. the point in time when ALCT2000 sends a channel link frame to the TMB]. L1A Output Source Switch [SW5 L1A_Window] SW5 is a hexadecimal rotary switch that selects the source of the Level 1 Accept signal sent to the LCT99 ECL Output connector [pins 11,1]. The L1A ECL output signal is delayed according to SW3 and SW4 [see above]. Table 69: L1A Output Source [SW5] [Normal running position shown in bold] Hex 0 1 2 3 Function L1A ECL output comes from the CCB L1A ECL output sent when LCT99 detects ALCT sending LCT to TMB [xtmb] L1A ECL output sent after ECL Input ext_trig received L1A ECL output always high [for debugging] Page 87 of 104 11/01/00 10:05 AM LED Display Mode Switch [SW12 CSC ID] SW12 is a hexadecimal rotary switch that selects the display mode for the LCT99 front panel LEDs. Table 70: LED Display Mode Switch [SW12] [Normal running position shown in bold] Hex 0 1 2 3 4 5 6 7 Function LCT0_[15..0] captured at xtmb time LCT0_[23..16] captured at xtmb time LCT1_[15..0] captured at xtmb time LCT1_[23..16] captured at xtmb time DAQMB Word Count [10..0] obtained by counting DAQMB frames in LCT99 DAQMB Word Count [10..0] extracted from ALCT2000 trailer frame LCT99 Summary LED Test [turns on all LEDs] LED Display Front-panel LEDs display information about data received from ALCT2000. The data displayed depends on the position of the LED Display Mode Switch [SW12]. Table 71: LCT99 LED Display Mode 0 or 2 Mode 1 or 3 Label Bit LED LCT 0/1 Bits[15..0] LCT 0/1 Bits[23..16] PRTRG L1A OK NOL1A INVPAT HALT FEB0 FEB1 FEB2 FEB3 FEB4 1ST 6 1ST 5 1ST4 2ND6 2ND5 2ND4 TCK CFD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - Blu Grn Red Red Red Grn Grn Grn Grn Grn Grn Grn Grn Grn Grn Grn Grn Grn lct[15] bxn[4] lct[14] bxn[3] lct[13] bxn[2] lct[12] bxn[1] lct[11] bxn[0] lct[10] key[6] lct[9] key[5] lct[8] key[4] lct[7] key[3] lct[6] key[2] lct[5] key[1] lct[4] key[0] lct[3] amu lct[2] pat[1] lct[1] pat[0] lct[0] valid pat - lct[23] 0 lct[22] 0 lct[21] 0 lct[20] 0 lct[19] 0 lct[18] 0 lct[17] 0 lct[16] 0 - Mode 6 [Normal Position] Summary Mode Active_feb_flag [ALCT Sequencer started] TMB valid pattern was followed by DAQMB header TMB valid pattern was not followed by DAQMB header Active_feb_flag not followed by TMB valid pattern DAQMB not followed by EOD frame LCT Chip 0 hit LCT Chip 1 hit LCT Chip 2 hit LCT Chip 3 hit -1st Best LCT has 6 hits 1st Best LCT has 5 hits 1st Best LCT has 4 hits 2nd Best LCT has 6 hits 2nd Best LCT has 5 hits 2nd Best LCT has 4 hits JTAG TCK Altera FPGA Configuration Done Page 88 of 104 11/01/00 10:05 AM LCT99 Configuration Shunts Table 72: LCT99-Passthru Configuration Shunts [Important Positions for LCT99-Passthru mod in bold] ID Shunt Position 1-2 Position 2-3 Normal SH0,2,4,6,8 SH1,3,5,7,9 SH10 SH11 SH12 Gnd FEB0-4 Channel Link cable drain wires Gnd FEB0-4 Channel Link cable shields Gnd DAQMB Channel Link cable shield Gnd TMB Channel Link cable shield Gnd CCB LVDS cable shield Float drains Float shields Float-shield Float-shield Float shield 1-2 1-2 1-2 1-2 1-2 SH13 SH14 Gnd vf_read1 DO NOT do for LCT99-Passthru Gnd vf_reset DO NOT do for LCT99-Passthru CCB enable signal FEB4[24] signal 2-3 2-3 SH15 SH16 SH17 Select ECL_clock as clock source Select 40MHz crystal as clock source Select CCB as clock source - SH18 SH19 Select Dip-switch SW14-5 as ext_inject source Select Dip-switch SW14-4 as ext_trig source Select ECL inject Select ECL trig 1-2 1-2 SH20-SH24 SH25-SH28 Connect 10K200E to JTAG chain Connect FlashRAM pair to JTAG chain Skip 10K200E Skip FlashRAMs 2-3 1-2 SH29 SH30 SH31 Enable TMB Channel Link 0 Enable TMB Channel Link 1 Enable DAQMB Channel Link Power down Power down Power down 1-2 1-2 1-2 OUT OUT IN Page 89 of 104 11/01/00 10:05 AM LCT99 Circuit Board Probe Points Table 73: LCT99-Passthru Circuit Board Probe Points ID[pins] P0[4..1] P1[4..1] P2[4..1] P3[4..1] P4[4..1] P5[4..1] P6[4..1] P7[4..1] P8[4..1] P9[4..1] P10[1] P10[2] P10[3] P10[4] P11[12..1] P12[12..1] P13[12..1] P14[1] P15[4..1] P16[1] P17[10..1] P18[10..1] P19[8..1] P20[10..1] P21[10..1] P22[8..1] P23[10..1] P24[10..1] P25[8..1] P26[1] P27[1] P28[1] P29[1] P30[1] P31[1] P32[1] P33[12..1] P34[12..1] Function FEB0 Channel Link 0 output bits [27..24] FEB0 Channel Link 1 output bits [27..24] FEB1 Channel Link 0 output bits [27..24] FEB1 Channel Link 1 output bits [27..24] FEB2 Channel Link 0 output bits [27..24] FEB2 Channel Link 1 output bits [27..24] FEB3 Channel Link 0 output bits [27..24] FEB3 Channel Link 1 output bits [27..24] FEB4 Channel Link 0 output bits [27..24] FEB4 Channel Link 1 output bits [27..24] ext_inject ext_trig enable CCB LVDS receiver feb4[24] (because clinks only receive 24 bits) Clock Probe [10..1]=rxclk[9..0], [11]=txclk (10K200K clock), [12]=clk_feb (to FEBs) FEB0 Link 0 received data Rxout bits [11..0] FEB0 Link 0 received data Rxout bits [23..12] Gnd [1]=Ccb_clk, [2]=ccb_bxo, [3]=ccb_bxreset, [4]=ccb_l1a Gnd TMB Link 0 data bits [9..0] TMB Link 0 data bits [19..10] TMB Link 0 data bits [27..20] TMB Link 1 data bits [9..0] TMB Link 1data bits [19..10] TMB Link 1data bits [27..20] DAQMB data bits [9..0] DAQMB data bits [19..10] DAQMB data bits [27..20] +5V current sense, high side. Current = (high side-low side)V/R(0.010ohms) +5V current sense, low side +3.3V current sense, high side +3.3V current sense, low side +2.5V current sense, high side +2.5V current sense, low side -5.2V FEB0 Link 1 received data Rxout bits [11..0] FEB0 Link 1 received data Rxout bits [23..12] Page 90 of 104 11/01/00 10:05 AM LCT99-Passthru Module Connectors FEB0 ßà ALCT2000 J10 Function: Receives channel link outputs from ALCT2000 J10 for re-transmission to TMB J6. Transmits clock and Test Pulse to ALCT2000. Connector Type: PCB: AMP 787190-2 Cable: AMP 1-749111-0 Shell: AMP 749608-1 Table 74: FEB0 ßà ALCT2000 J10 Connector Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal Link ID RxIN0+ RxIN0RxIN1+ RxIN1RxIN2+ RxIN2RxCLKIN+ RxCLKINRxIN3+ RxIN3RxIN0+ RxIN0RxIN1+ RxIN1RxIN2+ RxIN2RxCLKIN+ RxCLKINRxIN3+ RxIN3Clock+ [out] ClockTestPulse+ [out] TestPulseGnd Gnd+Drain TMB0 LVDS Channel Link TMB1 LVDS Channel Link Reserved Terminated in 100 ohms on ALCT2000 Ground Table 75: AMP SCSI Connector 26HD Pin Locations [View From PCB Top] 1 • 3 5 • 9 • 13 • 17 • 21 • 25 • 7 11 15 19 23 2 • 6 • 10 • 14 • 18 • 22 • 26 • • • • • • • 4 • 8 • 12 • 16 • 20 • 24 • Page 91 of 104 11/01/00 10:05 AM FEB4 ßàALCT2000 J11 Function: Receives channel link outputs from ALCT2000 J11 for re-transmission to DAQMB J5. Transmits BX0, RxReset, L1Accept, ExtInject, ExtTrig, Clock2 to ALCT2000. Connector Type: PCB: AMP 787190-2 Cable: AMP 1-749111-0 Shell: AMP 749608-1 Table 76: FEB4 ßà ALCT2000 J11 Connector Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal RxIN0+ RxIN0RxIN1+ RxIN1RxIN2+ RxIN2RxCLKIN+ RxCLKINRxIN3+ RxIN3BX0+ [out] BX0BxReset+ [out] BxResetL1Accept+ [out] L1AcceptExtInject+ [out] ExtInjectExtTrig+ [out] ExtTrigClock2+ [out] Clock2Reserved1+ Reserved1Gnd Gnd+Drain Link ID DAQMB0 LVDS Channel Link LVDS Signals From LCT99-Passthru: Terminated in 100 ohms on ALCT2000. Ground Page 92 of 104 11/01/00 10:05 AM J5 DAQMB Function: Transmits event dump data to the DAQMB over 1 LVDS channel link. Connector Type: PCB: 3M 2526-5002UB Cable: 3M 3399-6600 Table 77: LCT99-to-DAQMB LVDS Channel Link Connector Pin Signal 1 3 5 7 9 11 13 15 17 19 21 23 25 GND TxOUT0+ GND TxOUT1+ GND TxOUT2+ GND TxCLKOUT+ GND TxOUT3+ GND GND GND Pin Signal 2 4 6 8 10 12 14 16 18 20 22 24 26 GND TxOUT0GND TxOUT1GND TxOUT2GND TxCLKOUTGND TxOUT3GND GND Shield Drain Function Guard Cable Edge TxOUT0 Pair Isolate Adjacent Pairs TxOUT1 Pair Isolate Adjacent Pairs TxOUT2 Pair Isolate Adjacent Pairs TxCLKOUT Pair Isolate Adjacent Pairs TxOUT3 Pair Wasted Space Wasted Space Guard Cable Edge Page 93 of 104 11/01/00 10:05 AM J6 TMB Function: Transmits LCT data for the 2 best muons over 2 LVDS channel links to the TMB. Connector Type: PCB: 3M 2520-5002UB Cable: 3M 3425-6600 Table 78: LCT99-to-TMB LVDS Channel Link Connector Pin Signal 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 GND TxOUT0+ GND TxOUT1+ GND TxOUT2+ GND TxCLKOUT+ GND TxOUT3+ GND TxOUT0+ GND TxOUT1+ GND TxOUT2+ GND TxCLKOUT+ GND TxOUT3+ GND GND GND GND GND Pin Signal 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 GND TxOUT0GND TxOUT1GND TxOUT2GND TxCLKOUTGND TxOUT3GND TxOUT0GND TxOUT1GND TxOUT2GND TxCLKOUTGND TxOUT3GND GND GND GND Shield Drain Link ID Common Link 0: 1st Best Muon Link 1: 2nd Best Muon Common Function Guard Cable Edge TxOUT0 Pair Isolate Adjacent Pairs TxOUT1 Pair Isolate Adjacent Pairs TxOUT2 Pair Isolate Adjacent Pairs TxCLKOUT Pair Isolate Adjacent Pairs TxOUT3 Pair Isolate Adjacent Pairs TxOUT0 Pair Isolate Adjacent Pairs TxOUT1 Pair Isolate Adjacent Pairs TxOUT2 Pair Isolate Adjacent Pairs TxCLKOUT Pair Isolate Adjacent Pairs TxOUT3 Pair Guard Cable Edge Wasted Space ” ” GND Page 94 of 104 11/01/00 10:05 AM J7 CCB Function: Receives Clock, BX0, BxReset, and Level 1 Accept from the CCB module. Connector Type: PCB: 3M 2520-5002UB Cable: 3M 3421-6600 Table 79: LCT99 Clock & Control Board Connector Pin 1 3 5 7 9 11 13 15 17 19 Signal Pin Signal GND Clock GND BX0+ GND BxReset+ GND L1Accept+ GND GND 2 GND Clock GND BX0GND BxResetGND L1AcceptGND Shield Drain 4 6 8 10 12 14 16 18 20 Function 40MHz LHC Clock (Square Wave) Resume counting Stop counting, preset BXN & Event #. Level 1 Accept Page 95 of 104 11/01/00 10:05 AM J8 ECL Out Function: Outputs Front-panel ECL signals from the LCT99 FPGA. Connector Type: PCB: 3M 2516-5002 Cable: 3M 3452-6600 Table 80: LCT99 ECL Output Connector Pins +,1,2 3,4 5,6 7,8 9,10 11,12 13,14 15,16 Function Active FEB Flag [ALCT Sequencer started] Sequencer busy, not accepting new muons. Invalid pattern after pre-trigger and drift delay TMB transmission frame [LCTs going out to TMB] DAQMB FIFO /write_enable Level 1 Accept from ccb,xtmb, or ext_trig DAQMB transmission frame [Header going to TMB] Test Pulse output [Jump to ECL Input pin with wires] J9 ECL In Function: Inputs Front-panel ECL signals. Connector Type: PCB: 3M 2510-5002 Cable: 3M 3473-6600 Table 81: ECL Input Connector Pins +,1,2 3,4 5,6 7,8 9,10 Function Test Pulse Input [Needs jumper to ECL out 15] External Inject Input [set SH18 to 1-2] External Trigger Input [set SH19 to 2-3] ECL Clock Input [set SH15 to 1-2] Not connected Page 96 of 104 11/01/00 10:05 AM J10 ByteBlaster Function: Connects LCT99 to an Altera ByteBlaster (TTL) for programming FPGAs. The signals on this connector are NOT compatible with the LVDS ByteBlaster. Connector Type: PCB: 3M 3793-5002 Cable: 3M 3473-6600 Table 82: LCT99 ByteBlaster Connector Pin 1 2 3 4 5 6,7,8 9 10 Name TCK GND TDO +5V TMS TDI GND Function Test Clock input from ByteBlaster Ground Test Data Output to ByteBlaster Fused +5V source to ByteBlaster Test Mode Select from ByteBlaster Unused Test Data Input from ByteBlaster Ground Page 97 of 104 11/01/00 10:05 AM Operating Procedures System Cables The system normally consists of ALCT2000, LCT99-Passthru, CCB, TMB, and DAQMB modules. LCT99-Passthru connects all of these modules together. See Figure 1: System Diagram on page 9 for the connections. Cables from ALCT2000 to LCT99-Passthru must be Skewclear twisted-pairs, while the other connections are ordinary ribbon cable or twist-n-flat cable. LCT99-Passthru Configuration Setting up LCT99 consists of selecting switch settings and shunt positions. Although it is a VME module, it does not communicate with the VME backplane, and it is not computer programmable. LCT99 Switch Settings SW14 DIP-Switch is used mostly for self-tests. See Table 67: LCT99 Configuration Switch SW14 on page 86 for a full description. The normal-running configuration is: Table 83: LCT99 SW14 Normal Settings SW Label [Ignore] SW14-1 SW14-2 SW14-3 SW14-4 SW14-5 SW14-6 SW14-7 SW14-8 /enx il1a halt resu injp /fck - Normal Setting ON ON ON ON ON ON ON ON Hexadecimal Rotary Switches: For complete descriptions, see the sections starting with CCB Mode Switch [SW11 Board ID]on page 87. Usually only SW3,SW4 and SW5 need to be considered. Table 84: LCT99 Hex Switch Normal Settings SW SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12 Old LCT99 Label [Ignore] Plane Threshold Pattern Threshold L1A Count Offset L1A Delay LSB L1A Delay MSB L1A Window Drift Delay BXN Offset FIFO Pretrig TBins FIFO Time Bins FIFO Mode Board ID CSC ID New Passthru Function None None None LCT99 L1A Delay LCT99 L1A Delay L1A Source None None None None None CCB Source LED Display Normal Setting Don't Care Don't Care Don't Care Time it in Time it in 0 Don't Care Don't Care Don't Care Don't Care Don't Care 0 6 Page 98 of 104 11/01/00 10:05 AM LCT99 Shunt Settings are described in Table 72: LCT99-Passthru Configuration Shunts on page 89. Table 85: LCT99 Normal Shunt Settings ID SH0,2,4,6,8 SH1,3,5,7,9 SH10 SH11 SH12 SH13 SH14 SH15 SH16 SH17 SH18 SH19 SH20-SH24 SH25-SH28 SH29 SH30 SH31 Normal 1-2 1-2 1-2 1-2 1-2 2-3 2-3 OUT OUT IN 1-2 1-2 2-3 1-2 1-2 1-2 1-2 Page 99 of 104 11/01/00 10:05 AM ALCT2000 Configuration The ALCT2000 board is designed to be controlled almost exclusively via JTAG commands. Switches and shunts on the board must be in the normal running positions shown below to enable the full range of JTAG control. Switch Settings DIP-Switch SW11: ALCT2000 can run with or without JTAG initialization. The normal running mode is to require JTAG configuration of all registers, and the SW11 DIP-Switch is ignored. See the Manual Configuration section on page 50 for a full description of SW11. Table 86: ALCT2000 Normal SW11 Switch Settings SW11-n Normal Setting 1 2 3 4 5 6 7 8 9 10 11 12 ON ON ON ON ON ON ON ON ON ON ON ON CSC ID Hex-Switch can be read via JTAG commands. In the normal running mode, the switch may be set to any value. Configuration Jumpers are normally set to enable all functions on the ALCT2000. See Table 54: ALCT2000 PCB Jumpers on page 69 for a full description of the jumper settings. Table 87: ALCT2000 PCB Jumpers Normal Setting Jumper SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 Normal Position 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 Page 100 of 104 11/01/00 10:05 AM Level 1 Accept The ALCT2000 must receive a Level 1 Accept to initiate raw-hits readout to the DAQMB. At the LHC, L1A will arrive at the ALCT2000 about 3us after the bunch crossing that led to a muon trigger. ALCT2000 can generate its own internal Level 1 Accept signal for test purposes. However, the internal L1A is not sent to the DAQMB, and it would not read the ALCT raw hits data. L1A Source ALCT2000 can receive Level 1 Accept from many different sources. LCT99 gets L1A from the CCB and forwards it to ALCT2000 over the FEB4 Skewclear cable. L1A External Trigger For external triggering, such as from scintillators, standard NIM modules can send an L1A signal to the CCB. A stable delay of about 3us is needed from the time of the muon transit. Analog delays may drift or jitter too much to be reliable, so LCT99 has the ability to produce a precise, digital delay. See the section L1A Output Source Switch [SW5 L1A_Window] on page 87 for a description of LCT99's L1A delay. To use LCT99s L1A delay from an External Trigger: 1) Connect the scintillator trigger signal to LCT99s J9 ECL Input "External Trigger" [pins 5,6]. 2) Set LCT99 L1A Output Source [Hex SW5] to "2", which selects ext_trig as the L1A source. 3) Connect LCT99 J8 ECL Output L1A [pins 11,12] to the CCB's L1A front panel input. 4) Adjust LCT99 Hex Switches SW3,SW4 to time in L1A at the ALCT2000 board (see below). L1A Internal Trigger For internal triggering from the ALCT2000 muon hit-pattern finder, the L1A signal needs to be generated at a fixed delay time after the pattern is found. At the LHC, it is ALCT2000's LCT data transmission to the TMB that ultimately results in L1A being issued by the Global Trigger System. The Shadow Sequencer in LCT99 recognizes the point in time that ALCT2000 transmits its LCT data to the TMB. LCT99 can then generate an ECL L1A signal at an adjustable time later. To use LCT99s L1A delay from an Internal Trigger: 1) Set LCT99 L1A Output Source [Hex SW5] to "1", which selects xtmb as the L1A source. 3) Connect LCT99 J8 ECL Output L1A [pins 11,12] to the CCB's L1A front panel input. 4) Adjust LCT99 Hex Switches SW3,SW4 to time in L1A at the ALCT2000 board (see below). Page 101 of 104 11/01/00 10:05 AM L1A Time-in Procedure In general, if the source of L1A is changed (say from external trigger to internal trigger), L1A will need to be re-timed at the ALCT2000 module. There are several registers and switches that need to be tuned: 1) ALCT2000 L1A Delay [in the Concentrator Control Register on page 55] 2) ALCT2000 L1A Window Width [in the Concentrator Control Register on page 55] 3) LCT99 L1A Delay (optional) [SW3, SW4 on page 87] At the LHC, the ALCT2000 L1A window will be set to allow ±1 Bunch Crossing uncertainty. Then the ALCT2000 L1A Delay will be set to match the arrival time of the L1A signal from the Global Trigger System (via the CCB module). At the FAST sites, the situation is different. The DAQMB is programmed to expect L1A at a specific time. An easy procedure is to time in the CCB L1A signal to arrive within the DAQMBs window. Then program ALCT2000 to position its L1A window around the L1A signal. ALCT L1A Test Points Level 1 Accept and the L1A window used by ALCT2000 are available as TTL signals at test points on the ALCT2000 board near the Concentrator FPGA. Level 1 Accept is visible at TP64 "STAT_L1A" L1A Window is visible at TP62 "STAT_L1A_WIN" The L1A signal must arrive within the L1A Window: Figure 17: Level 1 Accept Signals On ALCT2000 PCB 3.2µs 25ns STAT_PRETRIG 75ns STAT_L1A_WINDOW 25ns STAT_L1A Page 102 of 104 11/01/00 10:05 AM FAQs 1) Q: Why is the ALCT2000 Blue Pre-Trigger LED always on? A: Most likely, the JTAG registers have not been initialized. At power-up all the JTAG register bits are set to 0. This makes the pattern pre-trigger threshold 0, which means the Sequencer will be constantly triggering and processing events having 0 hits. 2) Q: Why is LCT99 needed to generate Level 1 Accept? A: It is not absolutely necessary to use LCT99 for this. The main advantage is that LCT99 uses its 40MHz clock to generate the 3.2us delay, so LCT99's L1A is far more stable than one from an analog NIM gate generator or similar device. Page 103 of 104 11/01/00 10:05 AM Known Problems 1) 2) 3) 4) 5) 6) 7) 8) 9) Raw hits dump frame count is only 10 bits. 32 tbin dumps take 1546 frames, needing 11 bits Tbin data sets special word bit 14, so can't tell data frame from EOD or Trailer Frame. We will probably change EOD to 7EOD to make it unique Highest 2 FEB id bits in dump (15,14) are ORd into bit 14, so bit 15 remains a DDU special Use FEB=7 for ALCT special words Need to put FPGA version into header frame Need a header-frame separator before the first raw hits frame Need to add CSC size (how may LCT chips) wires to Concentrator Add verbose chip info to JTAG ID registers Frequency of invalid patterns should be readable Revision History 06/29/00 08/01/00 10/04/00 11/01/00 V2.0 V2.0 V2.1 V2.1 JK JK JK JK Adapted from version LCT99 design memo Ready for 1st review LGs typographical corrections, + added -4.3V to ADB power estimate Added N. Bondar's ADB power measurement for 100 boards Page 104 of 104 11/01/00 10:05 AM
