LOW VOLTAGE OPERATION OF A
32-BIT ADDER USING LEVEL
CONVERTERS
Mohammed Ashfaq Shukoor
ECE Department
Auburn University
11/29/2007
ELEC 6270-001 Class Project Presentation
1
Objectives



To reduce the power consumption by
operating the adder at reduced voltage,
coupled with level converters.
To study the effect of Voltage reduction on
the Power consumption and delay of the
adder
To characterize the Level Converters for
power consumption and delay
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Setup for Low Voltage Operation
VDD_L
Low Voltage
outputs
High Voltage
inputs
32-bit Adder
65
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33
Low-to-High
Level
Converter
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High Voltage
Outputs
3
Why Level Converters???
(2)
(1)
VDD_L
( = 2.5 V)
VDD_H
Vout_L
Vout_H
( ‘0’= 0 V)
Vin_H
( = 3.3 V)
(‘1’= 2.5V)
( ‘0’= ???)
Vin_L
( ‘0’= 0 V)
( ‘0’= 0 V)
(‘1’= 3.3V)
(‘1’= 2.5V)
(‘1’= 3.3V)
So……… only a Low-to-High Level
Converter is required!!
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Low-to-High Level Converter
Transistors
with thicker
oxide and
longer channels
VDD_H
p1
p2
Vout_H
Vin_L
n2
n1
VDD_L
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third
Edition, Section 12.4.3, Addison-Wesley, 2005.
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Adder and Level Converter Design


The 32-bit adder was designed using VHDL
Synthesized with 0.35 micron TSMC
technology using Leonardo
- Area = 224 gates


Designed the Level Converters using Design
Architect
Timing and Power analysis was done using
ELDO
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Normal (High) Voltage Operation of the
Adder



VDD = 3.3 V
Power Dissipation = 2.1120 miliwatt
Delay = 0.55882 ns
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Experimental Results
Average Power
VDDL
(in Volts)
Delay
(in
nanosecond)
Adder
(in miliwatts)
Level
Converter
(in microwatts)
32 - Level
Converters
(in miliwatts)
TOTAL
(in miliwatts)
3.0
1.6123
117.7102
3.7709
5.5081
1.51444
2.5
1.0266
126.8847
4.0596
5.2150
1.88333
2.0
0.63547
193.941
6.2515
7.0571
3.77439
1.5
0.35897
148.5038*
4.2706*
4.7805*
-
1.0
0.164371
28.8465*
0.58371*
0.7781*
-
* The power consumption values when the level converter fails
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Delay Break-Up
Delay in ns
VDD in Volts
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Adder
Level Converter
Total
3.3
0.55882
(not used)
-
3.0
0.6197
0.98585
1.60555
2.5
0.77
1.24575
2.01575
2.0
1.01829
2.61889
3.63718
1.5
1.59359
Fails
-
1.0
5.58529
Fails
-
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Power Versus Voltage Plot for the Adder
Power vs. Voltage
Average Power in miliwatts
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
VDD in Volts
Simulation Results
Theoretical Results
P α VDD2
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Delay versus Voltage Plot for the Adder
Delay vs. Voltage
8
7
Delay in ns
6
5
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
VDD in Volts
Simulation Result
Delay 
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Theoretical Result
KVDD
VDD  Vt 
ELEC 6270-001 Low-Power Design of
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
= 1.5
11
Power-Delay Product Plot for the Adder
Power-Delay product
1.4
1.2
1
0.8
power-delay product
0.6
0.4
VDD = 1.5V
0.2
P = 0.359 mW
0
0
0.5
1
1.5
2
2.5
3
3.5
D = 1.59 ns
VDD in volts
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Reason for High Power Consumption in
Level Converter
VDD_H
p1
p2
Vout_H
Vin_L
n2
n1
VDD_L
The p1 – n1 and p2 – n2 transistors stay ON simultaneously for time >= the
inverter delay, thus substantial short circuit power dissipation.
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Alternative Design of a Level Converter
Dynamic CMOS
Inverter
VDD_H
CK
p
Vout_H
Vin_L
CK
n1
n2
High Voltage clock
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Inverter Operating at
the regular supply
voltage (VDD_H)
Phase
CK
Inputs
Output
Precharge
low
don’t care
high
Evaluation
high
Valid inputs
Valid
outputs
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Low Voltage Adder Operation with the Dynamic CMOS
based Low-to-High Level Converter
Average Power
VDDL
(in Volts)
3.0
2.5
Adder
(in miliwatts)
1.55964
1.0401
Delay
(in
nanosecond)
Level
Converter
(in microwatts)
32 - Level
Converters
(in miliwatts)
TOTAL
(in miliwatts)
52.0388
1.8841
3.8387
1.28385
48.1852
1.7400
2.8300
1.35529
2.0
0.69993
45.6025
1.6323
2.5818
2.5818
1.5
0.42559
43.2908
1.5567
2.0288
1.83406
1.4
0.38597
43.0325
1.5783
2.0104
1.9826
1.0
0.27214
47.2037
2.1422
2.4644
5.41575
~ 5% reduction in power consumption
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Problem with this design too!! 
Conventional Level Converter
Dynamic CMOS based
Level Converter
Gives rise to glitches due to the precharge phase of the clock
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Conclusion


The power consumption of the conventional level
converter is too high to be used with the adder for power
reduction. Need a one with lesser power consumption.
The optimum voltage for a low-voltage operation of the
adder was found to be ~ 1.5 V, at which
Power consumption = 0.36 mW (a drop of 83% from 2.112 mW at 3.3V )
Delay = 1.594 ns (three times increase from 0.56 ns at 3.3V)
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Future Work


Investigate the effectiveness of using a level
converter based flip flop [1],[2], in order to
incorporate the level conversion in the
register following the combinational logic.
Use of other low power level converters [1].
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References





Class Lectures
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third
Edition
ELDO User Manual
[1] F. Ishihara, F. Sheikh, B. Nikolic, “Level Conversion
for Dual-Supply Systems,” in IEEE Transactions on VLSI
Systems, Vol. 12, No. 2, Feb. 2004, pp.185–195.
[2] F. Klass, “Semi-Dynamic and Dynamic Flip-Flops with
Embedded Logic,” in Symposium on VLSI Circuits Digest
of Technical Papers, 1998, pp. 108 – 109.
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THANK YOU!!!
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