Preparation for Chip Testing
Chia-Hsiang Yang
Advisor: Prof. Dejan Marković
April 10, 2009
Road to Testing
 After (even before) getting the chip dies, there are lots of
things to do before testing…
Assembly
PCB board
ASIC board
Test Setup
package
chip die
wire-bonding
2
Package Data Sheet
SSM P/N CPG10018
A1
3
Socket/Chip PCB Footprint
 Ceramic PGA
– SSM P/N
CPG10018
(15 × $23.37)
– lead count
(pins): 100
 Test socket
A1 1 2 3 4 5 6 7 8 9 10 11 12 13
A 100 98 97 95 93 90 89 86 83 81 79 77 75
B 2
1 99 96 94 91 87 85 82 80 78 76 73
C 4
3
D 6
5
71 70
E 8
7
69 68
F 11 10 9
G 14 12 13
– 3M ZIF socket H 15 16 17
13×13 matrix
J 18 19
(2×$51.00)
92 88 84
Top view
(as footprint)
67 66 65
63 62 64
59 60 61
57 58
K 20 21
L 22 24
74 72
55 56
34 38 42
53 54
M 23 26 28 30 32 35 37 41 44 46 49 51 52
N 25 27 29 31 33 36 39 40 43 45 47 48 50
4
Bonding Diagram
 Cost $650 for 20
100
95
90
85
80
76
chips
1
75
5
70
10
65
15
60
20
55
25
51
26
30
35
40
45
50
5
PCB Board Layout
7500 mil
3590 mil
420 mil
 Layers: 6
 Material: FR4
 Minimum space: 5 mil
 Minimum hole size: 10 mil
6
Altium Designer
 Installed on dsp server
 Tutorial: Help -> Getting Started -> Getting Started with
PCB Design
PCB Library
Schematic Library
7
Plane Splitting
 Signals are routed on Top layer and Bottom Layer
 Internal planes are usually used for power/gnd
 We can split internal planes into many planes for
different signals
Internal
plane 4
Internal
plane 3
8
FPGA Aided Verification
 IBOB board and BPS design environment
– Test pattern generation and output data capturing through block
RAMs (in place of the pattern generator and logic analyzer)
– Z-DOK+ connectors provide data rate of 500 Mbps
– I/O Interface between client PC and IBOB board in Matlab/Simulink
environment
RS232 interface
(memory access)
RS232
IBOB
board
ZDOK+
ASIC
board
IBOB board
To increase access speed
between User terminal and IBOB
Board, Ethernet interface might
be used in the future
ASIC board
Parallel IV cable
(program)
9
IBOB Board
 FPGA-based processing board
 Xilinx Virtex-II Pro 2VP50 FPGA
 I/O interface
– 2x ZDOK+ 40 differential connectors
– 80x GPIO headers (4 banks) with
selectable IO voltage (1.5/1.8/2.5/3.3)
– 1x MDR 40 differential pair connector
– 2x CX4 10Gbps high-speed serial
connectors
2x ADC boards
– 1x RS232 interface
– 1x 10/100 RJ45 Ethernet interface
– 2x SMA IO
 2x 512k x 36-bit SRAMs
IBOB board
10
I/O Interface Mapping
 GPIO: Note the sequence on the board
BPS library
gpio0
gpio1
gpio2
gpio3
connector
J6
J7
J8
J9
sma, index 0
sma, index1
connector
SMA2
SMA1
J22
GPIO
CX4
BPS library
Z-DOK+ 40
 SMA: Mislabeled on the board
J8
J9
J7
J6
SRAM
SMA2
FPGA
SMA1
BPS library
zdok0
zdok1
connector
J22
J23
CX4
J23
Power
IBOB Board
DC/DC
DC/DC
DC/DC
DC/DC
MDR80
 ZDOK+
Z-DOK+ 40
SRAM
11
ZDOK+ Connector




Tyco Electronics, Adapter P/N: 6367555-3
Free samples provided
40 differential pairs
Data rates up to 6.250 Gb/s (But the FPGA I/O limits data
rate to about 500 Mb/s)
Z1
F20
F1
W1
Z6
W6
A20
A1
12
ZDOK+ Schematic
 40 differential pairs
 4 voltages (1.8V/2.5V/3.3V/5V) and ground
Note: clocks are not
sent through these
pings, so the ping
assignments after
CLK1 in the
datasheet should be
shifted accordingly.
For example, P<19>
and M<19> are
mapped to C19 and
C20, instead of D1
and D2.
13
Interface between ZDOK+ and ASIC
 Driver: SN65LVDS1 (outputs of the chip)


– 630 Mbps
Receiver: SN65LVDS2 (inputs of the chip)
– 400 Mbps
Supply voltage range, VCC: -0.5V to 4V
14
Simulink Test Model
 BPS design environment is installed on sherwin
 Transfer the resulting .bit file to dsp and use iMPACT to
program IBOB board
BPS environment
iMPACT (utility of Xilinx ISE)
15
Clock Source
 Change internal/external clock setting in
 Sine waves can be used for clocks, but you might need
to set the amplitude to be larger
Internal clock: 100MHz
external clock: from SMA2
16
Measurement Results
2.98 mm
PE
5
PE
6
PE
3
PE
4
PE
7
PE
8
0.6
0.48
0.4
0.32
0.2
2.89
(30.1)
register bank / scheduler
( Energy: pJ/bit)
50
100
150
200
250
0
300
Clock frequency (MHz)
PE
9
PE
10
PE
13
PE
14
PE
11
PE
12
PE
15
PE
16
2.98 mm
100
0
0
300
200
Clock frequency (MHz)
47.8 Clock frequency (MHz)
(122.4)
400
Core power (mW)
PE
2
0.75
275
(179)
Vdd (V)
Vdd (V)
Popwer (mW)
Popwer (mW)
PE
1
Minimum VDD (V)
0.8
fclk (MHz)
16
32
64
128
256
VDD (V)
0.321
0.378
0.48
0.6
0.75
Power (mW)
2.89
6.43
47.8
113.3
275
Energy/bit
30.1
33.5
124.4
147.5
179
17
Resources
 http://sherwin.ee.ucla.edu/researchwiki/index.php?title=
CAD_Tutorials
18