Grant Jennings
gtjennings@gmail.com
319-573-5039
Career Experience
Lattice Semiconductor; Hillsboro, OR
Sr. Applications Engineer; Sept, 2011—Present
Project Management:
Small group management on next generation product innovations:
Image processing, video compression
Interface specifications such as USB 2.0/3.0, MIPI M-PHY, VESA DSC, and eDP
Soft IP system requirements for next generation products
Guidance for reference design maintenance and customer procurement
Cross-functional teamwork to revisit performance metrics in legacy devices
Product Marketing:
Instrumental in development of the “Interfacing and Bridging” product line:
SWOT analysis of legacy products such as MachXO2, Lattice XP2 and Lattice ECP3
Assistance in product rebranding strategy through packaging size and cost methods
Development of support strategy for MIPI D-PHY Specification using current and legacy products
Competitive Analysis:
Technical, 4P’s and SWOT assessment for determining whether to productize a silicon shuttle run device
Power, Size, Cost and differentiation value variables assessed against competitors for $50M revenue project
Advertising & Promotion:
Developed user’s guides, web pages, and how-to videos for various products, demos, and reference designs
Multiple worldwide field training sessions and webcasts on MIPI D-PHY, CSI-2 and DSI solutions
Single and dual image sensor technical webcasts
Documents & Publications:
Over 12 publications on latticesemi.com related reference designs and PCB’s
Significant assistance with technical marketing collateral for web splash pages and product flyers
Awards & Recognition:
“RUN Award”
- Companies quarterly recognized employee
Innovator of the year
- Companies most recognized innovation and/or US Patent for the year
U.S. Patent
- Interfacing to MIPI D-PHY with Programmable IOs
Grant Jennings
gtjennings@gmail.com
319-573-5039
Career Experience (Continued)
Technical:
Development of several source synchronous camera and display bridge reference designs
MIPI CSI-2, DSI, and D-PHY Receive and Transmit
SubLVDS to CMOS and MIPI CSI-2 for Panasonic and Sony image sensors,
Aptina HiSPi to CMOS
WDR/HDR for Sony, Panasonic and Aptina image sensors up to 13MP
Interfacing of SERDES based standards such as HDMI/DVI, SDI, eDP, M-PHY and USB 3.0
Design and integration of dual camera IP Camera with TI DM365 and DM8127 processors
Partner development of TI ADC and DAC boards targeting Lattice ECP3
Dual camera integration for gesture recognition with Leap Motion Inc. and Cypress Semiconductor
Sony IMX169 CSI-2 to LG 1080x1920 DSI display with video overlay demo
I2S Master to SPI Slave interface design for TI and Cypress Semiconductor
Ultra low power crystal oscillator feedback circuit connected to MachXO2 FPGA for ADI
Interface PCB designs for Sony, Panasonic and Aptina Image sensors
DSI to DSI with video overlay demo and PCB for Qualcomm Snapdragon S4 development platforms
FPD-Link and MIPI DSI video smart frame buffer development for NVidia
MIPI UFS, Unipro and M-PHY interfacing to Toshiba NAND Flash UFS IC
Image and Display PCBs for MachXO3L and Lattice ECP5 Products
Dual CSI-2 to GPIF for Cypress Semiconductor EZ-USB FX3 IC
Image sensor extender design for car-driver recorder and machine vision applications
Functional characterization of MIPI D-PHY transmit via Agilent U7238A compliance test software
Grant Jennings
gtjennings@gmail.com
319-573-5039
Career Experience (Continued)
Rockwell Collins; Cedar Rapids, IA
Systems Engineer II (Design & Verification); Jan, 2008—Sept, 2011
Embedded SoC Architecture Verification & Integration:
Ported ARM 11 real-time software from a ASIC prototyping platform to a fabricated ASIC
Performed real time ASIC logic verification prior to fabrication
Lead verification of ASIC subsystems post fabrication
FPGA Designs:
ASIC prototyping lead; Prototyped two 20+ million gate ASIC designs on 16 Virtex V FPGAs
GPS IF recorder; Simulink HDL Coder loaded to a Virtex II; 44 Mhz IQ data off of a RAID Drive
Transceiver for communication to DPRAM IC via PCIe IC and a Spartan FPGA
Added instruction/data cache and TCM to ARM subsystem; preformed throughput measurements
ARM 11 Memory Interfacing:
Increased CPU throughput by 75%; synchronous burst memories, clock synchronization, optimization
Assisted with ARM ETM CoreSight features used in systems and software integration
Provided architecture support for AMBA AHB & APB
GPS Systems & Software:
First person to decode Modernized GPS messages with a receiver prototype
First person to acquire and track satellites on Rockwell Collins' newest GPS receiver card
Tracked GPS satellites on an ARM 11 using C code auto-generated from a Simulink model
Developed Boot Software for GPS application in C and Assembly for an ARM1136JFS
Customer Deliveries/Presentations:
Detailed analysis of ASIC power up issues and software/hardware resolutions
Analysis of ASIC power consumption for various navigation products
Proposal of ASIC changes desired for contractual re-spin agreement
CPU and system clock independence while tracking GPS satellites
Awards & Recognitions:
Certificate of Appreciation for ASIC verification, prototyping and integration
Lean 10x Innovation Award Winner 2010
Novascan Technologies; Ames, IA
Design Engineer; Feb, 2007—Dec, 2007
Implemented lock in (QAM) amplification architecture for drive and return signal comparison
Developed Simulink models; used Link for CCS to generate C code for the TI C6713 DSP
Designed a commercial AFM controller PCB; ADC, DAC, DSP and USB interfaces with Orcad
Research and development for a conductive AFM
Emerson Process Management; Eden Prairie, MN
Software Test Engineer; June, 2006 - December, 2006
Tested asset management software on various setups for performance and interoperability
Tested handheld devices for performance and system interoperability
Helped tackle various database, compatibility and support issues with various projects
Grant Jennings
gtjennings@gmail.com
319-573-5039
Education
Texas A&M University Commerce – Commerce, Texas
Graduating June, 2015
Master of Business Administration, Marketing Minor
University Online Program
Iowa State University - Ames, Iowa
Electrical Engineering, Bachelor of Science
Academic Business Research
Management:
Transformational, transactional and laissez-faire leadership styles
Management functions in context to the contingency approach
Motivational development and leadership analysis of aging workforce
Motivational behavior & the McClelland’s Paradigm
Resistance to organizational change
Business Administration:
Investigation of descriptive, historical, correlational, and experimental research methods
Scientific method of research practice and applications to business practices
Earned Value Management System Research Study
Marketing:
Image, brand, and competitive issues of St. Margret’s General Hospital
Market analysis of Sears Holdings Inc.
Source characteristics and executional framework of advertisements
Alternative marketing techniques
Seasonal promotion and advertisement creation
Ice Arena analysis using 4P’s and SWOT
Strategic brand management development process
Product lifestyle concept
Statistics:
Dummy variable method for testing confidence level in equality between two sets of coefficients
Finance & Accounting:
Basic financial statement types and purposes
Direct and Indirect Statement of Cash Flows
Absorption versus variable cost practices
Academic Technical Projects
FPGA Related:
Designed and synthesized single cycle, multi-cycle, and pipelined MIPS processors in Verilog
Took eye diagram and timing measurements on a Cyclone II FPGA; compared results to data sheet
ASIC Related:
Designed the schematic (Verilog), library and layout of an FPGA based off a Xilinx XC4000 series datasheet
Designed an RC transmitter and receiver IC in Verilog using Cadence Tools; Design was fabricated
Performed post layout timing analysis on RC transmitter/receiver before fabrication
Designed a custom multifunction IC under 50 micron in size using Cadence Tools
DSP Related:
Developed a tractor control program in C and assembly for the PowerPC processor
Design and implemented low, high and band pass filters on a TI 5416 DSP using Code Composer Studio
Senior Design Project:
Designed and built a wireless audio barcode scanner for the visually impaired
Grant Jennings
gtjennings@gmail.com
319-573-5039
Specialty Software
FPGA:
ASIC/Hardware:
Simulation:
Software Development:
Source Control:
Certify, Synplify Pro, Identify, Xilinx ISE, ACE by Auspy, Lattice Diamond
Cadence, Orcad10
Matlab & Simulink, Model Sim, Aldec, LabView, Mentor Graphics Hyperlynx
Code Composure Studio, CodeWarrior, Visual Studio, Lauterbach Trace32
Subversion, Clearcase, Clearquest
Test Equipment
High Speed Oscilloscopes, Logic Analyzers, Function Generators, Digital Multimeters, Vector Network Analyzers,
The Dini Group dn8000k10/dn9000k10 Multi-FPGA Platforms, Synopsys HAPS Multi-FPGA Platforms
Contact Information
Address:
Phone:
Email:
Website:
20792 SW Rosemount St. Beaverton, OR 97078
319-573-5039
gtjennings@gmail.com
www.grantjennings.info