intFwctrl
Massachusetts Institute of Technology
Kavli Institute for Astrophysics and Space
Research (MKI)
DHU Firmware Design Specification
Dwg. No. 37-14010
Revision D
Date 10/10/2015
37-14010
Page 1 of 45
Revision D
Table of Contents
1
PREFACE
1.1
1.2
1.3
REVISIONS
REFERENCES
TBD
2
SCOPE
3
DHU FIRMWARE DESIGN
3.1
3.2
3.3
3.3.1
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
4
5
6
6
DESIGN OVERVIEW
FPE DATA DOWNLINK (DDL) AND DECODER
FPE COMMAND UPLINK (CMD)
FRAME START
DDR2 INTERFACE AND XADC
PCI EXPRESS (PCIE) INTERFACE AND CONFIGURATION/STATUS REGISTERS
SCIENCE PROCESSING MODULES (SPM)
GUIDE STARS
SCIENCE STAMPS
ACCUMULATED FULL FRAMES
DIAGNOSTIC FRAMES
INTERFACES
4.1 INTERFACE OVERVIEW
4.1.1 JTAG INTERFACE
4.1.2 OSCILLATOR CLOCKS
4.1.3 SMAP (CONFIGURATION) INTERFACE
4.1.4 FPGA ID
4.1.5 S/C 1PPS
4.1.6 HARD_RSTN
4.1.7 FPE CMD BUS
4.1.8 FPE DATA DOWNLINK (DDL)
4.1.9 DDR2 MEMORY INTERFACE
4.1.10 PCIE INTERFACE
4.2 FPGA I/O
4.3 FPGA POWER
5
5.1
6
7
8
8
8
8
9
9
10
10
10
11
11
11
11
11
11
12
12
12
12
13
13
13
15
MEMORIES
MEMORY MAP
16
SOFTWARE CONFIGURABLE REGISTERS
6.1 REGISTER ADDRESS MAP
6.2 REGISTER DESCRIPTIONS
6.2.1 CAMERA-SPECIFIC GENERAL REGISTERS
6.2.2 CAMERA-SPECIFIC FPE INTERFACE REGISTERS
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17
18
18
25
Revision D
6.2.3
7
POWER UP
HARDWARE RESET
SOFTWARE RESET
FRAME START
33
33
33
33
CLOCKS
8.1
8.2
8.3
8.4
8.5
9
30
RESETS
7.1
7.2
7.3
7.4
8
DATA PROCESSING MODULES CONFIGURATION REGISTERS
DDR2 INTERFACE CLOCK TREE
PCIE INTERFACE CLOCK TREE
FPE INTERFACE CLOCK TREE
INTERNAL LOGIC CLOCK TREE
CLOCK CROSSING BOUNDARIES
35
36
36
36
36
FPGA CONFIGURATION
10 RADIATION MITIGATION
10.1 AUTOMATIC ERROR DETECTION
10.1.1 DATA MEMORIES
10.1.2 CONFIGURATION MEMORY
10.1.3 REGISTERS
10.2 OTHER ERROR DETECTION
10.2.1 OVERVIEW
10.2.2 LOSS OF SYNC/BAD DOWNLINK CONTROL BYTE
10.2.3 MISSING INTERRUPT
37
37
37
38
38
38
38
38
11 CONVENTIONS
12 DESIGN FOR TEST
12.1
12.2
12.3
SIGNAL I/O
MEMORY/REGISTER ACCESSIBILITY
IMAGE GENERATION
39
39
39
13 DESIGN CONFIGURATION ANALYSIS
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.3
13.4
13.4.1
13.4.2
13.4.3
OVERVIEW
MEMORY SIZE REQUIREMENTS
GUIDE STAR
SCIENCE STAMP
ASTEROSEISMOLOGY 10-SECOND INTEGRATION
FULL FRAME
DIAGNOSTIC FRAME
MEMORY MAP EXAMPLE
TIMING DIAGRAMS/INFORMATION
PIXEL BATCH TRANSFER/PROCESSING
DDR2 MEMORY CONTENTION DURING PROCESSING
TRANSFER TO SBC
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39
39
39
39
39
40
40
40
41
41
42
43
Revision D
14 ACRONYMS/ABBREVIATIONS
TABLES
Table 1: Science Processing Module Configuration ................................................................... 9
Table 2: DHU External Interface List ............................................................................................ 14
Table 3: Memory Map ........................................................................................................................ 16
Table 4: Register Address Map ....................................................................................................... 17
Table 5: DHU Clocks ............................................................................................................................ 35
Table 7: Processing cycle time example for science stamps with cosmic ray
mitigation, worse case .............................................................................................................. 42
Table 8: Frame Transfer Values ..................................................................................................... 44
FIGURES
Figure 1: DHU-FPE overview
Figure 2: DHU Firmware Modules
Figure 3: DHU FPGA Interfaces
Figure 4: Example DDR2 Memory Configuration
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7
8
11
41
Revision D
1 Preface
1.1 Revisions
Rev.
01q
Aq
Bq
C
D
37-14010
ECO
37092
37105
37203
37263
37324
Description
New release
Author
KHaworth
Date
7/11/14
Incorporated ECO review comments
KHaworth
9/22/14
Reorganization of document, restructuring of
KHaworth 2/5/2015
command registers.
1. Specified BAR usage in PCIe.
KHaworth 6/15/2015
2. Added FPE_bitfile_size register.
3. Added housekeeping memory (separate
from FPE memory dump).
4. Specified that raw pixels are sign extended.
5. Removed overclock BARS, since all data is
now treated the same.
6. Specification of wait after soft reset.
7. Moved housekeeping memory location from
600 to 700.
8. Changed order of SPM Interrupt register.
9. Added more bits in the STATUS register for
version control.
10. Added specifics of configuration error
mitigation.
11. Changed details on how FPE/DHU sync up
the DDL interface.
1. 6.2.1.1 – added an enable bit to allow the
KHaworth 10/9/2015
DHU to listen for data, even when frames
are not going on the FPE.
2. 6.2.1.2 Fixed the status register to reflect
FPE and DHU versions
3. 6.1 Fixed the memory map to be byte
addressed.
4. 6.2.3.10 – 6.2.3.13 Changed the DDR base
address registers to be byte addressable to
match the PCIe.
5. 6.2.3.2 – Changed the Integration Number
to be “plus 1”.
6. 5.1 Clarification in memory map. PCIe
addresses on byte boundaries. Addresses
changed to reflect this. Also clarified 4kb
boundary restriction for DDR memories.
Page 5 of 45
Revision D
Rev.
ECO
Description
7. 6.2.2 Memory pack reordering.
8. 6.2.2.1 Specified that the address is in bytes
for the FPE_WDATA_BAR, and expanded the
register size to accommodate this.
9. 6.2.2.5 Added HMEM/VMEM to the HMEM
section, and specified the length of each
memory. Also updated the SMEM to be
wider to reflect FPE spec.
10. 6, 6.1 Explain parity check, and designate
which registers have parity checks.
11. Removed sign extending pixels.
12. Added DDL Error, corrected FPE errors.
13. Updated clock tree, resets.
Author
1.2 References
Reference Guide
Xilinx FPGA 7-series Data
Overview
Document
ds180_7Series_Overview.
pdf
FPE Firmware Design
Specification
37-14011-D
Notes
The overview has a link
to all relevant
documentation
1.3 TBD
Open questions. Indicated in the document as TBD.
1 Need the pixel order from the FPE.
2 Add power estimates when available.
3 The design example section needs to be updated when
science ops and commissioning operation has been
resolved.
4 Include test data algorithms. (6.2.1.15)
5 Fourth slice requirement (asteroseismology) still to be
firmed up.
2 Scope
The TESS satellite has one Data Handling Unit (DHU) with two flight programmable
FPGAs (Xilinx Virtex-7 XC7VX330T-2FF1157), each of which will collect and process
image data from two Focal Plane Electronics (FPE) FPGAs. This specification covers
the design and architecture of the Virtex FPGAs.
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Date
The DHU FPGAs interface with a Single Board Computer (SBC). The PCI express
interface is used for fast data transfer. The SBC uses a PCI-104S bus to interface to a
System FPGA, which generates SMAP configuration signals. This is shown in the
following image, with the orange-lined white boxes designating the focus of this
specification.
Figure 1: DHU-FPE overview
3 DHU Firmware Design
3.1 Design Overview
The DHU contains two FPGAs, each responsible for the processing of image data
from two CCD cameras, for a total of four cameras processed.
The DHU FPGA configures and commands the FPE FPGAs, and receives data and
housekeeping from the FPE FPGAs. In addition, data is processed and held in DDR2
memories for transfer to the SBC for further processing.
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The following diagram shows the key modules in the design of one FPGA. Both
FPGAs have the same design. On one FPGA, most of the modules are replicated per
camera; the exceptions are the XADC and the PCIe interface.
Figure 2: DHU Firmware Modules
3.2 FPE Data Downlink (DDL) and Decoder
The decoder converts the serial data from the FPE two downlink signal lines, each of
120 Mbps (DDR), using 480 MHz oversampling on each line. The serial data is
combined and translated into parallel data ready for processing. Details are found in
the Interface section.
3.3 FPE Command Uplink (CMD)
Each DHU FPGA configures and commands two FPE FPGAs through separate serial
synchronous interfaces at 3 MHz. Details are found in the Interface section.
Configuration uploads a bitfile to the FPE FPGA. Command writes to all FPE
memories and registers, and sends a frame start signal.
3.3.1 Frame Start
Each DHU commands two cameras. Each camera processing section of the DHU
independently sends frame start signals to the FPEs. These are based on the 1PPS
signal from the SBC and a programmable value of delay cycles.
3.4 DDR2 Interface and XADC
Data, while being processed, is stored in the 1 GByte DDR2 memories. The interface
contains Xilinx IP and an arbitration unit that arbitrates multiple requests to the
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memory. The XADC, on on-chip ADC module, processes the chip temperature for
DDR2 I/O signal adjustments.
3.5 PCI Express (PCIe) Interface and Configuration/Status Registers
Communication with the SBC is done via a PCI express bus. The PCIe has access to
configuration and status registers as well as the DDR2 memory via direct
addressing. The configuration and status modules keep housekeeping and interrupt
information from both the FPE and the DHU.
3.6 Science Processing Modules (SPM)
The science processing modules are independent, configurable blocks for
processing raw pixel data. This provides flexibility, but care must be taken to ensure
enough bandwidth and memory space exists for the configurations requested. See
the Design Configuration Analysis section for calculations about the current planned
configuration.
The science processing modules are configurable as is shown in the following table.
Table 1: Science Processing Module Configuration
Configuration
Enable On/Off
Bit Mask
Accumulation
Accumulation Interval
Minimum Subtraction
Maximum Subtraction
Min/Max Interval
Base Address Registers
37-14010
Details
This determines whether or not the
science processing module is being used.
This determines whether or not a bit
mask is applied to incoming raw data.
The bit mask, if applicable, is
programmed into the DDR2. Each pixel
will be either processed (corresponding
mask bit = 1) or dropped.
This determines whether or not data will
be accumulated.
This determines for how many frames
data will be accumulated.
This determines if the minimum value
will be subtracted from the total
accumulation.
This determines if the maximum value
will be subtracted from the total
accumulation.
This determines the interval for
subtracting the min and/or max values
from the frames within the interval.
These are the memory locations in the
DDR2 for all applicable memories, which
might include: Bit Mask, Accumulation
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Configuration
Details
Buffers A/B, Minimum, Maximum
The science processing modules can, at minimum, be configured to meet the
requirements for:
 Science Stamp Accumulation
 Full Frame Accumulation
 Guide Star Quaternion Collection
 Image Diagnostics
The following sections describe the science processing module configuration for
these applications. Please see the Registers section for details on how to program
the Science Processing Modules.
3.6.1 Guide Stars
Guide stars are collected at each frame for each camera. There are typically 200
“stamps” from each camera selected at approximately 225 pixels per stamp. A bit
mask is used to select these stamps. Each pixel is represented by one bit. If asserted,
the pixel will be included as a guide star; else it will be discarded. This allows
stamps of any size or shape.
Because the bit masks are held in DDR2 memory, and are used as control, the
asserted bits will be counted as they are received. An interrupt to the SBC is
asserted if the value of this count does not match a register value.
3.6.1.1 Pixel Locations
TBD: Draw layout of pixel to memory location for each CCD.
3.6.2 Science Stamps
Science stamps are collected at each frame and accumulated over a two-minute
interval. There are 32 bits allotted for accumulation. If cosmic ray mitigation is
required, the min and/or max can be subtracted from a set of data.
There are a maximum of 5000 “stamps” from each camera selected at approximately
100 pixels per stamp. These stamps are located by a bit mask. Each pixel has one bit.
If asserted, the pixel will be included as a science stamp; else it will be discarded.
This allows stamps of any size or shape.
3.6.3 Accumulated Full Frames
Full frames with overhead are accumulated over thirty minute intervals.
If cosmic ray mitigation is required, the min and/or max can be subtracted from a
set of data.
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3.6.4 Diagnostic Frames
This memory is a full frame. This data is collected at the first frame after reset, and
at subsequent intervals. After a frame of data is collected, the SBC will be notified.
Two diagnostic frames are held in memory per camera. Raw pixels, which are 16
bits, are backfilled with 0’s to 32 bits before being written into DDR2 memory.
4 Interfaces
4.1 Interface Overview
Figure 3: DHU FPGA Interfaces
4.1.1 JTAG Interface
The JTAG interface can be used for programming the FPGA in the lab.
4.1.2 Oscillator Clocks
Four oscillator clocks on the board will be routed to each FPGA: 125 MHz, 100 MHz,
60 MHz, and 200 MHz. See section 8 for additional details of clock use.
4.1.3 SMAP (Configuration) Interface
The SBC will load the bitfile into each FPGA. This is accomplished via a PCI interface
on the SBC. This interface is passed through bridge logic on a Microsemi FPGA
programmed by Space Micro, Inc., which resides on the FPGA board, and will
translate to the Slave 32-bit SMAP interface.
4.1.4 FPGA ID
A single pin designates the difference between the two FPGAs. One FPGA must have
the pin pulled up; the other must have it pulled down. Cameras 1 and 2 will have the
pin pulled up; cameras 3 and 4 will have the pin pulled down.
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4.1.5 S/C 1PPS
The 1PPS signal is routed from the SBC through the IPC Microsemi FPGA, and to
each of the DHU FPGAs.
4.1.6 Hard_Rstn
Two active-low, asynchronous hard_rstn signals are driven from the SBC through
the IPC Microsemi FPGA. Each DHU FPGA receives a separate hard_rstn.
4.1.7 FPE CMD Bus
Each DHU FPGA has two serial synchronous command interfaces to its two FPEs,
each with a 3 MHz clock and separate serial data line.
The command interface packets, sent over an RS-422 Serial Synchronous interface,
are described in the FPE Firmware Design document, 37-14011.
4.1.8 FPE Data Downlink (DDL)
4.1.8.1 Overview
Raw full frame signed images are downloaded to the DHU FPGA over the Data
Downlink Interface. The Data Downlink Interface, per camera, consists of two lines.
Each line is transmitted at 60 MHz, with data on both clock edges, resulting in 120
Mbps data transfer.
The input runs at 480 MHz, creating a 4X oversampling rate for data recovery. A
start and stop bit delineates each 8-bit data byte.
Data, housekeeping, and FPE register status will be sent via this interface.
The image data packets and housekeeping packets, sent over the DDL interface, are
fully described in the FPE Firmware Design document, 37-14011.
4.1.8.2 Synchronization
A start bit with a control byte will indicate the start of a new transfer to the DHU.
An error on the DDL interface can be detected in one of the following ways:
1. Unknown control byte value.
2. The 1PPS signal is converted to a Start Of Frame command sent to the FPE. In
processing the frame, the FPE will start with a start-of-frame control symbol,
and end with an end-of-frame control symbol. An error is detected if:
a. The Start of Frame command is sent to the FPE, and the next control
value received over the DDL is not start of frame.
b. The Start of Frame command is sent to the FPE, but there was no
previous control value over the DDL designating end of frame.
c. Two Start of Frame commands are sent, but no start-of-frame control
symbol is received.
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If any of these occur, the SBC will be interrupted. The FPGA will continue to process
packets as they are received until the SBC takes action, either by performing a
software reset of the camera logic that has the error, or toggling the hard reset
signal to reset the entire FPGA.
4.1.9 DDR2 Memory Interface
Per FPGA, two 64-bit DDR2 controllers access 512 MB SDRAM each. The interface is
provided as IP by Xilinx for the Virtex 7, and is described in the document
ds176_7Series_MIS.pdf.
The DDR2 components used are 4Gbit - 64Mb x 72. The maximum clock frequency is
333 MHz. Because the Xilinx doesn’t have EDAC in its controllers, the bus width used
will be 64 bits. The clock frequency used will be 250 MHz, or 500 Mbps. This results
in an effective speed of 64*250 = 32 Gbps.
The Xilinx controller is programmed to interface to memory type MT47H64M16XX25. It will automatically adjust to this device’s requested refresh rate.
The Xilinx controller does not allow for EDAC on the memories. Since most of the
data is transient, this will not adversely affect the system. However, the bit masks
residing in the DDR memories will need to be checked each time they are used. This
is done by a counter that keeps track of the asserted bits in the mask, then compares
them to a known value. If there is a discrepancy, the SBC is interrupted.
The Xilinx controller responds to resets as follows: After deassertion of system
reset, the PHY performs the required power-on initialization sequence for the
memory. This is followed by several stages of timing calibration for both the write
and read datapaths.
The XADC is instantiated to monitor and supply the temperature to both DDR2
controllers, so that they can “maintain DQS center alignment in the data valid
window by compensating for temperature drift.” The XADC must be configured for
continuous looping on the XADC and calibration temperature, both set with
averaging to 16, so that the temperature is updated every 116 microseconds. In
addition, the Xilinx module ddr_phy_tempmon must be instantiated so that the
temperature is sampled whenever a REF (refresh) or ZQ (calibration) command has
been sent to the controller, and all pending transactions have been cleared.
4.1.10 PCIe Interface
The PCIe interface is used for commands and telemetry between the each FPGA and
the SBC. It is also used for fast data transfer from the FPGA DDR2 memories into the
SBC DDR2 memories. The SBC acts as a master, initiating all transfers.
4.2 FPGA I/O
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Table 2: DHU External Interface List
Port Name
I/
O
Description
System Signals
Hard_Rstn
OscClk60
I
I
LVCMOS18
LVCMOS18
OscClk125_p/n
I
OscClk100_p/n
I
Cam1_SysDDR_p/n
I
Cam1_RefDDR_p/n
I
Cam2_SysDDR_p/n
I
Cam2_RefDDR_p/n
I
SC_1PPS
FPGA_ID
I
I
Active low Reset from SBC
60 MHz Oscillator Clock
Input
125 MHz Oscillator Clock
Input
100 MHz Oscillator Clock
Input
125 MHz Oscillator Clock
Input, DDR Controller 1
200 MHz Oscillator Clock
Input
125 MHz Oscillator Clock
Input, DDR controller 2
200 MHz Oscillator Clock
Input
1PPS from spacecraft
Identification for FPGA (0 or
1, depending on FPGA)
I
LVDS Data Downlink A
LVDS
I
LVDS Data Downlink B
LVDS
O
I
RS-422 serial synchronous
clock
RS-422 serial synchronous
data
LVDS Data Downlink A
I
LVDS Data Downlink B
Camera Interface
FPE_cam1_DDLA_p
/n
FPE_cam1_DDLB_p
/n
FPE_Cam1_CmdClk
FPE_Cam1_CmdDat
a
FPE_cam2_DDLA_p
/n
FPE_cam2_DDLA_p
/n
FPE_Cam2_CmdClk
O
RS-422 serial synchronous
clock
FPE_Cam2_CmdDat O RS-422 serial synchronous
a
data
DDR2 controllers (1 and 2)
ddr2_cam1_addr[1 O All DDR signals are fast slew
3]
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O
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Drive
Str
mA
PULLUP TYPE
/DOWN/
NONE
LVDS
LVDS
DIFF_SSTL
18_II
DIFF_SSTL
18_II
DIFF_SSTL
18_II
DIFF_SSTL
18_II
LVCMOS18
LVCMOS18
8
LVCMOS18
8
LVCMOS18
LVDS
LVDS
8
LVCMOS18
8
LVCMOS18
SSTL18_II
Revision D
Port Name
I/
O
ddr2_ cam1_ba[3]
ddr2_ cam1_cas_n
ddr2_ cam1_ck_p/n
O
O
O
ddr2_ cam1_cke
ddr2_ cam1_cs_n
ddr2_ cam1_odt
ddr2_ cam1_ras_n
ddr2_ cam1_we_n
ddr2_ cam1_dq[64]
O
O
O
O
O
I/
O
I/
O
O
ddr2_
cam1_dqs_p/n[8]
ddr2_
cam2_addr[13]
ddr2_ cam2_ba[3]
ddr2_ cam2_cas_n
ddr2_ cam2_ck_p/n
ddr2_ cam2_cke
ddr2_ cam2_cs_n
ddr2_ cam2_odt
ddr2_ cam2_ras_n
ddr2_ cam2_we_n
ddr2_ cam2_dq[64]
ddr2_
cam2_dqs_p/n[8]
PCIe
pcie_exp_txp/n
pcie_exp_rxp/n
debug[16]
Description
Drive
Str
mA
O
O
O
SSTL18_II
SSTL18_II
DIFF_SSTL
18_II
SSTL18_II
SSTL18_II
SSTL18_II
SSTL18_II
SSTL18_II
SSTL18_II_
T_DCI
DIFF_SSTL
18_II_T_DCI
O
O
O
O
O
I/
O
I/
O
I
O
O
PULLUP TYPE
/DOWN/
NONE
SSTL18_II
SSTL18_II
DIFF_SSTL
18_II
SSTL18_II
SSTL18_II
SSTL18_II
SSTL18_II
SSTL18_II
SSTL18_II_
T_DCI
DIFF_SSTL
18_II_T_DCI
SSTL18_II
Signals for lab testing
12
12
(MGT)
(MGT)
8
LVCMOS18
4.3 FPGA Power
TBD: Insert a table showing the voltage for each FPGA voltage rail.
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5 Memories
On each Virtex 7-VX330T, there is 17000 Kb configurable block RAM, yielding 27 Mb
of on-chip memory.
In addition, there is 1GB of off-chip memory accessible by two DDR2 memory
interfaces for each FPGA.
5.1
Memory Map
A 32-bit address bus and a BAR ID is translated by the PCIe interface. Because PCIe
is delivered in 256-byte packets, it is expected that when writing to memory, the
entire packet is filled. If there is not enough data, the unused part of the packet must
be filled with zeros.
The memory map is as follows:
Table 3: Memory Map
Registers Camera 1
DDR2 Memory
Camera 1
Registers Camera 2
DDR2 Memory
Camera 2
BAR ID
0
0
Byte Start Address
0x00000000
0x20000000
Byte End Address
0x00003FFC
0x2FFFFFE0
1
1
0x00000000
0x20000000
0x00003FFC
0x2FFFFFE0
The base addresses for the individual Science Processing Module (SPM) data is fully
programmable, but must be on 64-byte boundaries. An example of a configuration is
included in the Design Configuration Examples/Memory section of this document.
There is 1 GByte (30 address bits) of space per PCIe BAR.
The DDR2 memory for one camera is 512 MByte of space, requiring 29 address bits,
but is accessible in 32 byte words. This means that the DDR space is addressed by
bits 28:5. For example, the first three addresses are 0x00000000, 0x00000020,
0x00000040.
6 Software Configurable Registers
The registers are physically in the FPGA, and externally accessible via the PCIe. Each
register is aligned to a 4-byte boundary. No sub-word access is allowed.
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In addition, crossing register boundaries in a packet write or read is not allowed.
Therefore, registers must be accessed, with a separate packet for general-purpose
registers, and each of the Science Processing Modules (SPMs).
Register space is accessible in 32-bit words. The first three addresses are
0x00000000, 0x00000004, 0x00000008.
Parity is generated for writeable registers that hold their values for multiple frames.
This is generated by firmware logic when written, then checked at the start of each
frame. An interrupt is issued if parity in any register is found to be incorrect. The
Register Address Map table designates which registers have parity checks.
6.1 Register Address Map
Table 4: Register Address Map
Address
Name
Offset
For simplicity, only camera 1 registers are listed here.
0x0000
CAM1_CONTROL
0x0004
CAM1_STATUS
0x0008
CAM1_INTERRUPT
0x000C
CAM1_INTERRUPT_ENA
0x0010
CAM1_INTERRUPT_FORCE
0x0014
CAM1_INTERRUPT_SPM
0x0018
CAM1_INTERRUPT_SPM_ENA
0x001C
CAM1_INTERRUPT_SPM_FORCE
0x0020
CAM1_PPS_DELAY
0x0024
CAM1_FRAME_COUNT
0x0028
Reserved
0x002C
CAM1_PIXELS
0x0030
Reserved
0x0034
CAM1_NUM_BAD_PKTS_A
0x0038
CAM1_NUM_BAD_PKTS_B
0x003C
CAM1_TEST_DATA
0x0040
CAM1_FPE_WDATA_BAR
0x0044
CAM1_FPE_WCTRL
0x0048
CAM1_FPE_RCTRL
0x004C
CAM1_FPE_BITFILE_SIZE
0x0050
CAM1_FPE_REPROGRAM
0x005C –
Reserved
0x03FC
The registers below are repeated per SPM. The Data
Processing Modules perform the processing (Science
37-14010
Page 17 of 45
Parity?
Y
N
N
Y
N
N
Y
N
Y
N
N
N
N
N
N
N
Y
N
N
Y
N
Revision D
Address
Name
Offset
Stamp, FFI, etc). These are programmable for
maximum flexibility. There are five of them, starting
at : 0x0400, 0x0800, 0x0C00, 0x1000, and 0x1400.
0x0400
CAM1_SPMx_CTRL
0x0404
CAM1_SPMx_CURRENT_INT
0x0408
CAM1_SPMx_FRAME_START
0x040C
CAM1_SPMx_FRAME_END
0x0410
CAM1_SPMx_BM_NUM_PXLS
0x0414
CAM1_SPMx_INT_NUM
0x0418
CAM1_SPMx_CHUNK_NUM
0x041C
CAM1_SPMx_PAUSE_NUM
0x0420
Unused
0x0424
CAM1_SPMx_BM_BAR
0x0428
CAM1_SPMx_MIN_BAR
0x042C
CAM1_SPMx_MAX_BAR
0x0430
CAM1_SPMx_BAR_DATA_BUFA
0x0434
CAM1_SPMx_BAR_DATA_BUFB
0x1C00CAM1_FPE_HSK[0 to 127]
0x1DFC
0x1E00 –
Reserved
0x1FFC
0x2000 –
CAM1_FPE_MEM_DUMP [0 to 2047]
0x3FFC
Parity?
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
6.2 Register Descriptions
6.2.1 Camera-Specific General Registers
6.2.1.1 CAMn_CONTROL
The reset is not required unless there is a problem with one of the cameras. If the
reset is triggered, a 1 microsecond wait must follow before any further commands
can be issued.
This controls reset of this camera, as well as sending frame starts to the FPE and
listening to the data downlink. The enable is intended to work as follows:
 DHU bit file is loaded
 DHU registers are configured (with ENABLE of CAMn_CONTROL set to 0)
 FPE bit file is loaded
 FPE memories and registers are configured
 ENABLE of CAMn_CONTROL is set before the next applicable 1PPS signal
arrives.
37-14010
Page 18 of 45
Revision D
The ENABLE_DDL signal of the CAMn_CONTROL register is for when it is necessary
to receive housekeeping or memory data on the data downlink, but it is not desired
to receive or process frames. This is for debug purposes.
Bit Field
ENABLE_DDL
Bit # Access
2
RW
Reset
0
ENABLE_ALL
1
RW
0
RESET_ALL
0
WO
0
Description
When 1, enables the
logic to listen for
downlink camera N data
without sending frame
start signals. This is for
debug purposes to
receive housekeeping
and memory data only.
When 1, enables the
logic to listen for
Downlink Camera N
data, as well as enables
the logic to send frame
start signals to the
camera. When 0, the
data on the downlink is
ignored, and no frame
start signals are sent.
This is for normal
operation.
When 1, resets only this
DHU Camera logic. All
state machines and
address pointers return
to 0, and the DHU
Camera logic is disabled.
Note that no further
commands can be issued
for 1 microsecond, while
all clock regions reset.
6.2.1.2 CAMn_STATUS
This status register is for debug purposes, and for identifying the FPGA.
Bit Field
DDR_CALIB_COMP
Bit #
23
Access
RO
Reset
0
PCIE_LINKUP
22
RO
0
37-14010
Page 19 of 45
Description
The DDR memory has
finished initial calibration
The PCIe link is up.
Revision D
Bit Field
PCIE_APP_RDY
Bit #
21
Access
RO
IN_SYNCA
20
RO
IN_SYNCB
19
RO
TEST_MODE
FPE_FW_VERSION
18:17 RO
16:14 RO
FPE_CAM_ID
13:9
RO
FPGA_ID
8
RO
DHU_FW_VERSION 7:0
RO
Reset
0
Description
The PCIe is ready for data
transfers.
0
When 1, indicates that the
DDL interface has started
receiving data from the FPE
for line A. When 0, indicates
no data has been received.
0
When 1, indicates that the
DDL interface has started
receiving data from the FPE
for line B. When 0, indicates
no data has been received.
0
The current test mode.
Depends This is the version of the FW
on
in the FPE FPGA.
version
0
The camera ID. This is
reported as part of the
status, which is sent every
time a pixel packet is sent.
0/1
This is the value of a
strapped pin, indicating
which FPGA this is. This will
be identical for both
cameras.
Depends This is the version of the FW
on
in the DHU FPGA.
version
6.2.1.3 CAMn_INTERRUPT
If the corresponding enable bit in the CAMn_INTERRUPT_ENA register is set, an
assertion will cause a PCIe interrupt to the SBC. The SBC must write a ‘1’ to the bit
that caused the interrupt to clear the interrupt. If more than one bit is asserted, the
interrupt will persist until all bits are cleared.
Note that all FPE interrupts will persist until the error is fixed. Therefore, this
register can be cleared, but at the next transfer, if the problem is not solved, the
interrupt will reassert.
An SBC interrupt can come either from CAMn_INTERRUPT register or
CAMn_INTERRUPT_SPM register. Therefore, it is necessary to read both registers in
order to determine the interrupt source.
37-14010
Page 20 of 45
Revision D
Bit Field
DDL_SEQERR
Bit #
14
Access Reset
W1C
0
FPE_CFG_CRC_ERR
13
W1C
0
FPE_CFG_ECC_ERR
12
W1C
0
FPE_REG_ERR
11
W1C
0
FPE_HSK_ERR
10
W1C
0
FPE_PRG_ERR
9
W1C
0
FPE_SEQ_ERR
8
W1C
0
FPE_CMD_ REJECT
7
W1C
0
FPE_CMD_ INVALID
6
W1C
0
DDL_BAD_PKTB
5
W1C
0
37-14010
Description
The DDL has detected a
sequence other than PPS
Frame Start -> DDL Start of
Frame -> DDL End of Frame
-> PPS Frame Start. The
interrupt will stay asserted
until a correct sequence is
received.
The FPE configuration
memory has reported a CRC
mismatch. This means that
more than one error has
been detected in a frame.
This is unfixable, and the
configuration must be
reloaded.
The FPE configuration
memory has reported a
single or double bit error.
This will be automatically
cleared if fixed. If unable to
fix, FPE_CFG_CRC_ERR will
be asserted.
One of the registers has a
parity error.
The housekeeping memory
has an uncorrectable ECC
error.
The program memory has
an uncorrectable ECC error.
The sequence memory has
an uncorrectable ECC error.
An attempt to write/read
FPE memory while the FPE
is running frames has been
made.
A command has been
detected on the FPE, but it
does not decode to a known
operation.
An unknown packet has
been received on DDL B
Page 21 of 45
Revision D
Bit Field
DDL_BAD_PKTA
Bit #
4
Access Reset
W1C
0
DUMP_DATA
3
W1C
0
FPE_HK
2
W1C
0
FPE_LOADED
1
W1C
0
REG_ERROR
0
W1C
0
Description
An unknown packet has
been received on DDL A
Indication that requested
FPE memory dump is ready
to read from
CAMn_FPE_MEM_DUMP.
Indication that FPE
housekeeping/status
information is available to
read from CAMn_FPE_HSK.
The data in the
CAMn_FPE_WDATA memory
has been loaded onto the
FPE.
A parity error in a
configuration register (not
SPM) has been detected.
6.2.1.4 CAMn_INTERRUPT _SPM
If the corresponding mask bit in the CAMn_INTERRUPT_MASK_SPM register is set,
an assertion will cause a level interrupt to the SBC. The SBC must write a ‘1’ to the
bit that caused the interrupt to clear the interrupt. If more than one bit is asserted,
the interrupt will persist until all bits are cleared.
Bit Field
SPM4_BM_ERR
Bit #
20
Access Reset
W1C
0
SPM4_REG_ERR
18
W1C
0
SPM4_BUFB_RDY
17
W1C
0
SPM4_BUFA_RDY
16
W1C
0
SPM3_BM_ERR
15
W1C
0
SPM3_REG_ERR
14
W1C
0
SPM3_BUFB_RDY
13
W1C
0
SPM3_BUFA_RDY
12
W1C
0
37-14010
Description
Indication that SPM4 has
detected a bit mask error.
Indication that SPM4 has
detected a parity error in a
configuration register.
Buffer B of SPM 4 data is
ready for transfer
Buffer A of SPM 4 data is
ready for transfer
Indication that SPM3 has
detected a bit mask error.
Indication that SPM3 has
detected a parity error in a
configuration register.
Buffer B of SPM 3 data is
ready for transfer
Buffer A of SPM 3 data is
ready for transfer
Page 22 of 45
Revision D
Bit Field
SPM2_BM_ERR
Bit #
11
Access Reset
W1C
0
SPM2_REG_ERR
10
W1C
0
SPM2_BUFB_RDY
9
W1C
0
SPM2_BUFA_RDY
8
W1C
0
SPM1_BM_ERR
7
W1C
0
SPM1_REG_ERR
6
W1C
0
SPM1_BUFB_RDY
5
W1C
0
SPM1_BUFA_RDY
4
W1C
0
SPM0_BM_ERR
3
W1C
0
SPM0_REG_ERR
2
W1C
0
SPM0_BUFB_RDY
1
W1C
0
SPM0_BUFA_RDY
0
W1C
0
Description
Indication that SPM2 has
detected a bit mask error.
Indication that SPM2 has
detected a parity error in a
configuration register.
Buffer B of SPM 2 data is
ready for transfer
Buffer A of SPM 2 data is
ready for transfer
Indication that SPM1 has
detected a bit mask error.
Indication that SPM1 has
detected a parity error in a
configuration register.
Buffer B of SPM 1 data is
ready for transfer
Buffer A of SPM 1 data is
ready for transfer
Indication that SPM0 has
detected a bit mask error.
Indication that SPM0 has
detected a parity error in a
configuration register.
Buffer B of SPM 0 data is
ready for transfer
Buffer A of SPM 0 data is
ready for transfer
6.2.1.5 CAMn_INTERRUPT_FORCE
This register is for test purposes only, in order to easy generate an interrupt to test
system response. When values in this register are set to ‘1’, the corresponding bit
will trigger an interrupt to software. When set to ‘0’, it will not trigger an interrupt.
The force bit locations correspond to the CAMn_INTERRUPT bit locations. A W1C to
the interrupt registers will clear both the CAMn_INTERRUPT_FORCE register and
the CAMn_INTERRUPT register.
6.2.1.6 CAMn_INTERRUPT_ENA
When values in this register are set to ‘1’, the corresponding bit assertion in the
CAMn_INTERRUPT register will trigger an interrupt to software. When set to ‘0’, it
will not trigger an interrupt. The enable bit locations correspond to the
CAMn_INTERRUPT bit locations.
37-14010
Page 23 of 45
Revision D
6.2.1.7 CAMn_INTERRUPT_SPM_ENA
When values in this register are set to ‘1’, the corresponding bit assertion in the
CAMn_INTERRUPT_SPM register will trigger an interrupt to software. When set to
‘0’, it will not trigger an interrupt. The enable bit locations correspond to the
CAMn_INTERRUPT_SPM bit locations.
6.2.1.8 CAMn_INTERRUPT_SPM_FORCE
This register is for test purposes only, in order to easy generate an interrupt to test
system response. When values in this register are set to ‘1’, the corresponding bit
will trigger an interrupt to software. When set to ‘0’, it will not trigger an interrupt.
The force bit locations correspond to the CAMn_INTERRUPT_SPM bit locations. A
W1C to the interrupt registers will clear both the CAMn_INTERRUPT_SPM_FORCE
register and the CAMn_INTERRUPT_SPM register.
6.2.1.9 CAMn_PPS_DELAY
The register is the delay from the 1PPS signal to the command to the FPE to start a
frame. This is counted in 125 MHz clock cycles.
Bit Field
DELAY
Bit#
31:0
Access
RW
Reset
0
Description
The number of 125 MHz
clocks to delay before sending
the 1PPS signal as an
indication to start frame
processing.
6.2.1.10 CAMn_FRAME_COUNT
Counts the number of frames. Starts on the first frame received from the FPE. Rolls
over at maximum.
Bit Field
CNT
Bit#
31:0
Access
RO
Reset
0
Description
Frame Counter.
6.2.1.11 CAMn_PIXELS
The number of pixels processed for the current frame. This is counted as pixels
come in. This resets at the beginning of the following frame.
Bit Field
NUM_PIXELS
Bit#
31:0
Access
RO
Reset
0
Description
Number of pixels processed
6.2.1.12 CAMn_NUM_BAD_PKT_A/B
The number of bad packets received on line A/line B. For debug purposes.
Bit Field
37-14010
Bit#
Access
Reset
Description
Page 24 of 45
Revision D
NUM_BAD_PKT 31:0
RO
0
Number of bad packets
received on line A/B.
6.2.1.13 CAMn_TEST_DATA
This register determines the algorithm used to produce test data (Algorithms TBD).
Bit Field
TEST_DATA
Bit#
1:0
Access
RW
Reset
0
Description
00 = Regular operation
01 = Algorithm 1
10 = Algorithm 2
11 = Algorithm 3
6.2.2 Camera-Specific FPE Interface Registers
These registers allow software programmable access to the FPE FPGAs. Examples
for loading are as follows:
Loading the FPE Bitfile
1. Load the DDR2 memory with the entire contents of the bitfile.
2. Write the CAMn_FPE_BITFILE_SIZE register with the number of 32-bit words
contained in the bitfile.
3. Write the CAMn_FPE_WDATA_BAR with the base address of where the bitfile
is located in the DDR.
4. Write xE0001 to the CAMn_FPE_WCTRL register. This will start the bitfile
load.
5. When the data transfer is complete, the FPE_LOADED bit will be asserted in
the CAMn_INTERRUPT register.
Loading the FPE Memories
Loading the memories is similar to the bitfile, but they must be packed in the DDR as
shown in the following table. This demonstrates all memories written at once, but
memories can also be written individually, using the same packing structure for the
memory chosen.
FPE Mem
Type
PRG_MEM
Size
SEQ_MEM
1024x33
37-14010
512x64
Translate to FPE WDATA
address
Write CAMn_FPE_WDATA address
0 to 1024. Pack as follows:
Address 0 = PRG_MEM(0)(63:32)
Address 1 = PRG_MEM(0)(31:0)
Write CAMn_FPE_WDATA address
0 to 2047. Pack as follows:
Address 0 = SEQ_MEM(0)(35:32)
Address 1 = SEQ_MEM(0)(31:0)
Etc.
Page 25 of 45
Description of
FPE Memory
Program
Memory
Sequencer
Memory
Revision D
HSK_MEM
512x8
VOLT_MEM
128x16
Write CAMn_FPE_WDATA address
0 to 127. Pack as follows:
Address 0(31:24) = HSK_MEM(0)
Address 0(23:16) = HSK_MEM(1)
Address 0(15:6) = HSK_MEM(2)
Address 0(7:0) = HSK_MEM(3)
Address 1(31:24) = HSK_MEM(4)
Etc.
Write CAMn_FPE_WDATA address
0 to 63. Pack as follows:
Address 0(31:16) = VOLT_MEM(0)
Address 0(15:0) = VOLT_MEM(1)
Address 1(31:16) = VOLT_MEM(2)
Etc.
Housekeeping
Select Memory
Voltage Levels
Control Memory
Loading the FPE Registers.
Registers are packed in the DDR memory as shown in the table below. Unlike
memory, not all registers must be written at once.
Registers
16x32
Write CAMn_FPE_WDATA address Control and
0 to REG_NUM.
Status Registers
6.2.2.1 CAMn_FPE_WDATA_BAR
The starting address where the write data exists in DDR memory.
Bit Field
BASE ADDRESS
Bit#
28:0
Access Reset
RW
0
Description
The location of the FPE write
data in DDR memory in bytes.
6.2.2.2 CAMn_FPE_WCTRL
Enables the write transfer to the FPE. Note that any load of the memory must occur
before any frame start signals are sent, or they will be ignored. The exception to this
is WRITE_TYPE to Load the Bitfile or Reset the FPE.
Bit Field
WRITE TYPE
37-14010
Bit#
Access Reset
19:17 RW
0
Description
000 = PMEM Load the
program memory.
001 = SMEM Load the
sequencer memory.
010 = HMEM Load the
housekeeping memory.
011 = VMEM Load the clock
voltages memory.
Page 26 of 45
Revision D
100 = Load the registers.
101 = Reset the FPE
110 = Unused
111 = Load the bitfile
Note that for PMEM, SMEM,
VMEM and HMEM, it is
required that the entire
memory be written. See
section below for how to pack
the data.
Registers may be written
individually or consecutively,
depending on REG_ADDR and
REG_NUM fields.
NUM
16:5
RW
0
REG_ADDR
4:1
RW
0
N/A
0
R0
0
How many consecutive 32-bit
values are to be written. If
registers, a value of 0 means
this command will be ignored.
If memory, a value of 0 means
the entire memory is written.
Note that any writes to readonly values will be ignored in
the FPE.
Start address of register write.
Note that memories always
start at their base, so this field
is ignored if not a register
write.
Unused
6.2.2.3 CAMn_FPE_READ_CTRL
Bit Field
DUMP_MEM
Bit#
2:1
DUMP_MEM_IMM 0
37-14010
Access
RW
Reset
0
RW
0
Page 27 of 45
Description
00: HSK
01: PMEM
10: SMEM
11: HMEM /VMEM
0 = Dump at end of
frame
Revision D
1 = Dump
immediately
6.2.2.4 CAM1_FPE_BITFILE_SIZE
This register holds the data, in 32-bit words, of the FPE bitfile. This is so the FPE
Command interface knows how many words to transmit to configure the FPE.
Bit Field
Bit#
Access Reset
Description
Bitfile_Size
31:0
RW
0
Number of configuration
words to send to the FPE.
6.2.2.5 CAMn_FPE_REPROGRAM
This register will cause the FPE_CAMn_CmdClk signal to be held high for 100 ms.
Upon receiving this signal, circuitry on the FPE board toggles the PROGRAM_B signal
to the FPGA, which will reset the FPGA configuration for reprogramming. This
register is self-clearing.
Bit Field
Bit#
Access Reset
Description
REPROG
0
WO
0
If set to 1, causes the FPE
FPGA to be put into a
configuration reset state,
awaiting a new bitfile load.
This bit is self-clearing.
Setting to 0 has no effect.
6.2.2.6 CAMn_FPE_MEMORY_DUMP [0 to 2047]
This data buffer holds the dumped data from the FPE.
Bit Field
Data
Bit#
31:0
Access
RW
Reset
0
Description
Only one memory can be read per frame, in addition to housekeeping data. The
protocol is as follows:
1. Write to the CAMn_FPE_RCTRL register. The transfer will start, either
immediately or on the next Frame Start signal. The number of values that will
be read from the FPE depend on the memory size or the number of
housekeeping samples selected per frame (an FPE register selection). Only
one memory, or housekeeping samples, can be read per frame or per
immediate request. In typical operation, only the housekeeping is read.
Register status from the FPE is automatically dumped with housekeeping
data.
2. The data will be transferred from the FPE, and collected by the DHU, either at
the end of the frame, or immediately, if IMM is selected.
FPE Dump
Type
SMEM
37-14010
Size
1024x36
Translate to FPE WDATA
address
Address 0 = SEQ_MEM(0)(35:32)
Page 28 of 45
Description of
FPE Memory
Sequencer
Revision D
Address 1 = SEQ_MEM(0)(31:0)
Etc.
PMEM
512x64
HMEM/VMEM 512x8
Memory. There
are a total of 2048
32-bit words.
Address 0 = PRG_MEM(0)(63:32) Program Memory.
Address 1 = PRG_MEM(0)(31:0)
There are a total
of 1024 32-bit
words.
Address 0(31:24) = HSK_MEM(0) Housekeeping
Address 0(23:16) = HSK_MEM(1) Select and Clock
Address 0(15:8) = HSK_MEM(2)
Level Voltage
Address 0(7:0) = HSK_MEM(3)
Memories. There
Address 1(31:24) = HSK_MEM(4) are a total of 192
…
32-bit words (128
Address128(31:16) = CLV_MEM(0) from HSK and 64
Address128(15:0) = CLV_MEM(1) from CLV)
Address129(31:16 = CLV_MEM(2)
…
6.2.2.7 CAMn_FPE_HOUSEKEEPING [0 to 127]
This data buffer holds the housekeeping data from the FPE.
Bit Field
Data
Bit#
31:0
Number of
Values
Variable
x16. This is
designated in
the FPE
Translate to FPE WDATA address
37-14010
Access
RW
Reset
0
Description
Address 0 (31:24): Unused
Address 0 (23:16): Total number of
16-bit housekeeping samples and
register values.
Address 0 (15:9): Unused
Address 0 (8:0): Housekeeping select
(HSK_SEL) value.
Address 1 (31:16): Housekeeping
sample1.
Address 1(15:0): Housekeeping
sample2.
Etc.
Address N (31:16) : Second to last
register value.
Address N (15:0) : Last register value
Page 29 of 45
Description of FPE
Memory
Housekeeping
Samples and Status
Registers
Revision D
6.2.3 Data Processing Modules Configuration Registers
These registers allow software to configure and monitor the data processing
modules (currently Science Stamps, Diagnostic, Full Frame, and Guide Stars). There
are five SPMs available. The ENA bit in the CAMn_SPMx_CTRL registers enable a
specific SPM.
6.2.3.1 CAMn_SPMx_CTRL
Control register for the data processing module. This includes enabling the SPM, as
well as configuring it for what actions to take when a pixel packet arrives. Note that
for current functionality, the values of bits 4:0 are as follows:
 Science stamps: “10111”
 Diagnostic frames (accumulated, no cosmic ray mitigation): “00101”
 Full Frame Images: “10101”
 Guide stars: “00011”
Bit Field
SUB_MAX
Bit#
4
Access
RW
Reset
0
SUB_MIN
3
RW
0
ACCUM
2
RW
0
BIT_MASK
1
RW
0
ENA
0
RW
0
Description
Subtract the maximum from a
specified number (CHUNK_SIZE)
of 2-second integrations.
Subtract the minimum from a
specified number (CHUNK_SIZE)
of 2-second integrations.
Accumulate images according to
INTEGRATION register.
Use a bit mask to select pixels in
the frame.
Enable this SPM. When 1, the
SPM is enabled.
6.2.3.2 CAMn_SPMx_INT_NUM
Bit Field
Bit#
INTEGRATION 31:0
Access
RW
Reset
0
Description
How many frames to
accumulate (+1). For example,
if set to 7, then 8 frames will be
accumulated before
interrupting the SBC. If set to 0,
then the SBC will be
interrupted at each 2 second
frame (equivalent to no
accumulation).
6.2.3.3 CAMn_SPMx_CHUNK_NUM
37-14010
Page 30 of 45
Revision D
Bit Field
Bit#
CHUNK_SIZE 31:0
Access
RW
Reset
0
Description
If max/min are set in the CTRL
register, this is the number of
consecutive frames to keep track
of the max/min values. The
max/min values will be
subtracted off after the last
frame in the CHUNK_SIZE is
processed.
Reset
0
Description
How many frames between
processing. For example, if set to
32, then once an INT_NUM of
frames have been processed, 32
frames will be ignored before
resuming processing. A value of
0 means the processing will be
continuous.
6.2.3.4 CAMn_SPMx_PAUSE_NUM
Bit Field
PAUSE
Bit#
31:0
Access
RW
6.2.3.5 CAMn_SPMx_CURRENT_INT
This represents the current integration being processed. In order to write to this
register the ENA bit in the CAMn_SPMx_CTRL register must be set to ‘0’.
Bit Field
Bit#
CURRENT_INT 31:0
Access
RW
Reset
0
Description
The current integration being
processed. This can be written,
but only when the SPM is not
enabled (ENABLE bit in CTRL
register).
6.2.3.6 CAMn_SPMx_FRAME_START
Indicates the value of the FRAME_COUNTER register when the first integration
starts. This clears (gets the value of the next integration frame start) once software
has cleared the interrupt bit for the completed transfer, or when the next
integration cycle is complete, so this register must be read before either of those
events occur for accuracy.
Bit Field
START
37-14010
Bit#
31:0
Access
RO
Reset
0
Description
Registered value of
FRAME_COUNTER when
integration begins.
Page 31 of 45
Revision D
6.2.3.7 CAMn_SPMx_FRAME_END
Indicates the value of the FRAME_COUNTER register when the first integration ends.
This clears (gets the value of the next integration frame end) once software has
cleared the interrupt bit for the completed transfer, or when the next integration
cycle is complete, so this register must be read before either of those events occur
for accuracy.
Bit Field
END
Bit#
31:0
Access
RO
Reset
0
Description
Registered value of
FRAME_COUNTER when
integration ends.
6.2.3.8 CAMn_SPMx_BM_NUM_PXLS
The number of bits set in the bit mask. This will be checked against the number of
asserted bits pulled out of the memory. If these don’t match, the software will be
interrupted to reload the bit mask.
Bit Field
Bit#
NUM_PIXELS 31:0
Access
RW
Reset
0
Description
Number of asserted pixels in
the bit mask.
6.2.3.9 CAMn_SPMx_BM_BAR
Base address for the bit masks in the DDR memory (if one is used).
Bit Field
Base_Addr
Bit#
28:0
Access
RW
Reset
0
Description
Base address in bytes
6.2.3.10 CAMn_SPMx_MIN_BAR
Base address for the minimum temporary values in the DDR memory (if one is
used).
Bit Field
Base_Addr
Bit#
28:0
Access
RW
Reset
0
Description
Base address in bytes
6.2.3.11 CAMn_SPMx_MAX_BAR
Base address for the maximum temporary values in the DDR memory (if one is
used).
Bit Field
Base_Addr
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28:0
Access
RW
Reset
0
Description
Base address in bytes
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6.2.3.12 CAMn_SPMx_DATA_BAR_BUFA/B
Base address for the data memory. There are two buffers (A and B) that are used in
order to avoid overwriting data while the accumulated pixels are transferred to the
SBC memory.
Bit Field
Base_Addr
Bit#
28:0
Access
RW
Reset
0
Description
Base address in bytes
7 Resets
The resets listed here are from most disruptive to least disruptive.
7.1 Power Up
After the FPGA is powered up, the bitfile must be loaded. After the load is complete,
the Xilinx Global Synchronous Reset is released, and all flip flops, including
memories and registers, are set to a value determined by the initialization in the
configuration file.
7.2 Hardware Reset
Two active low signals routed through the onboard Microsemi processor can be
toggled to reset each entire FPGA individually. The hardware reset is synchronized
to each clock domain, and made active high.
Both camera-processing sides of the FPGA are reset. All registers are cleared to their
initial values. State machines are returned to their idle states. This includes the PCIe
bus logic and the XADC logic. On chip block memories are not cleared.
The Xilinx DDR2 controller responds to resets as follows: After deassertion of
system reset, the PHY performs the required power-on initialization sequence for
the memory. This is followed by several stages of timing calibration for both the
write and read datapaths.
7.3 Software Reset
A writeable software register per camera (CAMn_CONTROL) performs the same
actions as a hardware reset, but for only one camera, and excluding the PCIe bus
logic and the XADC logic, which is shared between cameras.
7.4 Frame Start
A frame start signal resets many of the state machines involved in processing. See
the following table for module resets.
Module
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Description
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Hard Soft
Frame
Reset Reset Start
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Module
Description
Hard Soft
Frame
Reset Reset Start
480 MHz interface to
identify, collect data bytes
from DDL. Can be disabled
via CAMn_CONTROL
register.
Decodes the incoming
data bytes
Y
Y
Y
Y
Y
Y
Encodes the commands
for the FPE
Serializes the FPE
commands
Y
Y
N
Y
Y
N
Collects the pixels until
1024 are received,
transmits them to the
SPMs
Y
Y
N
General chip registers
Memory dump handling
for reading out FPE
memories
Housekeeping handling
for reading out FPE
housekeeping
Y
Y
Y
Y
N
N
Y
Y
N
Science Processing
Modules
Process all science data.
Can be disabled.
Y
Y
N
PCIe Modules
The read/write interface
from the SBC.
Y
N
N
DDR2 Modules
Read/write access to the
DDR.
Y
Y
N
FPE Data Downlink
Synchronizer
Data Decoder
FPE Command
Command Encode
Command Interface
Pixel Collector
Control
Registers
Memdump
Housekeeping
8 Clocks
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Table 5: DHU Clocks
Clock
Name
Speed
Input Oscillator Clocks
60 MHz
OSC_CLK_60
Notes
100 MHz
OSC_CLK_100
125 MHz
OSC_CLK_125
125 MHz
CLK_CAM1_SysDDR
200 MHz
CLK_CAM1_RefDDR
125 MHz
CLK_CAM2_SysDDR
200 MHz
CLK_CAM2_RefDDR
Generated FPE Interface Clocks
480 MHz
DDL_CLK_S
125 MHz
DDL_CLK_P
3 MHz
FPE_CMD_CLK
Generated Internal Logic Clocks
125 MHz
CLK_125
Generated PCIe Clock
62.5 MHz
PCIe_USR_CLK
Generated DDR Clock
125 MHz
DDR_USR_CLK
Input clock from 60 MHz board oscillator.
Single ended
Input clock from 100 MHz board oscillator
into the PCIe reference clock. Differential
LVDS
Input clock from 125 MHz board oscillator.
Differential LVDS
Input clock from 125 MHz board oscillator
into the DDR2 system clock. Differential
LVDS
Input clock from 125 MHz board oscillator
into the DDR2 reference clock. Differential
LVDS
Input clock from 125 MHz board oscillator
into the DDR2 system clock. Differential
LVDS
Input clock from 125 MHz board oscillator
into the DDR2 reference clock. Differential
LVDS
Clocks serial side of Data Downlink.
Clocks parallel side of Data Downlink.
Clocks the command/configuration to the
FPE. Also clocks the SEU interface.
Internal FPGA 125 MH.
Clock for interfacing to Xilinx PCIe core
Clock for interfacing to Xilinx DDR2 core
8.1 DDR2 Interface Clock Tree
For information on the DDR2 Interface Clock Tree, refer to Xilinx specification
UG586 7 Series Devices Memory Interface Solutions. Input clocks to the DDR2 logic
include a 200 MHz reference clock, and
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8.2 PCIe Interface Clock Tree
The 100 MHz signal comes into a MGT pin and is sent directly to the Xilinx PCIe core
without buffering. The Xilinx PCIe core produces a 62.5 MHz clock for the user
interface. For details on the PCIe Interface Clock Tree, refer to Xilinx specification
PG054 7-Series Integrated Block for PCI Express.
8.3 FPE Interface Clock Tree
PLL : Phased Lock Loop
BUFR : Clock buffer with divide
8.4 Internal Logic Clock Tree
8.5 Clock Crossing Boundaries
The clock crossing boundaries are as shown in the following diagram. No
assumption is made about phase alignment. All control signals across boundaries
are double registered and extended, when traversing a fast to a slow clock domain,
or pulsed, when traversing a slow to a fast clock domain.








PCIe (62.5)/DDR (125)
PCIe (62.5)/registers (125)
PCIe(62.5)/SPMs (125)
DDR(125)/DDL(125)
CMD(3)/registers(125)
CMD(3)/DDR(125)
XADC(125)/DDR(125)
SPMs(125)/DDR(125)
9 FPGA Configuration
The FPGA bit file can be loaded via a 32-bit SMAP or a JTAG bus, controlled by a
three-bit input from the processor board. In the Xilinx Virtex 7 User’s Guide, this is
designated by input pins M[2:0].
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A JTAG interface will be provided for lab configuration of the FPGA. Per Xilinx
specification, this interface is always available, regardless of M pin settings.
10 Radiation Mitigation
10.1 Automatic error detection
10.1.1 Data Memories
With the exception of the bit masks, all memory, both on and off chip, contains
transient data, and therefore has no ECC. The bit masks, when read, will count
asserted bits. If this doesn’t match with a programmed register value, the SBC will
be interrupted, and the memory rewritten.
10.1.2 Configuration Memory
The configuration error detection/correction module instantiates the Frame_ECC2
Xilinx IP module, and captures the output data. At each 1 PPS pulse from the
spacecraft, the current state of the error detection/correction is forwarded to the
SBC using a Clk, Strobe and data as follows:
D0
D1
D2
D3
D4
D5
D6
The clock is running at 10 MHz. The strobe is active for one 10 MHz clock. Data
changes on positive edge of 10 MHz clock—start reading on first negative edge after
strobe. Bit 0 is first, and bit 54 is last. See Xilinx UG470 for details about the
information sent.
Bit
0
1
2
28:3
Name
CRC Error
ECC Error
ECC Single Error
FAR
33:29
Synbit
46:34
Syndrome
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Description
High until fixed
High until fixed
High until fixed
Frame Address Register
Value
Output bit address of
error
Output location of
erroneous bit
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47
54:48
Syndrome Valid
Synword
Output is valid
Word output on the frame
where an ECC error has
been detected
63:55
Unused
N/A
The SBC will take action to correct the configuration data if necessary.
10.1.3 Registers
All registers that hold persistent data will have a parity bit that is calculated when
the register is written. These bits will be checked on read. Each of the enabled SPMs
will interrupt the SBC upon detecting an error.
10.2 Other error detection
10.2.1 Overview
If memories and configuration report no issues, but an SEU has occurred in the logic,
this can be detected in multiple ways. There are three possible mitigations:
1. Issue a soft reset to one of the cameras (affects one camera)
2. Issue a hard reset to an entire FPGA (affects two cameras)
3. Power cycle the FPGA board and reconfigure the FPGAs (affects all cameras)
10.2.2 Loss of sync/bad downlink control byte
The synchronization byte is transmitted whenever there is no data, and the
downlink control byte is transmitted per packet. Loss of sync might occur if an SEU
occurs in DDL logic, either in the FPE or DHU, or in the data itself. The DHU will
detect this immediately and issue a loss of sync interrupt. If it is simply a data bit
flip, it will correct itself. Otherwise, the problem will persist.
10.2.3 Missing interrupt
There are at least two interrupt events to the SBC per frame for the guide stars. If an
interrupt has not been issued before the next frame begins, the SBC can assume an
error on that camera.
11 Conventions
In this design, bit ‘0’ designates the LSB. All transfers will transmit the least
significant byte/word/double word first. Data and memories are little endian. The
exception to this is the PCIe, which runs big endian, and is translated in the PCIe
interface module.
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12 Design For Test
12.1 Signal I/O
Sixteen debug signals are available via the Debug I/O bus for observability of
functions while lab testing.
12.2 Memory/Register Accessibility
The JTAG interface will have access to all memories and registers of the design.
12.3 Image Generation
The DDL Interface captures data from the FPE. In the absence of an FPE, three
algorithms can be used to generate automatic data. These algorithms are selectable
by the CAMn_TEST_DATA registers.
13 Design Configuration Analysis
13.1 Overview
This section takes the current planned configuration and analyzes the firmware for
memory space and bandwidth requirements. As science requirements firm up, this
section will change. TBD
13.2 Memory Size Requirements
13.2.1 Guide Star
For the data, assume 50 guide stars of approximately 10x10 4-byte pixels per CCD.
This yields 200x100x2 bytes = 40 KB.
The bit mask is a constant size, based on the number of pixels. There is 1 bit per
pixel, 2128x2076 data pixels, and 4 CCDs. This yields 2.11 MB per camera.
13.2.2 Science Stamp
For data, assume 5000 science stamps of approximately 100 pixels per camera. For
accumulation purposes, each pixel is allotted 4 bytes of space. This yields
5000x100x4 = 2 MB of memory per buffer per camera.
As stated in the Guide Star section, the bit mask is 2.11 MB per camera.
13.2.3 Asteroseismology 10-second integration
For data, assume 50 science stamps of approximately 100 pixels per camera. For
accumulation purposes, each pixel is allotted 4 bytes of space. This yields 50x100x4
= 2 kB of memory per buffer per camera.
As stated in the Guide Star section, the bit mask is 2.11 MB per camera.
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13.2.4 Full Frame
The total number of pixels per frame per CCD is 2128x2076. Four bytes are allowed
for accumulation.
For 2128x2076 pixels x 4 CCDs x 4 bytes, this yields 67.4 MB data. This is per buffer
per camera.
With cosmic ray mitigation, subtracting both min and max, raw pixels must be saved
for the running min and max values. For 2128x2076 pixels x 4 CCDs x 2 bytes, this
yields 33.7 MB per min/max.
13.2.5 Diagnostic Frame
With a frame of 2128 x 2076 x 2bytes x 4 CCDs, the required memory is
approximately 33.7 MB. This is per buffer per camera.
13.3 Memory Map Example
The following diagram is to demonstrate the current memory usage for one camera,
and not the exact locations of the data. It is programmable by base address registers.
Two buffers are necessary for data memories so that the SBC can transfer data out
of one while the FPGA is processing the other.
Though the diagram shows 2 MB boundaries, it is only required to maintain 32 byte
boundaries. The banks are shown to make the diagram easier to read. The DDR2
interface presents one contiguous memory space.
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Figure 4: Example DDR2 Memory Configuration
13.4 Timing diagrams/information
13.4.1 Pixel batch transfer/processing
The FPE sends 16 pixels, of 2 bytes each, plus one control byte, every 1.6 us (see FPE
specification for details). These raw pixels are collected until 1024 pixels have been
received. This will require receiving 64 pixel packets. At 1.6 us per packet, this will
take 102.4 us. This means all SPMs have to have their processing complete in 102.4
us, to be ready for the next pixel data.
Once the pixels are transferred to the SPMS, the SPMs load the information they
need from the DDR2 memory, do processing, and store the processed data into the
DDR2 memory.
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The following table shows an example for processing a sample science stamp
packet. This is a worse case configuration. Note that this table can be viewed as a
timeline, advancing time by the number of clock cycles given in each row. The total
time, given the number of clock cycles at 3968 and a 125 MHz clock, is 31.7 us. With
an overhead of 10%, this becomes approximately 35 us. This, however, assumes that
there is no contention on the DDR2 bus, which is not the case. See the next section
for details.
Table 6: Processing cycle time example for science stamps with cosmic ray mitigation, worse case
Action
Load Raw pixel data from DDL interface
Load bit mask from DDR2
Load minimum values from DDR2
Load maximum values from DDR2
Load accumulated values from DDR2
Process Pixels State Machine
Write minimum value update to DDR2
Write maximum value update to DDR2
Store processed pixels to DDR2
Number of 125 MHz
clock cycles
1024
128
128
128
128
2048
128
128
128
13.4.2 DDR2 Memory Contention during Processing
The following list shows the worst case timing, when all processing units are
requesting access to the DDR2 memory, and all processing units request to transfer
1024 pixels of data. It is assumed that no other contention (PCIe) is allowed to occur
during this time. This is guaranteed by firmware arbitration.
The DMA transfers for all current processing units are shown in the table below.
Note that this is worst case. For instance, data is only read from/written to the
DDR2 when needed. Bit masks mean that for a large percentage of the time
(depending on how many pixels are selected), no access to the DDR memories will
occur.
1. Guide Star Bit Mask Read
2. Guide Star Pixel Write
3. Science Stamp Bit Mask Read
4. Science Stamp Accum Read
5. Science Stamp Min Read
6. Science Stamp Max Read
7. Science Stamp Min Write
8. Science Stamp Max Write
9. Science Stamp Accum Write
10. Full Frame Accum Read
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11. Full Frame Min Read
12. Full Frame Max Read
13. Full Frame Min Write
14. Full Frame Max Write
15. Full Frame Accum Write
16. Diag Accum Read
17. Diag Accum Write
Each of these accesses is 128 cycles (this is determined by 1024 32-bit words
transferred 256 bits at a time to the DDR2 interface). This means that to complete
all transfers is 128*17 = 2176. Assuming arbitration overhead of 10%, this is
approximately 2400 cycles. At 125 MHz, this is 19.2 us.
Effectively, this means that all Science Processing Modules take 19.2 us to access the
DDR. If we add processing time of approximately 17 us (2048 cycles) and raw data
pixel transfer of approximately 9 us, then the total time to process a frame is
approximately 45 us for all SPMs. This worse case scenario is well within the 102 us
time allotted; however, the margin allows for further processing of the SPM. It also
allows for the SBC to get into the memories, if necessary, without corrupting science
data.
13.4.3 Transfer to SBC
When the End of Frame symbol is received, each SPM checks its counter. If the
counter has reached its maximum value, meaning all processing is complete, then it
interrupts the SBC. The SBC sets up a PCIe data transfer to extract the specified data
from the DDR memories.
Given 1.77 seconds (see below) to transfer an entire frame, and 2 seconds to collect
new images, the processor has approximately 0.23 seconds to do all transfers (TBD).
This includes the time it takes to service the interrupt, and set up the PCIe transfer.
Given that the data is not being processed at this time, the PCIe will be the only
client of the DDR2 memories, and will therefore not face contention. While science is
processing, any pending transfer from the PCIe will be stalled until processing is
complete, or at the next start of frame, if there has been an error.
Calculation for above:
PPF : Number of pixels per CCD per frame = 2128x2076 = 4.42 MPixels
NC : Number of CCDs = 4
PC: Pixel Clock time = 24 cycles at 15 MHz = 1600 ns
NP: Number of pixels transferred per clock = 16
TF = Time to transfer an entire camera frame
TF = PPF*NC* PC/NP = 1.77 s
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Only guide stars must be transferred every frame, as the data is needed for
quaternion calculations. All other transfers can happen over a longer period.
The table below shows the size of each of the data packets, along with how many
bits need to be transferred every frame.
Taking full frame images as an example:
The total number of bits accumulated for thirty minutes in a full frame image is 566
Mb. With two full frame image buffers, this means that all data must be transferred
within 30 minutes, before the next buffer begins filling.
Table 7: Frame Transfer Values
Data
Size
Guide Stars
200 guide stars *
100 pixels/GS * 16
bits/pixel ~ 1 Mb
4 CCD*2128*2076
0.63
pixels * 32 bits/pixel
~ 566 Mb
Full Frame Image
Mb/Frame to
Transfer
1
Science Stamps
5000 science stamps 0.53
* 100 pixels/SS * 32
bits/pixel ~ 16 Mb
Diagnostic Data
4
CCD*2128*2076*32
bits/pixel ~ 566 Mb
0.63
Notes
All bits need to be
transferred at every
frame.
566/900
All bits need to be
transferred every 30
minutes, or 900
frames.
16/30
All bits need to be
transferred every 2
minutes, or 30 frames
Diagnostic Data’s
purpose has not yet
been determined.
Assume the same
cadence as Full
Frames.
The PCI Express bus can transfer 32-bit words at 100 MHz, or 3.2 Gbps. Overhead
brings this down to approximately 2.56 Gbps.
To keep from transferring data while the SPMs are processing, this gives 0.23
seconds to transfer 2.79 Mb of data. This means we need to run at 12.1 Mbps, far
within the margin of the PCIe bus.
14 Acronyms/Abbreviations
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ADC
BAR
CCD
CS
CT
DDL
DDR
DDR2
DFT
DHU
ECC
FFI
FPGA
FPE
GPIO
GS
JTAG
LSB
MMCM
MSB
PCIe
PLL
PPS
SBC
SEU
SPM
SS
SSB
TBD
TESS
UART
XADC
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Analog to Digital Converter
Base Address Register
Charge Coupled Device
Channel Stop
Command/Telemetry
Data Downlink
Double Data Rate
Double Data Rate Memory, Generation 2
Design for Test
Data Handling Unit
Error Correcting Code
Full Frame Image
Field Programmable Gate Array
Focal Place Electronics
General Purpose Input/Output
Guide Stars
Joint Test Action Group (Test Access Port and Boundary Scan)
Least Significant Bit
Mixed Mode Clock Manager
Most Significant Bit
PCI (Peripheral Component Interface) Express
Phase Locked Loop
Pulse Per Second
Single Board Computer
Single Event Upset
Science Processing Module
Science Stamps
Solid State Buffer Memory
To Be Determined
Transiting Exoplanet Survey Satellite
Universal Asynchronous Receiver Transmitter
Xilinx Analog-Digital Converter
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