N07
page 1 of 15
Combinational Logic
two logic states
0 = false = off = low = space
TTL and CMOS nominally 0V (actually 0V to 0.8V)
1 = true = on = high = mark
TTL nominally +5V (actually 3V to 5V)
low level TTL nominally +3.3V (actually 2.4V to 5V)
NOT
CA
A
A
AND
C  AB
C
C
B
A
NAND
C  AB
C
B
A
OR
C  AB
C
B
A
NOR
C  AB
B
C
A
0
1
CA
1
0
A B
0 0
0 1
1 0
1 1
C  AB
0
0
0
1
A B
0 0
0 1
1 0
1 1
C  AB
1
1
1
0
A
0
0
1
1
B
0
1
0
1
C  AB
0
1
1
1
A
0
0
1
1
B
0
1
0
1
C  AB
1
0
0
0
N07
XOR
A
C  AB
C
B
NXOR
(equality)
C  AB
A
C
B
4-input AND
Q  A  BC D
A
B
C
D
Q
page 2 of 15
A
0
0
1
1
B
0
1
0
1
C  AB
0
1
1
0
A
0
0
1
1
B
0
1
0
1
C  AB
1
0
0
1
A
X
X
X
0
1
B
X
X
0
X
1
C
X
0
X
X
1
D
0
X
X
X
1
Q  A  BC D
0
0
0
0
1
N07
page 3 of 15
Equivalent Gates
A
A
C
A
A
C
B
A
C
C
B
C
A
B
B
A
A
B
A
C
C
B
C
C
A
0
0
1
1
B
0
1
0
1
1
1
0
0
1
0
1
0
1
0
0
0
A
0
0
1
1
B
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
N07
page 4 of 15
Design XOR using only NANDs
Digital design
1) find a circuit that provides most of desired functionality
2) design a circuit that will produce the differece between desired and available functionality
3) combine 1) and NOT 2)
N07
page 5 of 15
Transistor-Transistor Logic (TTL)
+5V
C
A
C
C
A
B
no current
leakage
E
A
0V
5V
iBE
off
on
iCE
off
on
C
5V
~0V
+5V
i
C
C
A
A
B
C
E
B
C
B
B
A
0V
0V
5V
5V
B
0V
5V
0V
5V
i
off
off
off
on
C
5V
5V
5V
~0V
A
0V
0V
5V
5V
B
0V
5V
0V
5V
i
off
on
on
on
C
5V
~0V
~0V
~0V
E
+5V
i
C
A
A
B
C
B
E
C
B
C
B
E
N07
page 6 of 15
TTL chips
must provide GND and +5V
74xy or 74xyz
74LSxy or 74LSxyz
74Lxy or 74Lxyz
74Hxy or 74Hxyz
74Cxy or 74Cxyz
standard TTL
low power Schottky
low power
high speed
CMOS
54xy or 54xyz
military grade (broader temperature range)
Propagation delay
t
A
C
A
C
Much better at sinking current than sourcing current
source ~ 20 mA
sink ~ 50 mA
+5V
fan-out
sourcing current
(may cause droop)
sinking current
(preferred)
Tri-state high impedance output (hi-Z)
A
B
EN
C
A
B
C
EN
DO NOT connect two TTL outputs together unless they are tri-state
EN
1
1
1
1
0
A
0
0
1
1
X
B
0
1
0
1
X
C
1
1
1
0
hi-Z
N07
page 7 of 15
Open collector output (no internal pull-up resistor)
C
A
A
B
C
B
C
E
B
C
B
E
N07
n07_chips.pdf
Basic combinational gates
7400 quad 2-input NAND
7402 quad 2-input NOR
7404 hex inverter
7408 quad 2-input AND
7432 quad 2-input OR
7486 quad 2-input XOR
7420 dual 4-input NAND
Combinational
74138 3-to-8 decoder
74139 dual 2-to-4 decoder
74154 4-to-16 decoder
7447 4-to7 seven segment decoder (common anode)
7448 4-to7 seven segment decoder (common cathode)
74148 8-to-3 priority encoder
74151 8-to-1 multiplexor
74153 dual 4-to-1 multiplexor
74157 quad 2-to-1 multiplexor
7483 4b adder with carry
7485 4b equality test with carry
74125 quad tri-state independent drivers
74244 octal tri-state bus drivers
Sequential
7474 dual D F/F positive edge
74273 octal D F/F positive edge
74112 dual J-K F/F negative edge
7490 4b decade counter
7493 4b binary counter
74191 4b binary up/down counter
7495 4b shift register
74195 4b bidirectional shift register
74164 8b parallel out shift register
page 8 of 15
N07
page 9 of 15
Sequential Logic
Basic flip-flop (F/F)
A
X
Y
B
A
0
0
1
B
0
1
0
X
1
1
0
Y
1
0
1
not used
set X
reset X
1
1
1
1
0
1
1
0
hold
hold
S-R F/F with positive level clock
S
Q
A
R
B
CLK
0
1
1
1
1
S
x
0
0
1
1
R
x
0
1
0
1
A
1
1
1
0
0
B
1
1
0
1
0
Q
hold
hold
0
1
1
not used
reset
set
not used
CLK
Transparent D F/F with positive level clock
D
CLK D Qn+1
Q
CLK
0
x
Qn
1
1
0
1
0
1
D
CLK
Q
N07
Clock
a) continuous pulse train
b) one shot pulse
Four types of clock inputs
a) positive level
CLK
b) negative level
CLK
c) positive edge
CLK
d) negative edge
CLK
Transparent versus edge triggered D F/F
D
S
D
Q
CLK
CLK
R
D
S
Q
Q
D
Q
CLK
R
CLK
Q
Q
page 10 of 15
N07
page 11 of 15
Quadrature for optical encoder
CCW
A leads B
A
A
B
B
CW
A
B
A leads B
D
Q
CLK
CCW / CW
positive edge
D flip-flop
(Q captures value of A
when positive edge
appears on B)
N07
page 12 of 15
Shift register (serial input, parallel output)
b0
IN
D
S
b1
Q
CLK
R
S
D
Q
CLK
Q
R
b2
D
S
Q
CLK
Q
R
b3
D
S
Q
CLK
Q
R
Q
CLK
A serial input, parallel output, 8 bit shift register shifts left toward the MSB when
clocked. The MSB output has been connected to the serial input after 36 hex has been
loaded. Show the contents after 3 more clocks. Show hex, binary and decimal.
HEX
initial contents
36
after 1st clock
after 2nd clock
after 3rd clock
General purpose shift register
parallel out
serial in
CLK
output enable
serial out
R/L
parallel load
parallel in
BINARY
UNSIGNED
DECIMAL
N07
page 13 of 15
J-K F/F
Qn+1 appears immediately after CLK edge
J
S
K
Qn+1
0
0
Qn
hold
0
1
1
1
0
1
0
1
Qn
reset
set
toggle
Q
CLK
K
J
Q
R
J
S
Q
J
CLK
K
R
S
Q
CLK
Q
K
R
Q
N07
page 14 of 15
Counters
J
S
Q
J
CLK
K
J
R
S
R
Q
J
CLK
Q
K
Q
J
CLK
K
S
R
S
K
R
Q
J
CLK
Q
K
Q
J
CLK
Q
S
R
S
K
R
Q
CLK
Q
K
Q
J
CLK
Q
S
R
S
Q
Q
CLK
Q
K
R
Q
N07
General purpose counter
parallel out
carry in
CLK
output enable
carry out
U/D
parallel load
parallel in
page 15 of 15