Supported by Cadence Design Systems, Inc. and MARCO/DARPA GSRC
Performance-Impact Limited
Area Fill Synthesis
Yu Chen
UbiTech, Inc.
Puneet Gupta, Andrew B. Kahng
Univ. of California, San Diego
http://vlsicad.ucsd.edu
1
Outline
 Chemical Mechanical Planarization and Area Fill
 Performance-Impact Limited (PIL) Fill Problem
 Capacitance and Delay Models
 Approaches for PIL-Fill Problems
 Computational Experiences
 Conclusion and Future Works
2
CMP & Area Fill
 Chemical-Mechanical Planarization (CMP)
•
Polishing pad wear, slurry composition, pad elasticity make
this a very difficult process step
wafer carrier
silicon wafer
slurry feeder
polishing pad
slurry
polishing table
 Area fill feature insertion
• Decreases local density variation
• Decreases the ILD thickness variation after CMP
Features
Post-CMP ILD thickness
Area fill
features
3
Fixed-Dissection Regime
 To make filling more tractable, monitor only fixed set of w  w
windows
•
offset = w/r (example shown: w = 4, r = 4)
 Partition n x n layout into nr/w  nr/w fixed dissections
 Each w  w window is partitioned into r2 tiles
w
w/r
tile
Overlapping
windows
n
4
Previous Objectives of Density Control
 Objective for Manufacture = Min-Var
minimize window density variation
subject to upper bound on window density
 Objective for Design = Min-Fill
minimize total amount of added fill features
subject to upper bound on window density variation
5
Previous Works on Area Fill
 Kahng et al.
•
•
•
•
First LP-based approach for Min-Var objective
Monte-Carlo/greedy method
Iterated Monte-Carlo/greedy method
Monte-Carlo methods for hierarchical fill problem
and multiple-layer fill problem
 Wong et al.
•
•
LP-based approaches for Min-Fill objective
LP-based approaches for multiple-layer fill
problem and dual-material fill problem
6
Outline
 Chemical Mechanical Planarization and Area Fill
 Performance-Impact Limited (PIL) Fill Problem
 Capacitance and Delay Models
 Approaches for PIL-Fill Problems
 Computational Experiences
 Conclusion and Future Works
7
Performance-Impact Limited Area Fill
 Why?
•
Fill features insertion to reduce layout density variation
change coupling capacitance
change interconnect signal delay and crosstalk
•
Current methods: no consideration of performance impact
during fill synthesis
Timing Closure Error ?
Filled layout
8
Related Works
 General guidelines:
•
•
•
•
Minimize total number of fill features
Minimize fill feature size
Maximize space between fill features
Maximize buffer distance between original and fill features
 Sample observations in literature
•
Motorola [Grobman et al., 2001]
key parameters are fill feature size and buffer distance
•
Samsung [Lee et al., 2003]
floating fills must be included in chip-level RC extraction and
timing analysis to avoid timing errors
•
MIT MTL [Stine et al., 1998]
proposed a rule-based area fill methodology to minimize added
interconnect coupling capacitance
9
Performance-Impact Limited Area Fill
 Problem Formulation
•
Two objectives:
- minimize layout density variation due to CMP
- minimize fill features' impact on circuit performance
•
In general, cannot minimize two objectives
simultaneously
- minimize one objective while keeping the other as constraints
•
Two formulations for PIL Fill problem
- Min-Delay-Fill-Constrained (MDFC) objective
- Max-MinSlack-Fill-Constrained (MSFC) objective
10
Min-Delay-Fill-Constrained Objective
 Given
•
•
•
•
•
A fixed-dissection routed layout
Design rule for floating square fill features
Prescribed amount of fills in each tile
Direction of current flow in each tile
Per-unit length resistance for interconnect segment in
each tile
Fill layout
such that
 Insert
fill features
into each tile such that
•
Performance
impact
total increase in wire
Total impact on
delay(i.e.,
is minimized
segment delay) is minimized
 Weakness of MDFC objective
•
can not directly consider the impact due to fill features
on the signal delay of complete timing paths
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Max-MinSlack-Fill-Constrained Objective
 Given
•
•
•
A fixed-dissection routed layout
Design rule for floating square fill features
Prescribed amount of fills in each tile
 Fill layout such that
•
minimum slack over all nets in the layout is
maximized
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Outline
 Chemical Mechanical Planarization and Area Fill
 Performance-Impact Limited (PIL) Fill Problem
 Capacitance and Delay Models
 Approaches for PIL-Fill Problems
 Computational Experiences
 Conclusion and Future Works
13
Capacitance and Delay Models
 Interconnect capacitance consists of
•
•
•
Overlap Cap.
: surface overlap of two conductors
Coupling Cap.
: two parallel conductors on the same plane
Fringe Cap.
: two conductors on different planes
 Mainly consider fill impact on coupling capacitance
 Elmore Delay Model
•
First moment of impulse response for a distributed RC
interconnect
•
Enjoys additivity property with respect to capacitance
along any source-sink path
14
Additivity Property of Elmore Delay Model
 Elmore Delay of RC Tree
 R1  C1
 R1  C1
 C1
 R1  C1
15
Slack Site Column
 Grid layout with fill feature size into sites
 Slack Site Column: column of available sites for fill
features between active lines
Active
lines
slack site
column
top view
w
fill grid
pitch
buffer distance
•
Per-unit capacitance between two active lines separated by
distance d, with m fill features in one column:
16
Slack Site Column in Tile
 Slack site columns in fixed-dissection regime
•
•
Between active line and tile boundary
Between active lines in adjacent tiles
 Advantage
•
Possible impact of fill feature at any position can be considered
1
2
Tile
Active
lines
3
A
D
4
F
B
C
7 slack blocks
E
5
G
6
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Scan-Line Algorithm
 Find out slack columns (within each tile) between pairs of
active lines in adjacent tiles
 Scan whole layout from bottom (left) boundary for horizontal
(vertical) routing direction
1
2
Tile
Active
lines
3
A
D
4
F
B
C
7 slack blocks
E
5
G
6
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Outline
 Chemical Mechanical Planarization and Area Fill
 Performance-Impact Limited (PIL) Fill Problem
 Capacitance and Delay Models
 Approaches for PIL-Fill Problems
 Computational Experiences
 Conclusion and Future Works
19
ILP Approach for MDFC PIL-Fill
 #RequiredFills obtained from normal fill synthesis
 Objective:
minimize weighted incremental delay due to fill features
Minimize:
l
: num of downstream sinks of segment
 Based on pre-built lookup table for coupling
capacitance calculation
•
Fill features have the same shape
•
Potential num of fill features in each column is limited
•
Other parameters are constant for the whole layout
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ILP Approach for MDFC PIL-Fill
 Constraints:
Binary:
1
mk n  
0
Ck
1.
mk   n  mkn
n 1
2.
mk  n
otherwise
Ck
m
n 1
kn
F   mk
 1 for each column
for all overlapping columns
# used slack sites = # fill features
Ck
3.
Capk   f (n, d k )  mkn
n 1
l
4.
incremental cap. due to mk features in each column
k
 l   Capk  ( Rl   rl j )
k 1
for each column
for each segment
j 1
total Elmore delay increment
5.
0  mk  Ck
# used slack sites  column size
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Greedy Method for for MDFC PIL-Fill
 Run standard fill synthesis to get #RequiredFills for each tile
 For each net Do
• Find intersection with each tile
• Calculate entry resistances of net
in its intersecting tiles
 Get slack site columns by scan-line algorithm
 For each tile Do
• For each slack column Do
- calculate induced coupling capacitance of slack column
•
•
Sort all slack columns according to its corresponding delay
While #RequiredFills > 0 Do
- select slack column with minimum corresponding delay
- insert
features into the slack column
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Iterated Approaches for MSFC PIL-Fill
 Pre-Steps:
Partition the given layout into tiles and sites
Run normal area fill synthesis:
required fills (RFij) for each tile,
total number of requires fills (RF)
Scan whole layout to get all slack site columns
 Reduced Standard Parasitic Format (RSPF) file
•
Interface between Static Timing Analysis and fill synthesis
 Iteration variables
•
•
LBslack: lower bound on slack value of slack site columns
UBdelay: upper bound on total added delay during one iteration
23
Iterated Approaches for MSFC PIL-Fill
Update RSPF file
with capacitance increase
Choose slack site column k with
maximum slack value Smax
Run STA tool with RSPF file to get
slacks for all input pins
Smax< LBslack Yes Decrease LBslack
Calculate slack for
Run STA
each active line
Calculate max number of feasible
max number of feasible
fills for slack site column k
fills for
column k
Calculate slack value
for
each slack site column
overlapping size of
Get #fills to be inserted for each min
column k in tile
tile intersecting with column k
number of required
fills for tile
Calculate added delay Dadd
Yes
Dadd > UBdelay
Yes
DF > 0
No
End
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Outline
 Chemical Mechanical Planarization and Area Fill
 Performance-Impact Limited (PIL) Fill Problem
 Capacitance and Delay Models
 Approaches for PIL-Fill Problems
 Computational Experiences
 Conclusion and Future Works
25
Computational Experience
 Testbed
•
C++ under Solaris
•
CPLEX 7.0 as linear programming solver
•
300 MHz Sun Ultra-10 with 1GB RAM
 Test cases
•
In LEF/DEF format
•
Signal delay calculation based on RSPF file
•
Use previous LP/Monte-Carlo methods as normal fill
synthesis (Chen et al. TCAD02)
26
Experiments for MDFC PIL-Fill
Runtime
ofPIL-Fill
PIL-FillSynthesis
Methods
Weighted
800
9000
T o t aC lPDUe(lsaeyc () n s )
700
8000
7000
600
Normal
ILP
ILP
Greedy
Greedy
6000
500
5000
400
4000
300
3000
200
2000
100
1000
00
11
22
33
44
55
66
77
Testcases
Testcases
8
9
10
11
12
12
• PIL-Fill methods are better than normal fill method
• LUT based ILP has better performance but longer runtime
27
Experiments for MSFC PIL-Fill
Iterated Greedy Approaches for MSFC PIL-Fill
2500
M i n i m u m S l a c k (ps)
2000
1500
1000
Orig MinSlack
Normal MinSlack
MSFC MinSlack
500
0
1
2
3
4
5
6
-500
-1000
Testcases
•
Iterated greedy method for MSFC PIL-Fill only decrease minimum slack
of all nets by 7% (min), 20% (average), 37% (max)
significant improvement
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Outline
 Chemical Mechanical Planarization and Area Fill
 Performance-Impact Limited (PIL) Fill Problem
 Capacitance and Delay Models
 Approaches for PIL-Fill Problems
 Computational Experiences
 Conclusion and Future Works
29
Conclusions and Future Research
 Contributions:
•
•
•
•
Approximation for performance impact due to area fill insertion
First formulations for Performance-Impact Limited Fill problem
ILP-based and greedy-based methods for MDFC PIL-Fill problem
Iterated greedy-based method for MSFC PIL-Fill problem
 Future Works
•
Budget slacks along segments
•
Consider impact due to fill on overlap and fringe capacitance
•
Other PIL-Fill formulations
avoid iteration with STA
- Min density variation while obeying upper bound on timing
impact
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Thank You!
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