The 68HC11 Microcontroller
Chapter 5: Operation Modes and Memory Expansion
The 68HC11 Microcontroller
Han-Way Huang
Minnesota State University, Mankato
H. Huang Transparency No.5-1
The 68HC11 Microcontroller
The 68HC11 Operation Modes
- Single chip mode: a mode in which the 68HC11 functions without external address
and data buses. The 68HC11 has 5 I/O ports (A, B, C, D, and E) to use in this mode.
- Expanded mode: a mode in which the 68HC11 has the capability to access a 64KB
address space. In this mode, port B is used as the upper address signals (A15-A8)
and port C is used as time-multiplexed address/data bus (A7/D7-A0/D0). Only three
I/O ports are available for direct use.
- Special test mode: mainly used by Motorola in fabrication testing.
- Special Bootstrap mode: a mode in which a bootstrap ROM is enabled. The
bootstrap ROM contains a loader program that will be executed after the RESET
signal is going high and this program will load in a 256-byte program from the SCI
subsystem to the on-chip SRAM and then transfer the CPU control to that loaded
program.
Establishment of the operation mode
On the rising edge of the RESET, the voltage levels on pins MODA and MODB are
latched into the HPRIO register, which determines the operation mode of the 68HC11.
H. Huang Transparency No.5-2
The 68HC11 Microcontroller
Memory Technologies and Terminology
1. Nonvolatile and volatile memories: differentiated by whether a memory
component will lose its contents when the power is removed.
2. ROMs and RAMs: differentiated by whether a a memory component can be
read/write from/into for roughly the same amount of time.
3. Dynamic and Static RAMs: differentiated by whether a RAM requires periodic
refresh operation in order to maintain its stored information.
4. Memory capacity: the total number of bits that a memory chip contains.
5. Memory organization: describes the number of bits that can be accessed from a
memory chip in one operation. The organization is specified as m  n, where m
is the total number of locations and n is the number of bits in each location.
H. Huang Transparency No.5-3
The 68HC11 Microcontroller
Example 5.1 Using the following memory chips, how many SRAM chips will be
needed to build a 512KB, 16-bit memory system for a 16-bit microprocessor?
a. 256K × 1 SRAM
b. 256K × 4 SRAM
c. 256K × 8 SRAM
d. 64K × 8 SRAM
Solution:
a. Sixteen SRAM chips with × 1 organization are needed to construct a 16-bit
memory system. 16 256K × 1 chips are required to build a 512KB 16-bit
memory system.
b. Four SRAM chips with × 4 organization are needed to construct a 16-bit
memory system. Four 256K × 4 SRAM chips are needed to construct a 512 KB
16-bit memory system.
c. Two SRAM chips with × 8 organization are needed to construct a 16-bit memory
system. Two 256K × 8 SRAM chips are needed to construct a 512 KB 16-bit
memory system.
d. Two SRAM chips with × 8 organization are needed to construct a 16-bit memory
system. Eight 64K × 8 SRAM chips are needed to construct a 512 KB 16-bit
memory system.
H. Huang Transparency No.5-4
The 68HC11 Microcontroller
Reposition 68HC11 on-chip SRAM and I/O registers
-
The upper four bits of the INIT register reposition the on-chip SRAM to the
beginning of any 4KB page
The lower four bits of the INIT register reposition the I/O registers to the
beginning of any 4KB page.
The repositioning of SRAM and I/O registers can only be done within 64 E
clock cycles after reset.
Example 5.2 Reposition the 68HC11 on-chip SRAM to $2000-$20FF and remap I/O
registers to $3000-$303F.
Solution: Set the upper four bits and lower four bits of the INIT register to $2 and
$3, respectively.
SRAM
IOREG
remap
INIT
equ
equ
equ
equ
ldab
staa
…
$20
; value to remap SRAM to $2000-$20FF
$03
; value to remap I/O registers to $3000-$303F
SRAM+IOREG
$1030
#remap
INIT
H. Huang Transparency No.5-5
The 68HC11 Microcontroller
External Memory Expansion Issues
• address space assignment
• address decoding
• timing consideration
Address space assignment
- only unallocated memory space should be assigned to external memory
components
- memory space is often allocated in the unit of 2n KB (n is an integer) for 8-bit
microcontrollers
- address decoder can be simplified if memory space is divided into blocks of the
same size.
Allocated space for the 68HC11A8
$0000-$00FF:
$1000-$103F:
$B600-B7FF:
$E000-$FFFF:
SRAM
I/O registers
EEPROM
ROM
H. Huang Transparency No.5-6
The 68HC11 Microcontroller
Example 5.3 Assign the 68HC11 memory space using a block size of 4KB.
Solution: The 64KB memory space can be divided into 16 4KB blocks.
Block number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Address range
$0000-$0FFF
$1000-$1FFF
$2000-$2FFF
$3000-$3FFF
$4000-$4FFF
$5000-$5FFF
$6000-$6FFF
$7000-$7FFF
$8000-$8FFF
$9000-$9FFF
$A000-$AFFF
$B000-$BFFF
$C000-$CFFF
$D000-$DFFF
$E000-$EFFF
$F000-$FFFF
H. Huang Transparency No.5-7
The 68HC11 Microcontroller
Example 5.4 Assign the 68HC11 memory space using a block size of 8KB.
Solution: The 64 KB space can be divided into eight 8KB blocks.
Block number
0
1
2
3
4
5
6
7
Address range
$0000-$1FFF
$2000-$3FFF
$4000-$5FFF
$6000-$7FFF
$8000-$9FFF
$A000-$BFFF
$C000-$DFFF
$E000-$FFFF
Address decoding methods
- partial-decoding: each addressable location responds to more than one address
on the system bus
- full-decoding: each addressable location responds only to one specific address
on the system bus
H. Huang Transparency No.5-8
The 68HC11 Microcontroller
TTL Decoder Chips
- 74138: a 3-to-8 decoder
- 74139: dual 2-to-4 decoder
O0
O1
O2
O3
E1
E2
E3
74138
A2
A1
A0
O4
O5
O6
O7
1Y0
1Y1
1Y2
1Y3
E1
A1
A0
74139
E2
B1
B0
2Y0
2Y1
2Y2
2Y3
Figure 5.1 The 74138 and 74139 decoder chips
H. Huang Transparency No.5-9
The 68HC11 Microcontroller
Example 5.5 Use a full decoding scheme to design an address decoder for a computer
that has the following address space assignments:
SRAM1: $2000-$3FFF
ROM1: $4000-$5FFF
2
E PROM: $6000-$7FFF
SRAM2: $A000-$BFFF
ROM2: $C000-$DFFF
Solution: Each memory component is 8KB. A 3-to-8 decoder 74LS138 can be used as
the address decoder. The highest 3 address bits will be used as the address inputs to the
decoder.
The highest three address bits
for each component are:
The decoder circuit is:
74LS138
SRAM1:
ROM1:
2
E PROM:
SRAM2:
ROM2:
001
010
011
101
110
E1
E2
E
E3
A15
A2
A14
A1
A13
A0
O0
O1
O2
O3
O4
O5
O6
O7
SRAM1_CS
ROM1_CS
EEPROM_CS
SRAM2_CS
ROM2_CS
Figure 5.2 Address decoder design for Example 5.5
H. Huang Transparency No.5-10
The 68HC11 Microcontroller
Example 5.6 Design an address decoder for a 68HC11-based product that has 2KB of
2
external E PROM and 2KB of external SRAM using partial decoding method.
Solution:
-
Use the dual 2-to-4 decoder 74139 as the address decoder.
Divide the 64KB address space of the 68HC11 into four 16 KB blocks.
Use the two highest address signals A15A14 as the address inputs to the decoder.
2
Assign the address space $4000-$7FFF to E PROM.
Assign the address space $8000-$BFFF to SRAM.
E1
E
74LS139
1Y0
unused
1Y1
EEPROM_CS
A15
A1
1Y2
SRAM_CS
A14
A0
1Y3
unused
Figure 5.3 Address decoder for Example 5.6
H. Huang Transparency No.5-11
The 68HC11 Microcontroller
Example 5.7 Make space assignment for an 8-bit microcontroller-based system
with 2 external 8KB SRAM chips, 2 8KB EPROM chips, 1 8KB flash memory chip,
and 8 I/O devices. After making space assignment, design a decoder for it.
Solution: Use a two-level space assignment and two 74138 to perform addressing
decoding. The level one and level two space assignments are:
Block number
Address range
Assigned to
Block number
Address range
Assigned to
0
1
2
3
4
5
6
7
0000H~1FFFH
2000H~3FFFH
4000H~5FFFH
6000H~7FFFH
8000H~9FFFH
A000H~BFFFH
C000H~DFFFH
E000H~FFFFH
not assigned
EPROM2
I/Os
flash memory
SRAM1
SRAM2
not assigned
EPROM1
0
1
2
3
4
5
6
7
4000H~43FFH
4400H~47FFH
4800H~4BFFH
4C00H~4FFFH
5000H~53FFH
5400H~57FFH
5800H~5BFFH
5C00H~5FFFH
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
(a) Level-one memory space assignment
(b) Level-two memory space assignment
Table 5.5 Two-level memory space assignment for Example 5.7
H. Huang Transparency No.5-12
The 68HC11 Microcontroller
The decoding circuitry is as follows:
VCC
ALE
A15
A14
A13
74138
E3
E2
E1
A2
A1
A0
VCC
O0
O1
O2
O3
O4
O5
O6
O7
74138
not used
EP ROM1_CS
flash_CS
E3
E2
E1
SRAM1_CS
A12
not used
A11
A10
EP ROM2_CS
SRAM2_CS
A2
A1
A0
O0
O1
O2
O3
O4
O5
O6
O7
I/O1_CS
I/O2_CS
I/O3_CS
I/O4_CS
I/O5_CS
I/O6_CS
I/O7_CS
I/O8_CS
Figure 5.4 An example of two-level decoding
H. Huang Transparency No.5-13
The 68HC11 Microcontroller
Conventions of Timing Diagrams
- Ideal signals have 0 rise and fall times
1
0
Figure 5.5 Ideal logic level
- A real signal has nonzero rise and fall times
trise
tfall
1
90% V DD
0
10% V DD
Figure 5.6 Real signal
H. Huang Transparency No.5-14
The 68HC11 Microcontroller
- Normal signal representation
1
0
Figure 5.7 Single-signal waveform
1
0
Figure 5.8 Multiple-signal waveform
- Unknown signals (when they are changing) representation
unknown
(a) Single signal
unknown
(b) multiple signals
Figure 5.9 Unknown signals
H. Huang Transparency No.5-15
The 68HC11 Microcontroller
Floating signal representation
- A floating signal is represented by a level half way between logic high and low.
Signal
floating
(a) Single signal
Signals
floating
(b) multiple signals
Figure 5.10 Floating signals
H. Huang Transparency No.5-16
The 68HC11 Microcontroller
Signal causal relationships
Causes
Cause
Signal A
signal A
signal B
Signal B
Result
(a) single cause and single result
Signal C
Result
Signal D
(b) multiple causes and single result
Cause
Signal A
Causes
Signal A
Signal B
signal B
Results
Signal C
Results
Signal C
Signal D
(c) single cause and multiple results
(d) multiple causes and multiple results
Figure 5.11 Causal relationships between signals
H. Huang Transparency No.5-17
The 68HC11 Microcontroller
The 68HC11 Bus Cycle Timing Diagrams
- A 68HC11 external bus cycle can only be performed in expanded mode and controlled
by the E clock signal.
- All read and write bus cycles take one E clock cycles to complete.
- All timing parameters use 20% and 70% of the power supply voltage as reference points.
(Motorola is using this convention)
- Most timing parameters are measured relative to the rising and falling edges of the
E clock signal.
- The phrase before the rising edge of the E clock uses the time when the magnitude of
the E clock signal is 0.2VDD as a reference point.
- The phrase after the rising edge of the E clock uses the time when the magnitude of
the E clock signal is 0.7VDD as a reference point.
- The phrase before the falling edge of the E clock uses the time when the magnitude of
the E clock signal is 0.7VDD as a reference point.
- The phrase after the falling edge of the E clock uses the time when the magnitude of
the E clock signal is 0.2VDD as a reference point.
H. Huang Transparency No.5-18
The 68HC11 Microcontroller
MC68HC11 Read Bus Cycle Timing Diagram
tcyc
PWEH
PWEL
tf
E
tr
R/W
tAH
tAV
tACCE
tDSR
tAH
A15-A8
tMAD
A7/D7-A0/D0
tAVM
tDHR
tACCA
ADDRESS
DATA
tASL
PWASH
AS
tASD
tASED
Figure 5.12 MC68HC11 read bus cycle timing diagram
H. Huang Transparency No.5-19
The 68HC11 Microcontroller
For the 2 MHz E clock signal and the 68HC11 read bus cycle timing diagram
-
-
PWEL is the E clock low pulse width (227 ns)
PWEH is the E clock high pulse width (222 ns)
A15-A8 and R/W signals are valid tAV (94ns) before the rising edge of E clock
A15-A8 and R/W signal remain valid for tAH (30 ns) after the falling edge of E
clock
A7-A0 and D7-D0 are multiplexed on the same PC7-PC0 pins
PC7-PC0 are used as A7-A0 when E clock is low
PC7-PC0 are used as D7-D0 when E clock is high
A7-A0 are valid tAVM (86 ns) before the rising edge of E clock
Read data must be valid for tDSR (30 ns) before the falling edge of E clock so
that 68HC11 can read it correctly
Read data must remain valid for tDHR (0-83ns) after the falling edge of E clock so
that 68HC11 can read it correctly
The falling edge of the AS signal is often used by the address latch to latch A7-A0
and A7-A0 remain valid for tAHL (26 ns) after AS falls
Multiplexed address delay is tMAD (83 ns) after the falling edge of E clock.
H. Huang Transparency No.5-20
The 68HC11 Microcontroller
68HC11 Write Bus Cycle Timing Diagram
tcyc
PWEH
PWEL
tf
E
tr
R/W
tAV
tAH
A15-A8
tMAD
A7/D7-A0/D0
tAVM
tDDW
ADDRESS
tASL
tDHW
DATA
tAHL
PWASH
AS
tASD
tASED
Figure 5.13 MC68HC11 write bus cycle timing diagram
H. Huang Transparency No.5-21
The 68HC11 Microcontroller
For the 2 MHz E clock and the 68HC11 Write bus cycle timing diagram, most
signals are identical to those in read bus cycle timing diagram except
- the 68HC11 drives the data bus when E clock is high
- the 68HC11 drives D7-D0 tDDW (128 ns) after the rising edge of the E clock until
tDHW (33 ns) after the falling edge of the E clock
H. Huang Transparency No.5-22
The 68HC11 Microcontroller
Adding an 8KB SRAM HM6264A to the 68HC11
- The HM6264A has 13 address pins to address each of the 8192 locations on the chip.
- The HM6264A uses × 8 organization.
- There are two chip enable signals: one (CS1) is active low, the other (CS2) is active
high.
- The active low signals WE and OE control the data in and out from the chip.
NC
A12
A7
VCC
A6
A5
A4
A3
A8
A9
A11
OE
A10
A2
A1
A0
I/O1
I/O2
I/O3
VSS
WE
CS2
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
Figure 5.14 Hitachi HM6264A pin assignment
H. Huang Transparency No.5-23
The 68HC11 Microcontroller
The HM6264A Read Cycle Timing Diagrams
There are four access times:
1. Address access time (tAA)
2. CS1 access time (tCO1)
3. CS2 access time (tCO2)
4. OE access time (tOE)
tRC
Address
CS1
CS2
tAA
tCO1
tHZ1
tCO2
tHZ2
tLZ1
tLZ2
tOE
OE
tOHZ
tOLZ
DOUT
Data valid
tOH
Figure 5.15 HM6264A read cycle timing diagram
H. Huang Transparency No.5-24
The 68HC11 Microcontroller
HM6264A Write Cycle Timing diagram
- Write data must be valid for tDW before WE goes high
and remain valid for at least tDH after WE goes high
- the pulse width of WE must be at least tWP
tWC
Address
tWR
tAW
tCW
CS1
tCW
CS2
WE
tWP
tAS
tDW
tDH
DIN
tWHZ
DOUT
tOW
Figure 5.16 HM6264A write cycle timing diagram (OE low)
H. Huang Transparency No.5-25
The 68HC11 Microcontroller
Interfacing the HM6264A-12 with the 2 MHz 68HC11
- Address space assigned to the HM6264A-12 is $4000-$5FFF
- The 74F138, having a propagation delay of 8 ns, is used as the address decoder
- The 74F373, having a propagation delay of 11.5 ns, is used as the low address
latch
- The WE signal is generated by NANDing the E clock and the inverting copy of
R/W.
- The NAND gate has a propagation delay of 15 ns.
- The inverter that is used to invert the R/W signal has a propagation delay of 15 ns
- The circuit connection is in Figure 5.17 of the next slide
H. Huang Transparency No.5-26
The 68HC11 Microcontroller
PB7/A15
74F138
A2
PB6/A14
A1
PB5/A13
A0
E
E3
E2
68HC11
O2
74LS00
AS
AD7-AD0
CS2
CS1
WE
R/W
PB4/A12 PB0/A8
VDD
E1
74LS04
A12-A0
74F373
LE
O7-O0
HM6264A
D7-D0
OE
OE
I/O8 - I/O1
Figure 5.17 Interfacing an 8KB HM6264A to the 68HC11
H. Huang Transparency No.5-27
The 68HC11 Microcontroller
Read Access Timing Analysis
- Timing verification is illustrated using an overlapped 68HC11 and HM6264A timing
diagram in Figure 5.18.
- The time when the data outputs from the HM6264A become valid is determined by the
last asserted input signal -- CS1 in this example
- A15-A8 are valid 94 ns before E rises
- A7-A0 are latched into the 74F373 at 41.5 ns before the rising edge of E clock
The lower address signals A7-A0 are latched by the AS signal
The AS signal falls to 0.7 VDD at 53 ns before the rising edge of E clock
The 74F373 has a propagation of 11.5 ns
A7-A0 is valid at 41.5 ns (53 - 11.5) before E rises
-
WE is high for a read cycle
E3 is the last asserted input signal for 74F138 and hence dictates the output valid time
O2 is asserted 8 ns after the rising edge of E clock
Data output from the HM6264A is valid 128 ns after the rising edge of the E clock or 94 ns
(222 - 128) before the rising edge of the E clock -- this satisfies the 68HC11 read data setup
time (30 ns)
H. Huang Transparency No.5-28
The 68HC11 Microcontroller
222 ns
227 ns
E
R/W
68HC11 A15-A8
timing
30 ns
D7 - D0
A7 - A0
AD7-AD0
0-83 ns
11.5 ns
AS
41.5 ns
A12-A0
8 ns
CS1
HM6264A-12
timing
8 ns
CS2
1
OE
0
WE
1
120 ns
94 ns
8-48 ns
0-40 ns
I/O8 - I/O0
Figure 5.18 Overlapped 68HC11 and HM6264A-12 read timing diagrams
H. Huang Transparency No.5-29
The 68HC11 Microcontroller
- The data hold time is the smaller one (8ns - 43ns) of the following two values:
1. The output hold time from address change (tOH = 10 ns). Address inputs
become invalid 33 ns after the E clock falls. Therefore, it holds up to 43 ns
after E falls.
2. Chip selection CS1 to output in high impedance time tHZ1: 8 - 48 ns.
- The data hold time requirement (0 to 83 ns) is violated. However, the data is held
valid by the capacitance of the printed circuit board until other component drives
the multiplexed address/data bus -- the earliest time is 138 ns after the falling edge
of the E clock (or 53 ns before the rising edge of the next E clock cycle).
- Both the read data setup and hold times are satisfied for the 68HC11.
- The analysis about the PCB capacitance holds data valid follows:
H. Huang Transparency No.5-30
The 68HC11 Microcontroller
Analysis on the duration of the data holding time by PCB capacitance
- Each data pin (D7-D0) and the PCB ground plane form a capacitor
- After memory chip stops driving data pins, the charge across the capacitor leaks away via
1. input leakage current into the 68HC11 data pin (on the order of 10 mA)
2. input leakage current into the memory chip (on the order of 2 mA)
3. other leakage paths on the printed circuit board
- Let
DV = voltage change required for a data bus signal to change from 1 to 0 and
is 2.5V for a 5V power supply
Dt = the time that it takes the voltage across the capacitor to drop by DV
I=
total leakage current
C = the capacitance on the PCB. C is 20 pF/ft for a typical PCB
Assume the data bus signal path is 1 foot long
Then Dt = CDV ÷ I = 20 pF × 2.5 V ÷ 12 mA = 4 ms
Even if the leakage current is ten times larger, the PCB capacitance can still hold the data
for up to 400 ns.
H. Huang Transparency No.5-31
The 68HC11 Microcontroller
Write Bus Cycle Timing Analysis
- Timing verification is illustrated using an overlapped 68HC11 and HM6264A
timing diagram in Figure 5.19.
- The following timing parameters must be satisfied:
1.
2.
3.
4.
5.
6.
7.
write cycle time
write pulse width
address setup time
address valid to end of write
data valid to end of write
data hold time
write recovery time
(120 ns min.)
(70 ns min.)
(0 ns min.)
(85 ns min.)
(50 ns min.)
(0 ns min.)
(0 ns min.)
H. Huang Transparency No.5-32
The 68HC11 Microcontroller
222 ns
2-MHz
E
227 ns
R/W
68HC11
timing
33 ns
A15-A8
33 ns
128 ns
D7-D0
AD7-AD0
109 ns
53 ns
18 ns
AS
336.5 ns
11.5 ns
A12-A0
15 ns
41.5 ns
222 ns
WE
56.5 ns
HM6264A-12
timing
8 ns
8 ns
25 ns
CS1
CS2
1
OE
0
required
50 ns
0 ns
I/O8-I/O0
Figure 5.19 Overlapped 68HC11 and HM6264A-12 write cycle timing diagram
H. Huang Transparency No.5-33
The 68HC11 Microcontroller
Calculation of Write Cycle Time
Write cycle time is the period during which the address inputs to the HM6264A are valid and
is equal to the sum of the following parameters:
- Address inputs (A12-A0) to the HM6264A valid time before the rising edge of the E clock
(A7-A0 become valid later than A12-A8).
- E clock rise time (20 ns at 2 MHz)
- Pulse width when the E clock is high
- E clock fall time
- Address inputs hold time after the E clock falls (33 ns). (A12-A8 become invalid earlier
than A7-A0).
tWC = 41.5 ns + tr + PWEH + tf + tAH = 336.5 ns (120 ns min. required)
tr
PWEH
tf
E
94 ns
33 ns
A12-A8
174 ns
41.5 ns
A7-A0
Write cycle time
Figure 5.20 Calculation of write cycle time
H. Huang Transparency No.5-34
The 68HC11 Microcontroller
Calculation of Write Pulse Width (WE)
Since the WE signal is the NAND function of the R/W and E clock, the width is
equal to the high pulse width of the E clock and is equal to 222 ns (70 ns is required).
H. Huang Transparency No.5-35
The 68HC11 Microcontroller
Calculation of Address Setup Time
The address setup time is measured from the moment that all address inputs are valid until
the write enable signal goes low. A12-A8 become valid 94 ns before the rising edge of E
clock and A7-A0 become valid 41.5 ns before the rising edge of the E clock. The WE signal
becomes valid 15 ns after the rising edge of the E clock due to the propagation delay of the
NAND gate. The address setup time is calculated as follows:
tAS = 41.5 ns + tr + 15 ns = 76.5 ns
The calculated value satisfies the requirement (0 ns min.).
tr
E
15 ns
WE
41.5 ns
A12-A0
Address
setup time
Figure 5.21 Calculation of the address setup time
H. Huang Transparency No.5-36
The 68HC11 Microcontroller
Time from Address Valid till the End of Write
This parameter is measured from the moment when all address inputs are valid until the write
enable signal becomes invalid. This parameter is the sum of the following terms:
1.
2.
3.
4.
5.
the lead time from address signals become valid to the rising edge of the E clock (41.5 ns)
the E clock rise time (20 ns)
the E clock high pulse width (222 ns)
the E clock fall time (20 ns)
the propagation delay of the NAND gate (15 ns)
tAW = 41.5 ns + 20 ns + 222 ns + 20 ns + 15 ns = 318.5 ns (85 ns min. required)
PWEH
tf
E
15 ns
WE
41.5 ns
A12-A0
Address valid to end of write
Figure 5.22 Calculation of address valid to end of write
H. Huang Transparency No.5-37
The 68HC11 Microcontroller
Calculation of Write Data Setup Times
The write data setup time (tDW) is measured from the moment that the 68HC11 drives
the data on the data bus until the WE signal goes high (50 ns min. required).
tDW = PWEH - t DDW + delay of the NAND gate = 222 ns - 128 ns + 15 ns = 109 ns
222 ns
E
D7-D0
WE
tDDW
write data
setup time
15 ns
H. Huang Transparency No.5-38
The 68HC11 Microcontroller
Write Data Hold Time (tDH)Calculation
- tDH is measured from the moment when WE becomes invalid until D7-D0 become invalid.
tDH = tDHW - NAND delay = 33 ns - 15 ns = 18 ns (> 0 ns)
E
15 ns
WE
tDH
tDHW = 33 ns
D7-D0
H. Huang Transparency No.5-39
The 68HC11 Microcontroller
Calculation of Write Recovery Time
Write recovery time (tWR) is measured from the moment that the earliest chip select
signal (CS1 in this example) becomes invalid until the moment that the address signals
are invalid. The calculation of tWR is illustrated in Figure 5.23.
E
8 ns
CS1
33 ns
A12-A0
Write recovery
time
Figure 5.23 Calculation of write recovery time
All timing parameters have been verified to satisfy the requirements.
H. Huang Transparency No.5-40