LPCXpresso Workshop
B. Vasu Dev
vasu@easyarm.com
Enabling the ARM Learning in INDIA
AGENDA

ARM Introduction

Development Tools Setup

Hardware Detail and Schematics

ARM Cortex Programming

Using CMSIS ( Create New Projects for Cortex )

Application Development
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ARM INTRODUCTION
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What is ARM?
The ARM is a 32-bit reduced instruction set
computer (RISC) instruction set architecture (ISA)
developed by ARM Holdings.
ARM also known as Advance RISC Machine
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Why ARM?
Simplicity is the key philosophy behind the ARM design
RISC machine with small instruction set and consequently a small gate count.
High Performance
Low power consumption
Small amount of silicon die area.
Open Source Development Tools
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Where is ARM?
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History
Founded in November 1990
Spun out of Acorn Computers
Designs the ARM range of RISC processor cores
Licenses ARM core designs to semiconductor partners who
fabricate and sell to their customers.
ARM does not fabricate silicon itself
Also develop technologies to assist with the design-in of the
ARM architecture
Software tools, boards, debug hardware, application
software, bus architectures, peripherals etc
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ARM Core Family
Application
Cores
Embedded
Cores
Secure Cores
ARM720T
ARM7EJ-S
SecureCore
SC100
ARM920T
ARM7TDMI
SecureCore
SC110
ARM922T
ARM7TDMI-S
SecurCore
SC200
ARM926EJ-S
ARM946E-S
SecurCore
SC210
ARM1020E
ARM966E-S
ARM1022
ARM968E-S
ARM1026EJ-S
ARM996HS
ARM11 MPCore
ARM1026EJ-S
ARM1136J(F)-S
ARM1156T2(F)-S
ARM1176JZ(F)-S
ARM Cortex-M0
ARM Cortex-A8
ARM Cortex-M1
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ARM Core Family
T: Thumb
D: On-chip debug support
M: Enhanced multiplier
I: Embedded ICE hardware
T2: Thumb-2
S: Synthesizable code
E: Enhanced DSP instruction set
J: JAVA support, Jazelle
Z: Should be TrustZone?
F: Floating point unit
H: Handshake, clockless design for synchronous or
asynchronous design
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ARM Core Family
ARM processor core + cache + MMU = ARM CPU cores
ARM6 → ARM7
– 3-stage pipeline
– Keep its instructions and data in the same memory system
– Thumb 16-bit compressed instruction set
– On-chip Debug support, enabling the processor to halt in response to a
debug request
– Enhanced Multiplier, 64-bit result
– Embedded ICE hardware, give on-chip breakpoint and watchpoint
support
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ARM Core Family
ARM8
→ ARM9 → ARM10
ARM9
– 5-stage pipeline (130 MHz or 200MHz)
– Using separate instruction and data memory ports
ARM 10 (1998. Oct.)
– High performance, 300 MHz
– Multimedia digital consumer applications
– Optional vector floating-point unit
ARM11 (2002 Q4)
–8-stage pipeline
– Addresses a broad range of applications in the wireless, consumer,
networking and automotive segments
–Support media accelerating extension instructions
–Can achieve 1GHz & Support AXI
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ARM Architecture Versions
Version 1
– The first ARM processor, developed at Acorn Computers Limited 1983-1985
– 26-bit address, no multiply or coprocessor support
Version 2
– Sold in volume in the Acorn Archimedes and A3000 products
– 26-bit addressing, including 32-bit result multiply and coprocessor
Version 2a
– Coprocessor 15 as the system control coprocessor to manageCache
– Add the atomic load store (SWP) instruction
Version 3
– First ARM processor designed by ARM Limited (1990)
– ARM6 (macro cell), ARM60 (stand-alone processor)
ARM600 (an integrated CPU with on-chip cache, MMU, write buffer)
ARM610 (used in Apple Newton)
– 32-bit addressing, separate CPSR and SPSRs
– Add the undefined and abort modes to allow coprocessor emulation and virtual
memory support in supervisor mode
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ARM Architecture Versions
Version 3M
– Introduce the signed and unsigned multiply and multiplyaccumulate
instructions that generate the full 64-bit result
Version 4
– Add the signed, unsigned half-word and signed byte load and store instructions
– Reserve some of SWI space for architecturally defined operation
– System mode is introduced
Version 4T
– 16-bit Thumb compressed form of the instruction set is introduced
Version 5T
– Introduced recently, a superset of version 4T adding the BLX, CLZ and BRK
instructions
Version 5TE
Add the signal processing instruction set extension
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ARM Architecture Versions
Version 6
– Media processing extensions (SIMD)
• 2x faster MPEG4 encode/decode
• 2x faster audio DSP
– Improved cache architecture
• Physically addressed caches
• Reduction in cache flush/refill
• Reduced overhead in context switches
– Improved exception and interrupt handling
• Important for improving performance in real-time tasks
– Unaligned and mixed-endian data support
• Simpler data sharing, application porting and saves memory
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ARM Architecture Versions
Version7
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Development of the
ARM Architecture
1
2
Halfword
and signed
halfword /
byte support
System
mode
4
SA-110
3
Early ARM
architectures
ARM7TDMI
ARM720T
5T
E
CLZ
SA-1110
Thumb
instruction
set
Improved
ARM/Thumb
Interworking
Saturated maths
DSP multiplyaccumulate
instructions
ARM1020E
4T
ARM9TDMI
ARM940T
Jazelle
5T
EJ
Java bytecode
execution
ARM9EJ-S
ARM926EJ-S
ARM7EJ-S
ARM1026EJ-S
SIMD Instructions
6
Multi-processing
XScale
ARM9E-S
ARM966E-S
V6 Memory
architecture (VMSA)
Unaligned data
support
ARM1136EJ-S
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ARM Cores & Arch Ver
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ARM CORTEX
The ARM Cortex family includes processors based on the three distinct profiles
of the ARMv7 architecture.
The A profile for sophisticated, high-end applications running open and
complex operating systems
The R profile for real-time systems
The M profile optimized for cost-sensitive and microcontroller applications
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Why ARM Cortex ?
1. Developed for embedded systems
2. High performance with low dynamic power
Harvard Architecture
30% performance improvement over ARM7TDMI
Single-cycle multiply and hardware division
Atomic Bit manipulation
Best code density
Thumb-2 brings 32-bit performance with 16-bit code density
Deterministic
Interrupt controller inside the core, 6-cycle latency 6 CPU cycles wake up time from Low
Power Mode
Improved debug features
Serial Wire debug and JTAG
2 data watchpoints, 8 hardware breakpoints
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ARM Cortex PipeLine
Cortex CPU executes instruction in single cycle. And this is
achieved with the three stage pipeline.
-
One instruction being executed the next is being deecoded
and the third is being fetch from the memory.
-
Speculative fetch is performed for the branch instruction so
both conditional instructions are available for execution
without any performance hit..
-
The worst case is the indirect branch where the speculative
fetch can not be made and need to flush the pipeline.
Pipeline
is the key to the overall performance of the Cortex
CPU.
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Three Stage Pipeline
The pipeline is used to overcome the delay caused by instruction fetching and
decoding before execution.
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Three Stage Pipeline
Fetch
– The instruction is fetched from memory and placed in the instruction pipeline
Decode
– The instruction is decoded and the data path control signals prepared for the next
cycle
Execute
– The register bank is read, an operand shifted, the ALU result generated and
written back into destination register
The three stage pipeline has hardware independent stages that execute one
instruction while decoding a second and fetching a third.
PC runs 8 bytes ahead of current execution instruction since it holds the address of
the fetching instruction but not the current execution instruction.
0x4000
LDR PC,[PC,#4] results PC => 0x400C not 0x4004
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Processor Modes
Register R13-R15 having special function within the
Cortex CPU.

Register R13 allows the CPU to operates in
Two Operating modes[Thread & Handler].


Each mode having it's own stack and space.

Two stack is called Main stack and process stack.
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Registers
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Exception Handling
When an exception occurs, the ARM:

Copies CPSR into SPSR_<mode>

Sets appropriate CPSR bits

Change to ARM state

Change to exception mode

Disable interrupts (if appropriate)

Stores the return address in LR_<mode>

Sets PC to vector address
To return, exception handler needs to:

Restore CPSR from SPSR_<mode>

Restore PC from LR_<mode>
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Exception Handling
The NVIC supports nesting (stacking) of interrupts, allowing an interrupt to be serviced earlier by
exerting higher priority. It also supports dynamic reprioritisation of interrupts. Priority levels can be
changed by software during run time.
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Instruction Set
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Instruction Set
ARM’s implement two types of instruction sets

32-bit ARM Instruction Set

16-bit Thumb Instruction Set
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ARM (32bit) IS
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ARM (32bit) IS

Every ARM (32 bit) instruction is conditionally executed.

The top four bits are ANDed with the CPSR condition codes, If they do not matched the
instruction is executed as NOP
The AL condition is used to execute the instruction irrespective of the value of the condition

code flags.

By default, data processing instructions do not affect the condition code flags but the flags
can be optionally set by using “S”. Ex: SUBS r1,r1,#1
Conditional Execution improves code density and performance by reducing the number of

forward branch instructions.
Normal
CMP r3,#0
BEQ skip
ADD r0,r1,r2
skip
Conditional
CMP r3,#0
ADDNE r0,r1,r2
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Condition Codes
Each ARM (32bit) Instruction can be prefixed with any of the
following conditional code.
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Condition Codes
Examples:
Set the flags, then use various condition codes
if (a==0) x=0;
if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1
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Branch instructions
B Basic branch instruction used to jump forward or backward of up to 32 MB.
BL Branch and Link instruction jumps to the destination and stores a return
address in R14 (Link Register).
BX, BLX Branch, Brach Link and Exchange.
This swaps the instruction sets from ARM to THUMB and vice versa
while jumping.
BXJ Branch and change to Jazelle state.
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Data Processing Inst.
Arithmetic: ADD
Logical:
Comparisons:
Data movement:
ADC
AND
CMP
MOV
SUB SBC RSB RSC
ORR EOR BIC
CMN TST TEQ
MVN
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Multiply Instructions
MUL, MLA
MULL, MLAL
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Data Transfer Inst.
Simple Data Transfer Inst.
LDR
STR
LDRB
STRB
LDRH
STRH
LDRSB
LDRSH
Word
Byte
Halfword
Signed byte load
Signed halfword load
Load / Store Multiple Registers
LDM
STM
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Swap Instruction
Are also called as semaphore instructions
SWP R12, R10, [R9]
; load R12 from address R9 and
; store R10 to address R9
SWPB R3, R4, [R8]
; load byte to R3 from address R8 and
; store byte from R4 to address R8
SWP R1, R1, [R2]
; Exchange value in R1 and address in R2
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Miscellaneous Inst.
Software Interrupt
Causes an exception trap to the SWI hardware vector
The SWI handler can examine the SWI number to decide what operation has been
requested.
By using the SWI mechanism, an operating system can implement a set of
privileged operations which applications running in user mode can request.
Ex. SWI #3
PSR Transfer Instructions
MRS and MSR allow contents of CPSR / SPSR to be transferred to / from a
general purpose register.
MRS{<cond>} Rd,<psr>
; Rd = <psr>
MSR{<cond>} <psr[_fields]>,Rm
; <psr[_fields]> = Rm
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2. Development Tools Set Up
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Development Tools Used.

LPCXpresso is development platform from NXP.

Eclipse based IDE, A GNU C Compiler,

A Linker and Libraries and GDB debugger.

Emulator.
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LPCExpresso setup
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LPCExpresso setup
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LPCExpresso setup
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Eclipse IDE
Eclipse IDE
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Work Space
Options used for
Project Development Source Code
Debug Mode
Debug and Programming
1.
Hardware and Schematics
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LPC1343
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NGX Base Board
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NGX Base Board
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H/W- NGX_NXP
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Hardware Details - Base Board

Hardware Features
- 2x16 LCD with Contrast control and back light.
- SD card connector.
- Power Jack.
- Reset Button.
- ISP Button.
- External Interrupt Button.
- Buzzer, Audio Jack.
- Ethernet Connector
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Hardware Details - Base Board
- 20 Pin JTAG Connector
- PS/2
- VGA
- Serial Connector 0
- Serial Connector 1
- Preset for ADC
- EEPROM.
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LPC1343 and Peripheral registers
LPC1343 Features:
- ARM Cortex Processor Running up to 72 MHz.
- 32Kb on chip flash programming memory.
- 8Kb SRAM
- Selectable boot up : UART or USB
- On chip drivers for MSC( Mass Storage Device) and
HID( Human Interface Device).
- I2C, SPI, UART, WDT, 32 bit Counter/Timer, USB.
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LPC1343 Block Diagram
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LPC1343 GPIO Peripherals
- LPC1343's GPIOs
GPIO_PORT0 → GPIO0_0 to GPIO0_11
GPIO_PORT1 → GPIO1_0 to GPIO1_11
GPIO_PORT2 → GPIO2_0 to GPIO2_11
GPIO_PORT3 → GPIO3_0 to GPIO3_3
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LPC1343 GPIO Features
- LPC1343 GPIOs
- GPIO pin can be configured as input or output by the
software.
- Each individual Pin can serve as an edge or level sensitive
interrupt request.
- Interrupt can be configured on single falling or rising edges.
- Level sensitive interrupt Pin can be HIGH or LOW active.
- All GPIO Pins inputs by default.
- Reading or writing of data registers are masked by address
bit 13:2 .
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LPC1343 GPIO Features
Name
Access
Description
Address
0x0000 to
GPIOnData
R/W
Portn data address masking register
0x3FF8
GPIOnData
R/W
Portn data address masking register
0x3FFC
GPIOnDIR
R/W
Data direction register for port n
0x8000
GPIOnIS
R/W
Interrupt Sense register for port n
0x8004
GPIOnIBE
R/W
Interrupt both edges register for port n
0x8008
GPIOnIEV
R/W
Interrupt event register for Port n
0x800C
GPIOnIE
R/W
Interrupt mask register for Port n
0x8010
GPIOnRIS
R
Raw interrupt status register for Port n
0x8014
GPIOnMIS
R
Masked Interrupt status register for Port n 0x8018
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LPC1343 GPIO Features
- GPIOnDIR : Pin 0 to 11, 12-31 reserved
0 – configured as input,
1- configured as Output
- GPIOnIS : Pin 0 to 11,12-31 reserved
0 – interrupt on Pin edge sensitive.
1 – interrupt on Pin Level sensitive
- GPIOnIBE : Pin 0 to 11, 12-31 reserved
0 – Interrupt on Pin is controlled through
register GPIOnIEV
1 – Both edges on Pin triggerEnabling
as interrupt.
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LPC1343 GPIO Features
- GPIOnIEV : Pin 0 to 11, 12-31 reserved
0 – falling edges or low level on pin trigger as interrupt.
1 – rising edges or high level on pin trigger as interrupt.
- GPIOnIE : Pin 0 to 11,12-31 reserved
0 – disables interrupt on that pin
1 – Enable interrupt on that pin.
- GPIOnRIS : Pin 0 to 11, 12-31 reserved
0 – No interrupt on Pin.
1 – Interrupt requirement met on Pin.
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LPC1343 GPIO Features
- GPIOnMIS : Pin 0 to 11, 12-31 reserved
0 – No interrupt or interrupt mask on Pin
1 – .interrupt on Pin
- GPIOnIC : Pin 0 to 11,12-31 reserved
0 – No effect
1 – Clear edge detection logic for Pin
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LPC1343 GPIO Programming
Step1: Configure pin as gpio( )
Step2: Configure the direction of pin(out)( ) ==>DIR
1 == >OUT 0 == > INPUT Default[input]
Step3: Make the pin High( ) ==>DATA
Step4: Make the pin Low( ) ==>DATA
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LPC1343 Timer/Counter
There are two 16-bit Timers and two 32-bit Timers.
Features :
• Counter or timer operation.
• Two 16-bit counter/timers with a programmable 16-bit prescaler.
• One 16-bit capture channel that can take a snapshot of the timer
value when an input signal transitions. A capture event may also
optionally generate an interrupt.
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LPC1343 Timer/Counter Registers
Name
Access
Description
Address
TMR16B0IR
R/W
The IR can be written to Clear Interrupts.
0x0000
TMR16B0TCR
R/W
The TCR is used for Timer/Counter
function
0x0004
TMR16B0TC
R/W
TC can be controlled through the TCR
0x0008
TMR16B0PR
R/W
Prescale register.
0x000C
TMR16B0PC
R/W
Prescale Counter
0x0010
TMR16B0MCR
R/W
Match Control Register
0x0014
TMR16B0MR0
R/W
Match Register 0
0x0018
TMR16B0MR1
R/W
Match Register 1
0x001C
TMR16B0MR2
R/W
Match Register 2
0x0020
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LPC1343 Timer/Counter Registers
Name
Access
Description
Address
TMR16B0CCR
R/W
Capture Control Register.
0x0028
TMR16B0CR0
RO
Capture Register 0
0x002C
TMR16B0EMR
R/W
External Match Register
0x003C
TMR16B0CTCR
R/W
Count Control Register.
0x0070
TMR16B0PWMC
R/W
PWM Control Register
0x0074
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LPC1343 Timer Programming
1)
Initialize the Timer.
timer16Init()
LPC_TMR32B0->MR0 = TimerInterval;
LPC_TMR32B0->MCR = 3;
/* Interrupt and Reset on MR0 */
2)
Enable the Timer.
timer16Enable()
LPC_TMR32B0->TCR = 1;
2)
Produce the appropriate delay.
timer16DelayTicks() or timer16DelayUS()
LPC_TMR32B0->TCR = 0x02;
/* reset timer */
LPC_TMR32B0->PR = 0x00;
/* set prescaler to zero */
LPC_TMR32B0->MR0 = delayInMs * ((SystemFrequency/LPC_SYSCON->SYSAHBCLKDIV) / 1000);
LPC_TMR32B0->IR = 0xff;
/* reset all interrrupts */
LPC_TMR32B0->MCR = 0x04;
/* stop timer on match */
LPC_TMR32B0->TCR = 0x01;
/* start timer */
/* wait until delay time has elapsed */
while (LPC_TMR32B0->TCR & 0x01);
}
4)
4)
Disable the Timer.
timer16Disable()
LPC_TMR32B0->TCR = 0;
Reset the Timer.
timer16Reset()
regVal = LPC_TMR32B0->TCR;
regVal |= 0x02;
LPC_TMR32B0->TCR = regVal;
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LPC1343 UART Registers
Address
Name
Access
Description
Offset
U0RBR
RO
Receive Buffer Register. Contain Next
receive char
0x0000
U0THR
WO
Transmit holding register ( next char
transmit )
0x0000
U0DLL
R/W
Divisor Latch LSB
0x0000
U0DLM
R/W
Divisor Latch MSB
0x0004
U0IER
R/W
Interrupt Enable Register
0x0004
U0IIR
RO
Interrupt ID Register
0x0008
U0FCR
WO
FIFO Control Register
0x0008
U0LCR
W/R
Line Control Register
0x000C
U0MCR
W/R
Modem Control Register
0x0010
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LPC1343 UART Registers
Address
Name
Access
Description
Offset
U0MSR
RO
Modem Status Register
0x0018
U0SCR
R/W
Scratch Pad Register
0x001C
U0ACR
R/W
Auto Baud Control Register
0x0020
U0FDR
R/W
Fractional Divisor Register
0x0028
U0TER
R/W
Transmit Enable Register
0x0030
U0RS485CTRL
R/W
RS485 Control Mode
0x004C
U0ADRMATCH
R/W
RS485 Address Match
0x0050
U0RS485DLY
R/W
RS485 Direction Control Delay
0x0054
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LPC1343 I2C Features
• Standard I2C-compliant bus interfaces may be configured as Master,
Slave, or Master/Slave.
• Arbitration is handled between simultaneously transmitting masters
without corruption of serial data on the bus.
• Programmable clock allows adjustment of I2C transfer rates.
• Data transfer is bidirectional between masters and slaves.
• Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus.
• Serial clock synchronization is used as a handshake mechanism to
suspend and resume serial transfer.
• Supports Fast-mode Plus.
• Optional recognition of up to four distinct slave addresses.
• Monitor mode allows observing all I2C-bus traffic, regardless of
slave address.
• I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus contains a standard I2C-compliant bus interface with two
pins.
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LPC1343 I2C Registers
Address
Name
Access
Description
Offset
I2C0CONSET
R/W
I2C Control Set Register
0x0000
I2C0STAT
RO
I2C status Register
0x0004
I2C0DAT
R/W
I2C Data Register
0x0008
I2C0ADR0
R/W
I2C Slave Address Register 0
0x000C
I2C0SCLH
R/W
SCH Duty Cycle Register High Half Word
0x0010
I2C0SCLL
R/W
SCL Duty Cycle Register Low Half Word
0x0014
I2C0CONCLR
WO
I2C Control Clear Register
0x0018
I2C0MMCTRL
R/W
Monitor Mode Control Register
0x001C
I2C0ADR1
R/W
I2C Slave Address Register 1
0x0020
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LPC1343 I2C Registers
Address
Name
Access
Description
Offset
I2C0ADR3
R/W
I2C Slave Address Register 3
0x0028
I2C0DATA_BUFFER RO
I2C Data Buffer Register
0x002C
I2C0MASK0
R/W
I2C Slave Address Mask Register 0
0x0030
I2C0MASK1
R/W
I2C Slave Address Mask Register 1
0x0034
I2C0MASK2
R/W
I2C Slave Address Mask Register 2
0x0038
I2C0MASK3
R/W
I2C Slave Address Mask Register 3
0x003C
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LPC1343 ADC Features
I2C Control Set register
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LPC1343 ADC Features
• Input multiplexing among 8 pins.
• 10-bit successive approximation Analog-to-Digital Converter (ADC).
• Power-down mode.
• Measurement range 0 to 3.6 V. Do not exceed the VDD voltage level.
• 10-bit conversion time ≥ 2.44 μs.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
• Individual result registers for each A/D channel to reduce interrupt
overhead.
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LPC1343 ADC Registers
Address
Name
Access
Description
Offset
AD0CR
R/W
A/D Control Register
0x0000
AD0GDR
R/W
A/D Global Data Register
0x0004
AD0INTEN
R/W
A/D Interrupt Enable Register
0x000C
AD0DR0
R/W
A/D Channel 0 Data Register
0x0010
AD0DR1
R/W
A/D Channel 1 Data Register
0x0014
AD0DR2
R/W
A/D Channel 2 Data Register
0x0018
AD0DR3
R/W
A/D Channel 3 Data Register
0x001C
AD0DR4
R/W
A/D Channel 4 Data Register
0x0020
AD0DR5
R/W
AD0DR6
R/W
A/D Channel 5 Data Register
0x0024
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A/D Channel 6 Data Register
0x0028
LPC1343 ADC Registers
Address
Name
Access
Description
Offset
AD0DR7
R/W
A/D Channel 7 Data Register
0x002C
AD0STAT
RO
A/D Status Register
0x0030
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in INDIA
LPC1343 ADC Programming
Initialize the ADC.
adcInit()
/* Disable Power down bit to the ADC block. */
LPC_SYSCON->PDRUNCFG &= ~(0x1<<4);
/* Enable AHB clock to the ADC. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<13)
LPC_ADC->CR = ((SystemCoreClock/LPC_SYSCON>SYSAHBCLKDIV)/ADC_Clk-1)<<8;
Read the particular ADC channel.
adcRead()
LPC_ADC->CR |= (1 << 24) | (1 << channelNum);
/* switch channel,start A/D convert */
Store the result in a variable or buffer.
Variable = LPC_ADC-> DR5
Enabling the ARM Learning in INDIA
LPC1343 USB Registers
Address
Name
Access
Description
Offset
USBDevIntSt
RO
USB Device interrupt Status
0x0000
USBDevIntEn
R/W
USB Device Interrupt Enable
0x0004
USBDevIntClr
WO
USB Device Interrupt Clear
0x0008
USBDevIntSet
WO
USB Device Interrupt Set.
0x000C
USBCmdCode
WO
USB Command Code
0x0010
USBCmdData
RO
USB Command Data
0x0014
USBRxData
RO
USB Receive Data
0x0018
USBTxData
WO
USB Transmit Data
0x001C
USBRxPLen
RO
USB Receive Packet Length
0x0020
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LPC1343 USB Registers
Address
Name
Access
Description
Offset
USBCtrl
R/W
USB Control
0x0028
USBDevFIQSel
WO
USB Device FIQ Select
0x002C
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LPC1343 SSP Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National
Semiconductor Microwire buses.
• Synchronous Serial Communication.
• Supports master or slave operation.
• Eight frame FIFOs for both transmit and receive.
• 4-bit to 16-bit frame.
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LPC1343 SSP Registers
Address
Name
Access
Description
Offset
SSP0CR0
R/W
Control Register 0
0x0000
SSP0CR1
R/W
Control Register 1
0x0004
SSP0DR
R/W
Data Register
0x0008
SSP0SR
RO
Status Register
0x000C
SSP0CPSR
R/W
Clock Prescale Register
0x0010
SSP0IMSC
R/W
Interrupt Mask Set and Clear Register
0x0014
SSP0RIS
RO
Raw Interrupt Status Register
0x0018
SSP0MIS
RO
Mask Interrupt Status Register
0x001C
SSP0ICR
WO
SSPICR Interrupt Clear Register
0x0020
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