Introduction to Embedded Systems
Rabie A. Ramadan
rabieramadan@gmail.com
http://www.rabieramadan.org/classes/2014/embedded/
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Real Time Synchronization
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Required when tasks are not independent and need to share
information and synchronize
If two tasks want to access the same data, semaphores are
used to ensure non-simultaneous access.
Potential Issues
• Priority Inversion – A situation in which a higher priority job is
blocked by lower priority jobs for an indefinite period of time
• Chain Blocking – A situation in which more than two resources
are available and a high priority task is blocked off from both
because of two or more lower priority tasks holding locks on
one or both of the resources.
Priority Inversions

Low priority task holds resource that prevents execution of
higher priority tasks.
- Task L acquires lock
- Task H needs resource, but is blocked by Task L, so Task L is
allowed to execute
- Task M preempts Task L, because it is higher priority
- Thus Task M delays Task L, which delays Task H
Priority Inheritance Protocol
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•
PIP eliminates priority inversion problem
The algorithm will increase the priority of a task to the
maximum priority of any task waiting for any resource the
task has a resource lock on
- i.e. if a lower priority task L has a lock on a resource
required by a higher priority task H, then the priority of the
lower task is increased to the priority of the higher task
- Once the lock is released the task resumes back its
original priority.
Priority Ceiling Protocol
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Each resource is assigned a priority ceiling, which is a priority equal
to the highest priority of any task which may lock the resource.
PCP eliminates chain blocking which considers the use of more
than one resource or semaphore
A task can acquire a lock on resource S only if no other task holds
a lock on resource R. Thus higher priority tasks will not be blocked
through both S and R
If a high priority task is blocked through a resource, then the task
holding that resource gets the priority of the high priority task. Once
the resource is released, the priority is reset back to its original
Priority inversion - A scheduling scenario where a high priority
task is indirectly preempted by a medium priority task
because it is blocked waiting for a shared resource.
Priority inheritance - A scheduling policy that attempts to solve
the problem of priority inversion as follows:
whenever a high priority task has to wait for some
resource, shared with an executing low priority task, the low
priority task is temporarily assigned the priority of the
highest waiting priority task for the duration of its own use
of the shared resource. This strategy prevents medium
priority tasks from preempting it. When the shared
resource is released the low priority task continues to
execute at its original priority level.
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Priority ceiling inheritance - An enhancement of the
priority inheritance policy.
A priority ceiling is defined for each resource. The
scheduling policy is the same as for priority inheritance
except that tasks can only acquire a resource if their
static priority is higher than the ceiling of any
currently locked resource (excluding that it has already
blocked itself).
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Timers and Interrupts
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The tight-coupling between the computer and external
world distinguishes an embedded system from a
regular computer system.
synchronization between the executing software and
its external environment is critical for the success of an
embedded system.
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Definition of ‘Interrupt’
Event that disrupts the normal
execution of a program and causes the
execution of special instructions
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Interrupts
Interrupt
Program
time t
UBC 104 Embedded Systems
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Interrupts
Interrupt
Program
Program
Interrupt Service Routine
time t
UBC 104 Embedded Systems
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Interrupts
Interrupt
Program
mov R1, cent
Program
Save
Context
eg push R1
Interrupt
Service
Routine
Restore
Context
mul R1, 9
eg pop R1
time t
UBC 104 Embedded Systems
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Hardware event is called a trigger.
The hardware event can either be a busy to ready transition
in an external I/O device (like the UART input/output) or an
internal event (like bus fault, memory fault, or a periodic
timer).
The execution of the interrupt service routine is called a
background thread.
killed when the interrupt service routine returns from
interrupt
A new thread is created for each interrupt request.
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Threads share access to I/O devices, system
resources, and global variables, while processes have
separate global variables and system resources.
Processes do not share I/O devices.
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Exception and Interrupt Handling in
ARM as a Case Study
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Interrupts vs. polling
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polling mechanism wastes the CPU time in looping
forever checking some flags to know that the event
occurred.
we have nowadays systems with more than one interrupt
source.
We may need priorities to be assigned to different
Events
Interrupt is the best way to handle events
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ARM modes of operation
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Internally has 7 different modes of operation
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User mode: used for normal program execution state
Fast Interrupt Request (FIQ) mode: This mode is used for interrupts
requiring fast response and low latency.
•
like for example data transfer with DMA
Interrupt Request (IRQ) mode: used for general interrupt services
Abort mode: selected when data or instruction fetch is aborted
System mode: Operating system privilege mode for users
Undefined mode: When undefined instruction is fetched
Supervisor mode: used when operating system support is needed where
it works as protected mode
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Protected Vs. Original Mode
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Protected mode differed from the original mode:
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Later dubbed “real mode”,
Areas of memory could be physically isolated by the processor itself to
prevent illegal writes to other programs running in memory at the same
time.
Prior to protected mode, multiple programs could be running in memory at
the same time, but any program could access any area of memory and,
therefore, if malicious or errant, for example, could take down the entire
system.
Isolates that possibility by allowing the operating system (OS) to dictate
where each program should run.
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ARM Modes of Operation
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ARM Register set
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Register structure in ARM depends on the mode of operation.
There are 16 (32-bit) registers named from R0 to R15 in ARM
mode (usr).
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Registers R0 to R12 are general purpose registers,
R13 is stack pointer (SP),
R14 is subroutine link register
R15 is program counter (PC).
R16 is the current program status register (CPSR) and it plays a main role
in the process of switching between modes – eg. the current processor mode
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Banked Registers
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Some registers are available with the same name but as
another physical register in memory which is called
(banked)
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Decreases the effort needed when context switching is required
The new mode has its own physical register space and no need to
store the old mode’s register values
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Register Organization in ARM
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ARM Exceptions
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Exception : any condition that needs to halt normal
execution of the instructions.
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State of resetting ARM core,
Failure of fetching instructions or memory access
There is always software associated with each exception,
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Exception handler.
Each of the ARM exceptions causes the ARM core to
enter a certain mode automatically.
Ex.
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Vector Table
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It is a table of instructions that the ARM core branches to when an
exception is raised.
These instructions are places in a specific part in memory and its address is
related to the exception type
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Exception priorities
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Since exceptions can occur simultaneously
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We may have more than one exception raised at the same
time,
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the processor has to have a priority for each exception so
it can decide which of the currently raised exceptions is
more important
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Exception priorities

various exceptions that occur on the ARM and their
associated priorities.
Both are caused by
an instruction
entering the
execution stage of
the ARM instruction
pipeline
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Link Register Offset
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This register is used to return the PC to the appropriate
place in the interrupted task
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not always the old PC value.
It is modified depending on the type of exception.
In the case of IRQ exception, the link register is pointing
initially to the last executed instruction
In data abort exception , the exception is handled and the
PC should point to the same instruction again to retry
accessing the same memory location again.
Data Exception : processor can fetch and store data or they
can refuse to do either.
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Entering and exiting an exception
handler
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Save the address of the next instruction in the appropriate
Link Register (LR).
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Copy Current Program Status Register (CPSR) to the Saved
Program Status Register (SPSR) of new mode.
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Change the mode by modifying bits in CPSR.
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Fetch next instruction from the vector table.
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Leaving exception handler
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Move the Link Register LR (minus an offset) to the PC.
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Copy SPSR back to CPSR, this will automatically changes
the mode back to the previous one.
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Clear the interrupt disable flags (if they were set).
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Interrupts
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Interrupts
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Interrupts
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Interrupt handling schemes
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Interrupt handling schemes
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Interrupt handling schemes
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Interrupt handling schemes
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In class work
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