VHDL
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VHDL
FCU, Department of ECE , IC Design Research Lab.
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Introduction
數位電路的設計方法，在早期由於電路比較簡單，
且電路合成的工具較不完整，早期都是使用gatelevel的方式用圖形介面，就所需之邏輯閘、正反
器一個個畫在電路圖上。
需要花相當的時間設計的輸入
由於邏輯閘相當多，會增加出錯機會即將來
維護上的困難。
Very High Speed ICs Hardware Description
Language (VHDL)
FCU, Department of ECE , IC Design Research Lab.
TEL:04-24517250 # 4945
VHDL程式基本架構
FCU, Department of ECE , IC Design Research Lab.
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VHDL程式基本架構
Library／ Package 宣告區
Entity宣告區
Generic 定義
Port 定義
Architecture 描述區
Component宣告
Signal宣告
BEGIN
Description statements
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VHDL程式基本架構
VHDL模型檔(****.vhd)
-- VHDL Design Unit 檔案說明
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY e-name IS
--port declaration
PORT (
P-name: mode type;
);
END ENTITY e-name;
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VHDL程式基本架構
ARCHITECTURE a-name OF e-name IS
--component declration
COMPONENT …..
END COMPONENT.. ;
--signal declaration
SIGNAL s-name: type;
BEGIN
--Concurrent statements; (設計內容)
END ARCHITECTURE a-name;
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VHDL程式範例
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IC7400 is
Port ( a1,a2,b1,b2,c1,c2,d1,d2 : in std_logic;
ao : out std_logic;
bo : out std_logic;
co : out std_logic;
do : out std_logic);
end IC7400;
architecture a of IC7400 is
begin
ao <=
bo <=
co <=
do <=
end a;
not (a1 and a2);
not (b1 and b2);
not (c1 and c2);
not (d1 and d2);
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Library … 宣告物件所存放之地方
1、LIBRARY
宣告user引用之物件所存放之地方
(library) …… IEEE
。一般, Simulator會對Library事先建立一個”對照表” ,
存於 **.ini 檔中
。此”對照表” 包括已事先設定(預設)之library及
其對映到磁 牒中之實際位置
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USE … 開啟 library中之package
2、USE
。開啟library中之package，以便使用宣告與定義過
的物件
、
。Package 用來宣告
定義一些VHDL中
可使用的物件 (Objects)
。物件包括：TYPE，Sub-program(Function, Procedure)，
CONSTANT, Deferred constant等
【語法】:
USE
Lib-name .package-name.all;.
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USE ------Compile時, 物件引用之package順序
(1) 預設之library package
(2) 宣告之library package。
Library與Use宣告之效力僅及於該Design unit
(Entity)
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ENTITY …
設計單元 (DESIGN unit) 定義
設計(DESIGN)定義 :
Design- unit name 與 external介面 (ports)
……… 相當於元件外型(name & pins)
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註解 (Comment)
hyphen ’--‘ 開頭，直到 Carriage-return 為止。
善用註解：
。VHDL design 檔最好加上適當之header；
註明: design unit, file name, function, modules Called,
limitation, author , revision number and date。
[範例]：
-- Design unit : y_func
-- File name : y_func.vhd
-- Function : Y(a,b,c)=Σ(1,3,6,7)=(not A and C) or (A and B)
-- limitation : No
-- Author
: MS-Shiau
-Department of Electronics ，Feng-Chia University
-- Revision : V.1 12/31/2001
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PORT (埠)
相當於 ……..
IC: pins ,
system : external interface signals
[語法]：
PORT(
p1-name : mode type ;
p2-name : mode type ;
…
pN-name : mode type );
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PORT ---- mode
IN , OUT , INOUT , BUFFER
Oen
INOUT
IN
OUT
BUFFER
Ien
IN :只可由單體外之信號驅動
OUT :可multi-driven , 不可 feed-in (不可驅動單體內之信號).
BUFFER: (與OUT似,但可feed-in內驅; 因不可多驅,一般較少用)
INOUT：全部PORTs均如此宣告會使程式可讀性降低
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Architecture
1、ARCHITECTURE
。 Design-unit設計內容: 功能描述
【語法】：
ARCHITECTURE a-name OF e-name IS
SIGNAL s-name： type ； ----- declaration
BEGIN
Concurrent Statements (功能描述) ；
END Architecture a-name ；
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描述風格(Description styles)
1、典型的描述風格(Description styles)
(1)Structural : 元件及其連接情形；Netlist 方式
(包括：Component.VHDL檔 , 及Design-unit中 Component
宣告, Component 啟動instantiation)
(2)Behavior : Process 方式, Function or Procedure方式
(包括： Sequential (timing順序安排) statements)
(3)Data-flow : Boolean 方式之concurrent signal assignments
(信號data處理，傳輸，方向。並時性, 以Boolean函式指定
信號值)
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Description styles運用
描
述
風
Structure style
Behavior style
Data-flow style
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格 特
色
與
使
用
適於階層式方塊元件(Toplevel)之design-module之建立；
具Reuse之特性
適於複雜電路之建立，但以
此描述合成之電路不易掌握
適於簡單電路之建立，以此
描述合成之電路具有較佳之
特性
DATA TYPE
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資料物件
VHDL中的物件使用前須事先宣告其「類別」與
「資料型態」
【語法】 ：
類別 資料物件名稱 ： 資料型態 ：= 初始值 ；
初始值 (Initial value)：
All signals have an initial value when simulation begins.
。User defined ： in the declaration (Ex :=‘0’ )
。Default ：the 1’st (left) value that appeared
in type declaration
※Initial value assignment is ignored in H/W synthesis.
。Way for synthesis: Global (Power-on ) reset
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物件類別
類別(Class)：
(1)port, Signal:
。 Circuit-connection (Wire名稱or正反器狀態)
。 Driver is scheduled by queue: ie. Means they have time-delay)
(2)Constant :
。代表一個固定值的identifier; 增加可讀性與可維護性.
。不可於程式執行中更改其值。
(3)Variable:
。只限於process or副程式中使用.
。不代表實際wire or 狀態, Local-storage operation
。其值於程式執行中可更改。
(Updated immediately, no delay)
(4)檔案(File)：
代表工作環境中之檔案，可有效地協助電路模擬之執行。
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型態
語法:
TYPE 型態名稱 IS ………………………
機定(Default) ：
在Standard package 與IEEE package中已預先定義者。
自訂(User)：
在User package 中 or
VHDL design unit中的Architecture與Begin 間宣告
者。
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典型標準之Types定義( STANDARD )
Package STANDARD
Type Boolean is (false,true);
Type Bit is (‘0’,’1’);
Type Character is ( ‘A’,..,‘0’,…等 );
Type severity_level is (note, warning, error, fail);
Type integer is range -2147483648 to 2147483647;
Type real is range -1.7014110e+38 to 1.7014110e+38;
Type time is range -9223372036854775807 to 9223372036854775807
Units fs;
Ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us;
sec = 1000 ms; min = 60 s; hr = 60 min; End units;
Subtype natural is integer range 0 to integer’high;
Subtype Positive is integer range 1 to integer’high;
Type string is array (positive range <>) of character;
Type bit_vector is array (natural range <>) of bit;
Function now return time;
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典型標準之Types定義 ( std_logic_1164 )
Type std_ulogic is (‘U’,’X’, ‘0’,’1’, ‘Z’,’W’, ‘L’,’H’,’-’ );
Function resolved (s: std_ulogic_vector) return std_ulogic;
Subtype std_logic is resolved std_ulogic;
函式呼叫
參數傳遞
Type std_ulogic_vector is array (natural range <>)of std_ulogic;
Type std_logic_vector is array (natural range <>)of std_logic;
Function “and” …
----- Include : “and”, “nand” , “or”, “nor” , “xor”, “not” .
----- Conversion Function:
Function to_Bit …
; to_Bitvector ,
to_stdulogic ; to_stdulogicvector ;
to_stdlogicvector ;
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典型標準之Types定義( std_logic_arith )
1992 Synopsys inc.
Type Unsigned is array (natural range <> ) of std_logic;
Type Signed is array (natural range <>) of std_logic;
Functions:
(1)arithmetics: “+”, “-”, “*”,
(2)Relation: “<”, “>”, “=”, “>=”, “=<”, “/=”,
(3)shift: SHL (arg,count) , SHR (arg,count),
Conversion Function:
CONV_integer ;
CONV_SIGNED(arg,size) ; CONV_UNSIGNED…
CONV_std_logic_vector(arg,size)
Note: std_與signed/unsigned純為 type “Cast” conversion :
B<=Unsigned(A) ; Signed (A) ; ----- A std_logic
A<=std_logic_vector(B) ; ----- B Signed or unsigned
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純量型(scale)
--- Integer
1、Integer：(default-defined)
TYPE integer IS range ____________ ;
。 32- 位元 , 範圍: -(231) ~ +(231-1)
。必要時可自行宣告範圍以減小合成之後電路的Size
[語法]：User-defined integer (range spec. use integer)
TYPE my_integer IS RANGE range_low TO range_hi；
TYPE my_integer IS RANGE range_hi DOWNTO range_low；
TYPE my_integer IS RANGE <>；
Note: <> --無限制(unconstrained) (物件宣告時再定)
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純量型(scale) --- Real
2、Real： (range spec. use real)
TYPE real IS range ………… ;
。數字須有小數點:
-1.0 e38 ~ +1.01e38 ;
[範例]：
Signal A: real ;
A<= 2.5E-15;
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純量型(scale) --- Physical Type
Physical Data Type
TYPE time IS Range <>
--基本單位範圍指定
Units
fs；
--基本單位
ps=1000 fs； --延伸單位
ns=1000 ps；
us=1000 ns；
ms=1000 us；
sec=1000 ms；
min=60 sec；
hr = 60 min；
END units；
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TYPE distance IS Range 0 TO 231-1
Units
nm；
um=1000 nm；
mm=1000 um；
cm=10 mm；
m=1000 mm；
Km=1000 m；
END units；
陣列型(Array)資料型態
陣列型(Array) …… 或稱 “矩陣”
。其元素由同一種之資料型態組合而成的複合式資料型態
[語法]:
TYPE ary_name IS ARRAY (起迄範圍) OF 元素類態；
※機定：一維陣列，
起迄範圍： 低 To 高 ；高DOWNTO 低 ; Integer < > …..unconstrained array
Note: Standard unconstrained array 為 Bit_vector 與 String
TYPE ary_name IS ARRAY(d_1_range , … , d_n_range) OF 元素型態；
※Note ：多維陣列 ; 起迄範圍/維
個別元素之指定；ary_name (integer)
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陣列型(Array)資料型態
【例】: VHDL
STANDARD package 中
Bit_vector ……. Bit之一維陣列
TYPE bit_vector IS ARRAY (natural <>) OF bit；
【例】: 一維陣列型態宣告
TYPE byte IS ARRAY (7 downto 0) OF bit；
TYPE word IS ARRAY (31 downto 0) OF bit；
TYPE Memory_name IS ARRAY (0 to 4096) OF word；
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陣列型(Array)資料型態
[範例]: 多維陣列型態宣告 ROM_ LUT：
-- 定義ROM_look-up-table之格式型態( 8X4 之陣列)
TYPE Rom_block IS ARRAY (0 TO 7, 0 TO 3) OF BIT;
-- 宣告物件:ROM_LUT與 設定其初始值
CONSTANT ROM_LUT : Rom_block := (
( ‘0’, ‘1’, ‘1’, ‘0’ ),
( ‘0’, ‘1’, ‘1’, ‘0’ ),
( ‘0’, ‘1’, ‘0’, ‘1’ ),
( ‘0’, ‘0’, ‘0’, ‘0’ ),
( ‘0’, ‘1’, ‘1’, ‘0’ ),
( ‘1’, ‘0’, ‘1’, ‘0’ ),
( ‘0’, ‘1’, ‘1’, ‘0’ ),
( ‘1’, ‘1’, ‘1’, ‘1’ ) );
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陣列型(Array)資料型態
2-Dimension Array type declaration
【範例】：定義一個 記憶容量為 1232 之ROM資料表Type
【Method-1】：1-D of 1D
TYPE word IS ARRAY(31 downto 0) of bit;
TYPE ROM_TABLE IS ARRAY(11 downto 0) of word;
【Method-2】：2D-directly
TYPE ROM_TABLE IS ARRAY(11 downto 0 , 31 downto 0) of bit ;
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OPERATOR
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分類
邏輯(Logic)
AND
OR
NAND
NOR
NOT
XOR
關係(Relation)
=
/=
<
<=
>
>=
四則(加減乘除)
+
-
*
/
MOD
REM **
符號
+
-
其他
ABS
&
移位／旋轉
SLL
SRL
SLA
SRA
ROL
ROR
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XNOR
運算優先順序
高 **
低
ABS
NOT
*
/
MOD
REM
SIGN “+”
SIGN “”
ADD “+”
ADD “”
=
/=
<
<=
>
>=
AND
OR
NAND
NOR
XOR
XNOR
優先權可用”小括號”定優先順序
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邏輯運算
邏輯運算子: AND, NAND, OR, NOR, NOT, XOR, XNOR
邏輯運算中NOT優先權最高，其他優先權一樣。
必要時可用小括號定優先順序。
在IEEE Library中定義邏輯運算值是以查表方式實現
【Example】
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-----------------------------------------------------| U X 0 1 Z W L H | |
----------------------------------------------------( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
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關係運算子
Scalar object 關係運算子為 “Overload” function
會傳回一個 Boolean 值(True/False)
FUNCTION “>” (L: operand_type ; R: operand_ type ) RETURN BOOLEAN;
(Standard 與IEEE.std_logic_1164 package沒有包含）
使用時： USE IEEE.NUMERIC_STD;
L(R) operand_type
R(L) operand_type
IEEE-1076.3 Numeric_bit & Numeric_std
Signed
Signed
Unsigned
Unsigned
Signed
Integer
Unsigned
Natural
物件需為integer, Signed
與Unsigned型態
A: std_logic_vector
SIGNED(A)
SYNOPSYS Std_logic_signed & Std_logic_unsigned
Std_logic_vector
Std_logic_vector
Std_logic_vector
Integer
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使用在Std_logic物件型態
四則運算子
加減運算
1、Integer 型態
。 沒有MSB進位處理
。 欲有MSB進位處理, 可採Signed – extension方式
(1)轉換: Signed(A) 或 Unsigned(A) ; A整數
(2) 用‘&’ operator 多串一位 ,來儲存MSB進位,
正數: ‘0’&B
負數: ‘1’&B
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四則運算子
2、Std_logic_vector 型態
需先將 std_logic_vector 化為 Signed or Unsigned 型態.
既可做邏輯運算處理也可做數值計算
物件Unsigned與Signed宣告, 一律以 downto 定出數列大小
需使用 下列packages
(1) Synopsis: Std_logic_arith
(2) IEEE: Numeric_std
【範例】：Addition -- AIN,BIN：8-BIT_std
Result <= (‘0’&unsigned(AIN)+(‘0’&unsigned(B(IN))+Cin ；
Cout <= Result (8)
Note： & 與 + 優先權相同，故加上小括號處理優先順序。
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四則運算子
3、Bit_vector 型態
Bit_vector 型態：用 unsigned處理
使用時:
(1)用Numeric_BIT package ，
(2)轉換:將 bit_vector 作unsigned處理;
(3)最後將結果再 bit_vector化
【範例】：
Sum <= bit_vector( unsigned(AIN) + unsigned(BIN))；
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移位/旋轉運算子 ……
IEEE.Numeric_std
亦為“Overload function”, 於1076_1993 (1076.3 ,
Numeric_std)加入
適用於任何一維陣列，type為Signed , unsigned
邏輯移位
語法：Function 呼叫
1 0 1 1 0 0 1 1
移出之位元：漏失
SLL (arg , N)
移走之位元：補
‘0’
1 1 0 0 1 1 0 0
SRL (arg , N)
其中：
SLL(a, 2)
1 1 0 0 1 1 0 1
移走之位元：補
‘0’
Arg: signed or unsigned
N: integer
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SRL(a, 2) 移出之位元：漏失
0 0 1 1 0 0 1 1
移位/旋轉運算子 …… IEEE.Numeric_std
1 0 1 1 0 0 1 1
語法：Function 呼叫
ROL (arg , N)
ROL(A, 2)
1 1 0 0 1 1 1 0
ROR (arg , N)
其中：
Arg: signed or unsigned
N: integer
1 1 0 0 1 1 0 1
ROR(A, 2)
0 1 1 1 0 0 1 1
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移位/旋轉運算子
算數移位
1 0 1 1 0 0 1 1
移出之位元：漏失
SLA 2
移走之位元：補LSB
1 1 0 0 1 1 1 1
1 1 0 0 1 1 0 1
移走之位元：補 MSB
SRA 2
移出之位元：漏失
1 1 1 1 0 0 1 1
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移位運算子
SYNOPSYS package :
…… std_logic_std
std_logic_arith
Signed extension (符號延伸)觀念之移位
SHL & SHR
完全採正常FUNCTION呼叫方式使用,實際上非Operator
SHR(A, N) ; -- A:signed or unsigned , N:unsigned
1 0 1 1 0 0 1 1
移出之位元
：漏失
SHL (AIN,2)
移走之位元
：補‘0’
1 1 0 0 1 1 0 0
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1 1 0 0 1 1 0 1
移走之位元
：補 MSB
SHR(AIN,2) 移出之位元
：漏失
1 1 1 1 0 0 1 1
範例： 移位/旋轉運算子
【範例】：SYNOPSYS
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE Std_logic_arith.all; -------------- Package
ENTITY Exp_SSHFT IS
PORT(AIN: IN std_logic_vector(3 downto 0);
BoutL: OUT std_logic_vector(7 downto 0);
BoutR: OUT std_logic_vector(7 downto 0);
Ncount : in std_logic_vector(1 downto 0))
END ENTITY EXP_SSHFT;
ARCHITECTURE A OF EXP_SSHFT IS
BEGIN
BoutL <= SHL( unsigned(AIN) , unsigned(Ncount));
BoutR <= SHR(unsigned(AIN) , unsigned(Ncount));
----正常FUNCTION呼叫
END A;
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FCU, Department of ECE , IC Design Research Lab.
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Signal Assignment
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Signal Assignment 特性
Signal Assignment : 兩端之Signal type均須一致
Signal
A<=B; ---有延遲現象
Variable A:=B ; ---Variable只能用在Process or 副程式中.
簡單型
條件型
(1) assign When…Else
(2) IF …Then assign ; Elsif… Then assign ; End IF;
具排它性,具優先性(愈前愈優先)
選擇型
(1)With sel_name Select assign when… , assign when others ;
(2)Case sel_name Is When… =>assign; End Case;
Note:sel_name所有的 ”值” 均須考慮,故使用others
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Multiple-driven Signal
How do we determine the state of this wire
Driver A
What value ?
Driver B
21 MUX with
tri-state output
(Resolved Signal)
Rule to determine: resolution function
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What value ?
Conditional Assignment
優先順序性
Cond_expression一般均以對多重信號之值的判斷 , 作為條
件Assign 之基礎
Conditional Assignment中的每項均具有排他性；(具有優
先順序性)。
Exp_1
cond_1 cond_2
S_name
cond_1
S_name
Exp_2
1
x
→
Exp_1
0
1
→
Exp_2
0
0
→
Exp_3
cond_2
Exp_3
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Selective Assignment
…… MUX
Selected signal Assignment 相當於MUX語法；
對單一信號的組合值做判斷基礎。
各選擇之間優先順序性相同。
MUX
Expression for多重值 , 相同選擇：
。List : 1 / 3 / 9
。Range : (1 to 4 )
A
B
Y
C
選擇信號(Ctl)：各種組合值均須考慮。
若否，則須以When Others概括之。
D
Ctl
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Concurrent(並時性)
簡單型
【語法格式】
S1 <= Expr ;
條件型 （多重信號源判斷：有優先順序）
【語法格式】
S1 <= Expr1 WHEN Cond1 ELSE
Expr2 WHEN Cond2 ELSE
Exprn ;
選擇型 （單一信號判斷：無優先順序）
【語法格式】
WITH Sel_name SELECT
S1 <= Expr1 WHEN Value1,
Expr2 WHEN Value2,
Exprn WHEN OTHERS ;
Note: Concurrent, 先做再談條件,不留尾巴
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Sequential(順序性)
簡單型
【語法格式】
S1 <= Expr ;
S1 := Expr ;
條件型 （多重信號源判斷：有優先順序）
【語法格式】
IF Cond1 THEN S1 <= Expr1 ;
ELSIF Cond2 THEN S2 <= Expr2 ;
ELSE Sn <= Exprn ;
END IF ;
選擇型 （單一信號判斷：無優先順序）
【語法格式】
CASE Sel_name IS
WHEN Value1 => S1 <= Expr1 ;
WHEN Value2 => S2 <= Expr2 ;
WHEN OTHERS => Sn <= Exprn ;
END CASE ;
Note: Sequential , 先談條件再做, 留尾巴
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…
範例
A
B
C
D
MUX
Y
SEL
以不同方式來編寫
Y AS1 S 0 BS1 S 0 CS1 S 0 DS 1 S 0
A
Ture Table
SEL
B
Y
S1
S0
0
0
A
0
1
B
1
0
C
1
1
D
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Y
C
D
SEL
範例 ……
並時性_簡單型
--mux_4to1_con.vhd
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
ENTITY mux_4to1_con IS
PORT( a,b,c,d : IN std_logic ;
sel : IN std_logic_vector(1 downto 0) ;
y: OUT std_logic ) ;
END mux_4to1 ;
ARCHITECTURE data_flow OF mux_4to1_con IS
SIGNAL tmp_a, tmp_b, tmp_c, tmp_d: std_logic ;
BEGIN
tmp_a <= a AND NOT sel(1) AND NOT sel(0) ;
tmp_b <= b AND NOT sel(1) AND sel(0) ;
tmp_c <= c AND sel(1) AND NOT sel(0) ;
tmp_d <= d AND sel(1) AND sel(0) ;
y <= tmp_a OR tmp_b OR tmp_c OR tmp_d ;
END data_flow ;
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範例 …… 並時性_條件型
--mux_4to1_con.vhd
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
ENTITY mux_4to1_con IS
PORT( a,b,c,d : IN std_logic ;
sel : IN std_logic_vector(1 downto 0) ;
y: OUT std_logic ) ;
END mux_4to1_con ;
ARCHITECTURE cond OF mux_4to1 IS
BEGIN
Y <= a WHEN sel=“00” ELSE
b WHEN sel=“01” ELSE
c WHEN sel=“10” ELSE
d WHEN sel=“11” ELSE
‘0’ ;
END cond ;
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範例 ……
--mux_4to1_con.vhd
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
ENTITY mux_4to1_con IS
PORT( a,b,c,d : IN std_logic ;
sel : IN std_logic_vector(1 downto 0) ;
y: OUT std_logic ) ;
END mux_4to1_con ;
ARCHITECTURE seq OF mux_4to1 IS
BEGIN
WITH sel SELECT
Y <= a WHEN “00” ,
b WHEN “01” ,
c WHEN “10” ,
d WHEN “11” ,
‘0’ WHEN OTHERS ;
END seq ;
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並時性_選擇型
範例 ……
順序性_簡單型
--mux_4to1_seq.vhd
略
ARCHITECTURE data_flow OF mux_4to1 IS
BEGIN
PROCESS(a,b,c,d,sel)
VARIABLE tmp_a, tmp_b, tmp_c, tmp_d: std_logic ;
BEGIN
tmp_a := a AND NOT sel(1) AND NOT sel(0) ;
tmp_b := b AND NOT sel(1) AND sel(0) ;
tmp_c := c AND sel(1) AND NOT sel(0) ;
tmp_d := d AND sel(1) AND sel(0) ;
y <= tmp_a OR tmp_b OR tmp_c OR tmp_d ;
END PROCESS ;
END data_flow ;
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範例 ……
--mux_4to1_seq.vhd
略
ARCHITECTURE cond OF mux_4to1 IS
BEGIN
PROCESS(a,b,c,d,sel)
BEGIN
IF sel=“00” THEN Y <= A ;
ELSIF sel=“01” THEN Y <= B ;
ELSIF sel=“10” THEN Y <= C ;
ELSIF sel=“11” THEN Y <= D ;
ELSE Y <= ‘0’ ;
END IF;
END PROCESS ;
END cond ;
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順序性_條件型
範例 ……
--mux_4to1_seq.vhd
略
ARCHITECTURE seq OF mux_4to1 IS
BEGIN
PROCESS(a,b,c,d,sel)
BEGIN
CASE sel IS
WHEN “00” => y <= a ;
WHEN “01” => y <= b ;
WHEN “10” => y <= c ;
WHEN “11” => y <= d ;
WHEN OTHERS => y <= ‘0’ ;
END CASE ;
END PROCESS ;
END seq ;
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順序性_選擇型
COMPONENT(元件)
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Component
…… Concepts
屬於structure style 描述方式 (Netlist type)；完整之應用，包
含三項：
(1)Component design unit : C_name.vhd
….. 建立元件模型本體. 元件功能描述(Model)
(2)Component declaration :
……使用時元件宣告：元件名稱, 元件長相(pins)；
格式與Entity類同(Component取代）
(3)Component instantiation :
……元件啟動：連線 PORT MAP
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Component
Component model … (comp.vhd)
( in “work” package )
Design-unit model … (struc.vhd)
Entity …… end entity
Architecture
component declaration here
Begin
Component instantiation here
End architecture
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元件模型建立
標準的VHDL design-unit Model設計
Entity 元件名稱 is
Port (元件介面接腳）
End 元件名稱 ;
Architecture A1 of 元件名稱 is
Begin
……………
End architecture A1;
P1 ~ P3: Formal name
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Component 使 用 ……
元件宣告
事先將欲使用之模型(Model)建立成*.vhd
元件名稱,PORT需與元件模型(Model)之Entity名稱相同
使用前必須引入元件模型(Model) 庫以供程式使用,
一般為 USE WORK.ALL;
【語法格式】
宣告
COMPONENT CP_name
PORT( p1,p2: MODE TYPE;
p3: MODE TYPE ) ;
END COMPONENT ;
P1 ~ P3: Formal name
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Component 使 用
…… 元件啟動 (拉線指定)
PORT MAP: 啟動元件之拉線指定
[語法格式]:
U1: Comp_name PORT MAP(拉線指定);
Note: S1~S3 :Physical Name;
CP_P: Formal Name
(1)By Name
PORT MAP(CP_p1 => s1,
CP_p2 => s2,
CP_p3 => s3) ;
(2)By Position
PORT MAP(s1,s2,s3) ;
若無需用到之輸出接腳可以宣告為OPEN,
輸入接腳 則需接’1’或’0’; (除非有設定Port initial value可用OPEN)
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使用 ……
另一種方式
【語法格式】
(1)有元件宣告時
Un: CP_name PORT MAP(p1, p2, pn) ;
(2)無元件宣告時
Un: WORK.E_name(A_name)
PORT MAP(p1, p2, pn) ;
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範 例
And-Or Design-Unit
Design - Unit
(1)元件Model建立
。AND model
。OR model
A1
A2
Y
B1
B2
(2)And-Or模組建立
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Sa
Sb
Example … 元件模型之建立
--Component design unit (and2.vhd)
LIBRARY IEEE;
USE IEEE.std_logic_1164.all ;
ENTITY and2 IS
PORT ( x,y : in, std_logic ;
z : out std_logic ) ;
END and2;
ARCHITECTURE a_and2 OF and2 IS
BEGIN
z <= x and y ;
END a_and2 ;
x
y
AND
z
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--Component design unit (or2.vhd)
LIBRARY IEEE;
USE IEEE.std_logic_1164.all ;
ENTITY or2 IS
PORT ( x,y : in, std_logic ;
z : out std_logic ) ;
END or2;
ARCHITECTURE a_or2 OF or2 IS
BEGIN
z <= x or y ;
END a_or2 ;
x
y
OR
z
Example … 結構化描述之模組
--Design unit (AND-OR.vhd)
LIBRARY IEEE;
USE IEEE.std_logic_1164.all ;
USE WORK.all ;
ENTITY and_or IS
PORT ( a1,a2,b1,b2 : in, std_logic ;
y : out std_logic ) ;
END and_or;
ARCHITECTURE A_and_or OF and_or IS
Design - Unit
A1
A2
Sa
Y
B1
B2
Sb
Component and2
PORT ( x,y : in std_logic ;
z : out std_logic ) ;
END Component ;
Component or2
PORT ( x,y : in std_logic ;
z : out std_logic ) ;
END Component ;
Signal sa,sb : std_logic ;
BEGIN
U1: and2 port map(a1,a2,sa) ;
U2: and2 port map(b1.b2.sb) ;
U3: or2 port map(sa,sb,y) ;
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END A_and_or ;
PROCESS
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PROCESS …… 功能
PROCESS Statement本身為 Concurrent
Statement
Statements in a PROCESS are executed
sequentially. (Sequential Statements)
行為化描述(Behavior-description)電路模型的
基礎 (Modeling complex behavior)
[典型之用處]：
1. I/O bebavior not easily using CSs.
2. Models utilize state information
3. Incorporate data structure
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Process statement
【語法格式】
[Lable：] PROCESS (Sensitivity_sig_List)
process_declaration_item;
(such as : Constant, Variable, Subprogram ;
Not Signal)
BEGIN
{sequential_statement}
END PROCESS [Lable] ;
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Process …… 說明
[Lable]: 可省略,但為可讀性,一般均有命名.若有 lable 則
END PROCESS 亦有 lable, 且名稱相同.
Sensitivity_List: 感測信號列表中如有信號變化(‘Event),則
PROCESS statement 會被計算處理.凡PROCESS中條件式
輸入信號與信號指定右邊之信號均須列入 Sensitivity-list.
process_declaration_item: 只有local影響力
Variables: Static, Initialized once and retain their values between
process activated
PROCESS電路合成結果, 可合成為組合邏輯
(Combinational-logic)電路, 亦可合成為序向邏輯
(Sequential-logic)電路
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PROCESS
……
Simulation
Process is executed once at the beginning of
simulation , then suspended (Automatically)。
Process is reactivated when listed sensitivity-signals
are evented。
Variable value: Static
。Initialized once only (at the beginning of simulation )
。Maintains the last value (between process activation)
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Process …… without sensitivity list
等效描述
(1)Lable: PROCESS
declaration;
BEGIN
sequential statements;
WAIT ON s1,s2;
END PROCESS Lable;
(2)Lable: PROCESS (s1, s2)
eclaration;
BEGIN
sequential statements;
END PROCESS Lable
Note: (1) Sensitivity list (2) WAIT statement倆者,
。只能有一者存在, 不可倆者俱在.
。如果倆者均不存在, 則Process會陷入無限之循環
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範例
…… Sequential Circuit 合成
D_flip_flop……CLK’event
Library ieee;
Use ieee.std_logic_1164.all;
Entity D_FF is
Port(CLK, D_in: IN std_logic;
Q_out: OUT std_logic);
End entity D_FF;
Architecture a1 OF D_FF IS
Begin
Process (CLK, D_in, Nclr)
Begin
IF Nclr=‘0’ then D_out<=‘0’;
ELSIF (CLK’event and CLK=’0’ )
then Q_out<=D_in;
End IF;
End Process;
End a1;
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D_latch…….. No Else
Library ieee;
Use ieee.std_logic_1164.all;
Entity D_latch is
Port(EN, D_in: IN std_logic;
Q_out: OUT std_logic);
End entity D_latch;
Architecture a2 OF D_latch IS
Begin
Process (EN, D_in)
Begin
IF(EN=’1’ ) then
Q_out<=D_in;
End IF;
End Process;
End a2;
範例
…… Combinational Circuit 合成
Mux2x1
Library ieee;
Use ieee.std_logic_1164.all;
Entity mux2x1 is
Port(A, B, S: IN std_logic;
End entity mux2x1;
Y: OUT std_logic);
Architecture A3 OF mux2x1 IS
Begin
Process (S, A, B)
Begin
IF(S=’1’ ) then
Y <= A;
Else
Y<= B;
End IF;
End Process;
End A3;
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範例： Design a D-F/F model
D Flip Flop
CLR PS CLK
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Qn+1
/Qn+1
L
-
-
L
H
H
L
-
H
L
H
H
↓
D
/D
H
H
-
Q0
/Q0
範例
…… Sequential合成 (D-F/F)
--d_ff.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY d_ff IS
PORT( d,clk,clr,ps: IN std_logic;
q,q_bar: OUT std_logic );
END d_ff;
ARCHITECTURE A OF d_ff IS
BEGIN
PROCESS(d,clk,clr,ps)
BEGIN
IF(clr=‘0’) THEN q <= ‘0’; q_bar <= ‘1’;
ELSIF(ps=‘0’) THEN q <= ‘1’; q_bar <= ‘0’;
ELSIF(clk’event and clk=‘0’) THEN q <= d; q_bar <= not d;
END IF;
END PROCESS;
END A;
No Else
D F/F synyhesized
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範例
…… Combinational合成
Concurrent Process …… Full_Adder
Library ieee;
Use ieee.std_logic_1164.all;
Entity FA is
Port (In1,In2,c_in:in std_logic;
Sum,c_out:out std_logic);
In1
End entity FA;
Architecture A1 of FA is
In2
Signal s1,s2,s3:std_logic;
Begin
HA1:Process(In1,In2)
C_In
Begin
S1<=in1 xor in2; S2<=in1 and in2;
End process HA1:
HA2:Process(S1,c_in)
Begin
Sum<=s1 xor c_in; S3<=s1 and c_in;
End process HA2:
OR1:Process(S2,S3)
Begin
C_out<=s2 or S3;
End process OR1:
End architecture A1,
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s1
HA
sum
HA
s2
s3
OR2
C_out
Passive Process
何謂“被動程序”?
一個存在於ENTITY中的 Process Statement
功能?
做各種不同的檢查與檢查時機之建立
影響效力: 同一 Entity中的每個Architecture均自動擁有此Process
相關之功能
Passive Process與一般Process Statement的差異性
使用方法相同, 但Passive Process只能存在Entity中, 而一般Process
則是存在Architecture之中
Passive Process中不可以有signal assignments , 但相關之設定可
以使用 Variable-assignment.
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Sequential Statements
WAIT/NEXT
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WAIT statement
Suspends the execution of Process statement
Formats: Process is reactivated at
WAIT FOR time ; … time interval after current time
WAIT ON sig_event ; One or more Signal Event occur
WAIT UNTIL condition ; … Condition true
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Example
……
of Wait
Wait for 50 nec ;
:Process suspended now and reactivated after 50 ns
Wait on A, B, C ;
:Process suspended now and reactivated when
one or more of listed signals is evented
Wait until A=B ;
:Process suspended now and reactivated When A=B
Wait;
:Wait forever
Wait on sig_event after 100 ns ;
Wait until condition after 100 ns ;
:Process suspended now and reactivated When ……
Either wait for-event (until condition) occur
Or 100 ns time elapsed
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範 例 ……
WAIT
WAIT UNTIL clk=’1’;
WAIT UNTIL clk’event and clk=’1’;
WAIT UNTIL not clk’stable and clk=’1’;
此三者等效
∵PROCESS statement為Concurrent
且為event-driven
故clk產生event之後Process執行,
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範 例 ： ……… Wait statement
等效描述
(1)Lable: PROCESS
declaration;
BEGIN
sequential statements;
WAIT ON s1,s2;
END PROCESS Lable;
(2)Lable: PROCESS (s1, s2)
eclaration;
BEGIN
sequential statements;
END PROCESS Lable
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Wait …… Waveform Generation
Reset
Library ieee;
use ieee.std_logic_1164.all;
Phi1
Entity none_overlapped_clk is
Phi2
Port(Phi1,Phi2,reset: out std_logic);
End Entity none_overlapped_clk;
Architecture A1 of none_overlapped_clk is
Begin
Reset: Reset <= ‘1’ , ‘0’ after 5 ns;
Clk_P: Process is
Begin
Phi1 <= ‘1’ , ‘0’ after 10 ns;
Phi2 <= ‘0’ , ‘1’ after 12 ns , ‘0’ after 18ns;
Wait for 20ns;
End process clk_p;
End architecture A1;
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NEXT statement
Used to stop the current loop iteration
FORMAT:
NEXT [loop_lable] WHEN condition
Operation :
If the condition is true , then
the current iteration of the loop labeled with loop_label (or inner-most) is
terminated.
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EXIT statement
Similar to NEXT statement
except that terminate the entire loop
Format:
EXIT [loop_level] WHEN condition;
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LOOP Statement
FOR…LOOP / WHILE…LOOP/ LOOP
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Loop Statement
Three type:
1、Known loop_number
FOR … LOOP
… END LOOP;
2、Unknown loop_number
WHILE … LOOP … END LOOP;
3、Simple loop
LOOP
… END LOOP;
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FOR … LOOP
Number_count type Loop
Format
FOR name IN range LOOP
… sequential statement;
END LOOP;
Note:
1. name&range must have same type
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範例
FOR I IN 1 TO 10 LOOP
A(I) := A(I)+1;
END LOOP;
-------WHILE A<B LOOP
A := A+1;
END LOOP;
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WHILE … LOOP
Conditional Loop
Format:
WHILE condition LOOP
… sequential statement;
END LOOP;
Note:
1. Never executed if condition is initially
false
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Simple LOOP
Format:
LOOP
… sequential statement;
END LOOP;
Executed continuously, So be insert with EXIT staement
Example:
LOOP
COMPUTE(x);
-- A Function named COMPUT
EXIT WHEN X <10 ;
END LOOP;
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Hierarchical Design
Parametric Modeling … Generics
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GENERICS
Design units 透過參數值設定結構； 適合發展參
數值可變之元件or系統。
Enables the construction of parameterized models
The value of generics must be known at compiling
time
Generics are constant objects and can only be read
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範例 ： 參數Delay time 設定
Typical parameter , used in Simulation only
Inertial delay :
適用於Gate-delay 規格之模擬。
Z <= x and y After 4 ns ；
Transport delay :
適用於Path-delay 規格之模擬
Z <= Transport x and y After 4 ns ；
Generic 參數
Z <= x and y After delay_time ；
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Generics 宣告
…… (參數化元件定義)
於參數化Component Model 的entity中宣告
語法：
GENERIC (gn_name : type := initial_value)；
範例：
ENTITY and2 IS
GENERIC (t_delay : time : = 4 ns)；
PORT ( x,y : in, std_logic; z : out std_logic)；
END Entity and2；
ARCHITECTURE a_and2 OF and2 IS
BEGIN
z <= x and y after t_delay；
END ARCHITECTURE a_and2；
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Generics 傳送
…… (參數化元件宣告)
在 使用此component之Design unit 的Architecture 中
component宣告時傳送
參數預定值
範例：
COMPONENT and2
GENERIC (t_delay : time : = 4 ns)；
PORT ( x,y : in, std_logic;
z : out std_logic)；
END COMPONENT ；
Note:兩處設定若不同時，則以component 宣告處為準。(原則：後者
優先)
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Generics 啟動
預定值(default value)的override
GENERIC MAP
…… 在component Instantiation時使用
Entity e_name IS
PORT ( a_name : mode, type; ……….)；
END Entity e_name；
ARCHITECTURE a_name OF e_name IS
COMPONENT and2
GENERIC (g_delay : delay_length : = 4 ns)；
PORT ( x,y : in, std_logic; z : out std_logic)；
END COMPONENT and2；
Map:第一優先
BEGIN
u1 : and2 generic map (10 ns) PORT MAP (a,b,c)；
END ARCHITECTURE a_name；
By name: g_Delay => 10 ns
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Generic ---- Default值使用
generic map (open) ；
……… 等效於不宣告
用於同一Generic被多重Override 後，
某一Component欲使用Default值時。
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範例 ： N-Input Gate
AND gate model different size AND gate
Entity generic_and is
generic (n : positive :=2);
PORT ( in1 : IN std_logic_vector((n-1) downto 0)
Y :OUT std_logic)；
END Entity generic_and；
ARCHITECTURE a1 OF generic_and IS
BEGIN
Process (in1)
variable and_temp : std_logic :=“0” ;
Begin
and_temp := ‘1’ ;
For I in (0 to (n-1) Loop
and_temp := and_temp and in(i);
End loop;
Y <= and_temp;
End process;
END ARCHITECTURE a1；
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Generic
…… Length-Parameter
[範例]:Design-Unit :
a length-parametric P_REG model
D_in(len_size-1)
D
Q
CLK
D (len_size-1) ………. DO
CLK
CLR Q (len_size-1) ……… QO
CLK
/Q
CLR
NRST
Q_out(len_size-1)
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範例: 通用P_REG model
N-bit Register參數化Model檔
Library ieee;
Use ieee.std_logic_1164.all
Entity P_reg IS
Generic (len_size: positive :=4 ); ………..參數:len_size 預定值=2
PORT (CLK, N_rst: IN std_logic;
D_in:IN std_logic_vector(len_size-1 downto 0);
Q_out: OUT std_logic_vector(len_size-1 downto 0))；
END Entity P_reg；
ARCHITECTURE a1 OF P_reg IS
BEGIN
PROCESS (N_RST, CLK);
BEGIN
IF N_RST=’0’ THEN Q_out <= ( OTHERS=>’0’ );
ELSIF ( CLK’event and CLK=’1’ ) THEN
Q_out <= D_in ;
END IF;
END PROCESS;
END ARCHITECTURE a1;
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P_REG 之使用
8-bit register (REG_8) model
-- 8_bit Register Device Model檔
Library ieee;
Use ieee.std_logic_1164.all
Entity reg_8 IS
PORT (CLK, N_rst: IN std_logic;
D_in: IN std_logic_vector(7 downto 0);
Q_out: OUT std_logic_vector(7 downto 0))；
END Entity reg_8；
ARCHITECTURE a8 OF reg_8 IS
Component P_reg
Generic( len_size:positive :=2); ---- 參數化元件宣告
PORT(CLK, N_rst: IN std_logic; D_in: IN std_logic_vector(7 downto 0);
Q_out: OUT std_logic_vector(7 downto 0))；
End Component P_reg;
BEGIN
U1: P_reg Generic map(8) ---- 參數化元件啟動
PORT map (CLK=>CLK,N_RST=>N_RST,D_in=>D_in,
Q_out=> Q_out);
END ARCHITECTURE a8;
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Generic_Adder
Let X:unsigned , Y; std_logic_vector
TYPE conversion (known as Cast )
X <= unsigned (y) ; Y <= std_logic_vector (X) ;
VHDL model: (參數化Model檔)
Library ieee;
Use ieee.std_logic_1164.all; ---- “+” for integer addition
Use ieee.Numeric_std.all; ---- “+” for Signed/ Unsigned addition
Entity Adder_n is
Generic (n: Positive :=4);
Port (A,B:in std_logic_vector (n-1 downto 0);
S:out std_logic_vector (n-1 downto 0);
Cin:in std_logic; Cout:out std_logic);
End Adder_n;
Architecture a1 of adder_n is
signal result, Carry: unsigned (n downto 0 ); ---- type conversion
Begin
Carry <=(0=> Cin, Others => ‘0’ ) ; ----cin=>Carry(0)
Result <= (‘0’&unsigned(A))+ (‘0’&unsigned(B))+Carry;
Sum <= std_logic_vector (result(n-1 downto 0 ));
Cout <= result (n) ;
End architecture a1;
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16_bit Adder
using parameterized Adder
-- 16_bit adder Device Model檔
Library ieee;
Use ieee.std_logic_1164.all;
Use work.all;
Entity add_16 is
Port(a,b:in std_logic_vector(15 downto 0);
s:out std_logic_vector(15 downto 0);
cin: in std_logic;cout:out std_logic);
End entity add_16;
Architecture a1 of add_16 is
Component adder_n
generic (n: positive :=4);
Port(a,b:in std_logic_vector(n-1 downto 0);
s:out std_logic_vector(n-1 downto 0);
cin: in std_logic;cout:out std_logic);
End component;
Begin
U1: adder_n generic map (16)
port map (a,b,s,cin,cout);
End a1:
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parametric
n to 2n decoder model
Diagram：
N input-lines
(n-1)………. O
Decoder (N-bit)
(2n-1)……… 0
2n output-lines
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… parametric n to 2n decoder model
N-bit Decoder 參數化Model檔
Library ieee;
Use ieee.std_logic_1164.all; ---- “+” for integer addition
Use ieee.Numeric_std.all; ---- “+” for Signed/ Unsigned addition
Entity decoder_n is
Generic (n: positive :=4);
Port (A:in std_logic_vector (n-1 downto 0);
Z:out std_logic_vector (2**n-1 downto 0));
End decoder_n;
Architecture a1 of decoder_n is
constant Z_out: Unsigned (2**n-1 downto 0) :=(0=>’1’, others =>’0’);
Begin
Z <= std_logic_vector sll(Z_out to_integer(unsigned (a)));
End architecture a1;
Note： std_logic_vector
To_bitvector
“1001”
To_ Stdlogicvector
Bit_vector
“1001”
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TEL:04-24517250 # 4945
Note： std_logic_vector Unsigned
Integer
A：
unsigned( )
To_integer( )
：B
“1001”
“1001”
5
Std_logic_vector
To_Unsigned(B,4)
Hierarchical Design
Regulated Modeling … Generate
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Generate Statement
GENERATE statement用來構建:
具有重複規則性連接結構(Regular interconnection)
的元件Model 。
【語法】： Concurrent - statement
G_label: 條件式-statement
GENERATE
Comp_label: comp_name PORT MAP(…; …; …);
END GENERATE;
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Generate 條件引述
Generate 條件式-statement , 常用格式
FOR …… GENERATE : Range define
IF …… GENERATE : value-define
典型用法：
(1). G_label1: FOR I IN low_limit TO hi_limit
GENERATE
Comp_label: comp_name PORT MAP(…; …; …);
END GENERATE;
(2). G_label3: IF I =3
GENERATE
Comp_label: comp_name PORT MAP(…; …; …);
END GENERATE;
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範例 ： A Register model
Entity reg_8 is
Port (D:in std_logic_vector(7 downto 0);
Q:out std_logic_vector(7 downto 0);
clk:in std_logic);
End reg_8;
Architecture a1 of reg_8 is
Begin
REG: For I in d’range GENERATE
U: DFF port map ( D(i), Q(i), clk);
END GENERATE;
End A1;
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TEL:04-24517250 # 4945
範例: Design Unit :
參數化Shift-register
(PG_SFT_REG_R) VHDL model
FF1
D_in
Temp 1
FF2
Temp 2
FF i+1
Temp i
FF length
Temp i+1
D_out
CLK
NRST
步驟：
(1)Design-Unit : “ DFF ” VHDL Model is required
(2)A parameterized generated structure
“PG_SFT_reg_L” model is defind
(3)Implement the shift-register model of a Specified-
length “SFT_REG_R8 model “
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parameterized generated structure
model PG_SFT_reg_R
Library ieee; Use ieee.std_logic_1164.all;
Entity PG_SFT_reg_R IS
Generic (lengthn : positive :=4);
PORT (CLK,NRST: IN std_logic; D_in: IN std_logic; D_out: OUT std_logic);
End entity PG_SFT_reg_R;
Architecture A1 of PG_SFT_reg_R IS
Component DFF
port (CLK,NRST,D: IN std_logic; Q: out std_logic) ; End component;
SIGNAL temp: std_logic_vector(1 to lengthn-1);
BEGIN -- define the number of structur-repeating
SFTL_reg : FOR I in 1 to (lengthn) GENERATE
Gen_start: IF I = 1 GENERATE
DffL1 : DFF PORT MAP (CLK, NRST, D_in, temp(1) ); End Generate;
Gen_end : IF I = lengthn GENERATE
DffL2 : DFF PORT MAP (CLK, NRST, temp(lengthn-1) , D_out ); End
Generate;
Gen_mid : IF( I>1)and(I<lengthn) GENERATE
DffL3 : DFF PORT MAP (CLK, NRST, temp(I-1) , temp(I) ); End Generate;
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End architecture
A1;
應用: 8-bit Shift_register Model
using PG_SFT_reg model
Library ieee;
Use ieee.std_logic_1164.all;
Entity SFT_reg_R8 IS
PORT (CLK,NRST, D_in : IN std_logic;
D_out: OUT std_logic);
End entity SFT_reg_R8;
Architecture A1 of SFT_reg_R8 IS
Component PG_SFT_reg_R IS
Generic (lengthn : positive := 8);
Port (CLK,NRST, D: IN std_logic; Q: out std_logic);
End component;
BEGIN
U1: PG_SFT_reg_R GENERIC MAP (lengthn => 8)
PORT MAP (CLK=>CLK, NRST=>NRST, D=>D_in, Q=>D_out);
End architecture A1;
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TEL:04-24517250 # 4945
應用: 8-bit Shift_register
Testbench
---- Preceding items aS usually used
-- Set the initial state of the register
NRST=‘1’ , ‘0’ after 5 nsec , ‘1’ after 10 nsec;
-- shift test process
Tester: Process
Variable Test_vector (7 downto 0) :=“10110010” ;
Begin
For I in test_vector’range loop
DIN <= test_vector(i);
CLK <= ‘0’; Wait for 5 ns; CLK <= ‘1’; Wait for 5 ns;
End loop;
Wait ;
End process Tester;
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State Machine
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Sequential
Logic
「邏輯電路」大系 －「結構示意圖」
邏輯電路
輸入
信號
輸出
信號
數位
電路
序向邏輯
組合邏輯
序向邏輯
輸入
信號
現在狀態
P_STATE
輸出
信號
組合邏輯
輸入
信號
輸出
信號
組合
邏輯
下一狀態
N-STATE
時間延遲
(記憶器正反器)
CLOCK
Moore-Machine序向邏輯
Mealy-Machine序向邏輯
Moore-Machine序向邏輯 ：O/P=F(P-STATE)
輸出
信號
組合邏輯
輸入
信號
Mealy-Machine序向邏輯 ：O/P=F(I/P，P-STATE)
時間延遲
組合邏輯
(記憶器正反器)
輸入
信號
組合邏輯
N-STATE
時間延遲
(記憶器正反器)
N-STATE
現在狀態
P_STATE
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輸出
信號
組合邏輯
現在狀態
P_STATE
CLOCK
CLOCK
State Machine
State-machine model
[Basic Parts]:
Inputs
Combinational
Logic
(1)Sequential Process (SEQ_P)
State <= initial_state;
-- Initial-state setting
Outputs
State
State <= Next_state;
-- Clocked state transfer
Next_state
Clk
(2)Combinational Process (COM_P)
N_RST
(1) Output Function
1/1
Output <= express ;
(2) Next state Function
Next_state <= state;
0/0
S0
S1
0/0
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TEL:04-24517250 # 4945
1/1
範例： State Machine
Library IEEE;
Use IEEE.std_logic_1164.All;
Entity state_machine is
Port (reset, clk,X :in std_logic;
Z :out std_logic);
End entity state_machine;
Inputs
X
Combinational
Logic
State
Next_state
Clk
Architecture A1 of state_machine is
N_RST
TYPE state_type IS (S0,S1,S2,S3);
SIGNAL state,next_state : state_type :=state_type’left ;
Begin
…………………
SEQ_P: Process ………… End process SEQ_P;
Com_P: Process ………… End Process Com_P;
………………….
End architecture A1;
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Outputs
Z
Signal States Type
Signal states declaration ……
Enumerated
Architecture …… Begin 間
-- Define state and its type
TYPE state_type IS (S0,S1,S2,S3);
SIGNAL state, next_state : state_type
:= state_type’left ;
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範例： Squential Process
A state machine changes state at a clock edge
SEQ_P : Process
Begin
Wait until (clk’event and clk=‘1’); --IF N_RST=‘0’ then
State <= state_type’left; ---initialize
Else
state <= next_state;
End if ;
Inputs
Combinational
End Process SEQ_P ;
Outputs
Logic
State
Next_state
Clk
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N_RST
範例： Combinational Process
(Output and Next_state Function)… Mealy machine
COM_P:Process (X , state )
Begin
Case state is
When s0 =>
IF x= ‘0’ then ---- Mealy-m
next_state <= s0; Z<=‘0’;
Else
next_state <= s1; Z<=‘1’;
End IF;
When s1 =>
IF x= ‘0’ then
next_state <= s0; Z<=‘0’;
Else
next_state <= s1; Z<=‘1’;
End IF;
End case;
End Process SEQ_P;
Inputs
X
Outputs
Z
Combinational
Logic
State
Next_state
本例中將Next_state與
Output 寫在一起(Mealy)
1/1
0/0
S0
S1
1/1
0/0
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Case is using for state-branch judge
範例：Traffic Controller Design
System structure
System Controller
State Diagram
Major Road
Car_Sensor
Minor Road
car
timed
Start_timer
Traffic_
Major_G
Controller
Minor_G
G
Major_G
Minor_R
Clk
Start_timer
timed
Car?
y
Timer
State of system :
TYPE state_type IS (G,R);
SIGNAL state ,next_state: state_type
:= state_type’right ;
-- for safety
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n
Start_timer
R
Major_G
Minor_R
y
Timed?
n
範例： Traffic Controller
--- Using single Process --Library ieee;
Use ieee.std_logic_1164.all;
Entity traffic is
port (clk , timed, car : in std_logic;
Start_timer , Major_green,
Minor_green : out std_logic)
End traffic;
Architecture A1 of traffic is
Type state_type is (G , R);
Signal state,next_state : state_type;
Begin
Seq: Process (clk) is -- clock-driven
seq.
Begin
If clk’event and clk=’1’ then
state <= next_state;
End if ;
End process seq ;
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Com: Process (state, timed , car) is
Begin
start_timer <= ‘0’;
Case state is -- Case for next_state and o/p
determine
When G =>
Major_green <= ‘1’; Minor_green <= ‘0’;
If car =’1’ then
start_timer <=’1’; next_state <=R
Else next_state <=G
End if;
When R =>
Major_green <= ‘0’; Minor_green <= ‘1’;
If timed =’1’ then next_state <=G;
Else next_state <=R;
End if;
End Case;
End Process com;
End architecture A1;
範例： Traffic Controller
--- Moor machine --Library ieee;
Use ieee.std_logic_1164.all;
Entity traffic is
port (clk , timed, car : in std_logic;
Start_timer , Major_green,
Minor_green : out std_logic);
End traffic;
Architecture A1 of traffic is
-- for all processes
Type state_type is (G , R);
Signal state ,next_state: state_type;
Begin
Seq_p : Process (clk) is
Begin
If clk’event and clk=’1’ then
state <= next_state;
End if ; --- no Else
End process seq_p ;
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Nextstate_p : Process (state, timed , car) is
Begin
--- Next_State = F(I/P , Present_state)
Case state is
When G =>
If car =’1’ then next_state <=R；
Else next_state <=G； End if;
When R =>
If timed =’1’ then next_state <=G;
Else next_state <=R; End if;
End Case;
End Process nextstate_p;
Output_p : Process (state, car) is
--- O/P = F( Present_state) Moor-machine
Begin
start_timer <= ‘0’;
If state =G then
Major_green <= ‘1’; Minor_green <= ‘0’;
If car = ‘1’ then start_timer <= ‘1’; End if;
Else Major_green <= ‘0’; Minor_green <= ‘1’;
End if;
End Process output_p;
End architecture A1;
