What is and Why CS-352?
Goal of the course
• Introducing the basic principles of computer organization
• Introducing assembly language programming
Why is this course important?
• To design computers
• To design specific classes of applications programs
such as compilers, operating systems, and real-time applications
• To write better high-level programs
• To buy computers
Overview
Three main parts
• Basic Architecture
• Machine Language
• Some Advanced Topics
Architecture
• Bottom-up: from gates to computer
Machine Language
• RISC-MIPS assembly language
Advanced Architecture
• Pipelining
• Memory Hierarchies
• Multiprocessors
Summary: Computer System Components
Proc
Caches
Busses
adapters
Memory
Controllers
I/O Devices:
Disks
Displays
Keyboards
Networks
What is “Computer Architecture”
Computer Architecture =
Instruction Set Architecture +
Machine Organization
SOFTWARE
-- Organization of Programmable
Storage
-- Data Types & Data Structures:
Encoding & Representations
-- Instruction Set
-- Instruction Formats
-- Modes of Addressing and Accessing Data Items and Instructions
-- Exceptional Conditions
The Instruction Set: a Critical Interface
software
instruction set
hardware
Example ISAs (Instruction Set Architectures)
Digital Alpha (v1, v3)
1992-97
HP PA-RISC (v1.1, v2.0)
1986-96
Sun Sparc
(v8, v9)
1987-95
SGI MIPS
(MIPS I, II, III, IV, V) 1986-96
Intel (8086,80286,80386,
1978-96
80486,Pentium, MMX, ...)
MIPS R3000 Instruction Set Architecture (Summary)
Registers
• Instruction Categories
– Load/Store
– Computational
– Jump and Branch
– Floating Point
• coprocessor
– Memory Management
– Special
R0 - R31
PC
HI
LO
3 Instruction Formats: all 32 bits wide
OP
rs
rt
OP
rs
rt
OP
rd
sa
immediate
jump target
funct
Organization
• Capabilities & Performance
Characteristics of Principal Functional
Units
– (e.g., Registers, ALU, Shifters, Logic
Units, ...)
• Ways in which these components are
interconnected
• Information flows between components
• Logic and means by which such
information flow is controlled.
• Choreography of FUs to
realize the
ISA
• Register Transfer Level (RTL)
Description
Logic Designer's View
ISA Level
FUs & Interconnect
Example Organization
• TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20
MBus Module
SuperSPARC
Floating-point Unit
L2
$
Integer Unit
Inst
Cache
Ref
MMU
Data
Cache
CC
MBus
L64852 MBus control
M-S Adapter
SBus
Store
Buffer
Bus Interface
DRAM
Controller
SBus
DMA
SBus
Cards
SCSI
Ethernet
STDIO
serial
kbd
mouse
audio
RTC
Floppy
What is “Computer Architecture”?
Application
Operating
System
Compiler
Firmware
Instr. Set Proc. I/O system
Instruction Set
Architecture
Datapath & Control
Digital Design
Circuit Design
Layout
• Coordination of many levels of abstraction
• Under a rapidly changing set of forces
• Design, Measurement, and Evaluation
Forces on Computer Architecture
Technology
Programming
Languages
Applications
Computer
Architecture
Operating
Systems
History
Technology
DRAM
Year
Size
1980
64 Kb
1983
256 Kb
1986
1 Mb
1989
4 Mb
1992
16 Mb
1996
64 Mb
1999
256 Mb
2002
1 Gb
In ~1985 the single-chip processor (32-bit) and the
single-board computer emerged
=> workstations, personal computers,
multiprocessors have been riding this wave since
In the 2002+ timeframe, these may well look like
mainframes compared single-chip computer (maybe
2 chips)
Technology => dramatic change
• Processor
– logic capacity: about 30% per year
– clock rate:
about 20% per year
• Memory
– DRAM capacity: about 60% per year (4x every 3
years)
– Memory speed: about 10% per year
– Cost per bit: improves about 25% per year
• Disk
– capacity: about 60% per year
Log of Performance
Performance Trends
Supercomputers
Mainframes
Minicomputers
Microprocessors
Year
1970
1975
1980
1985
1990
1995
Processor Performance (SPEC)
performance now improves 50% per year (2x every 1.5 years)
350
300
RISC
Performance
250
200
RISC
introduction
150
Intel x86
100
35%/yr
50
0
1982
1984
1986
1988
1990
1992
1994
Year
Did RISC win the technology battle and lose the market war?
Applications and Languages
•
•
•
•
•
•
CAD, CAM, CAE, . . .
Lotus, DOS, . . .
Multimedia, . . .
The Web, . . .
JAVA, . . .
???
Measurement and Evaluation
Design
Architecture is an iterative process
-- searching the space of possible designs
-- at all levels of computer systems
Analysis
Creativity
Cost /
Performance
Analysis
Good Ideas
Mediocre Ideas
Bad Ideas
Why do Computer Architecture?
• CHANGE
• It’s exciting!
• It has never been more exciting!
• It impacts every other aspect of electrical
engineering and computer science
Levels of Representation (61C Review)
temp = v[k];
High Level Language
Program
v[k] = v[k+1];
v[k+1] = temp;
Compiler
lw $15,
lw $16,
sw $16,
sw $15,
Assembly Language
Program
0($2)
4($2)
0($2)
4($2)
Assembler
Machine Language
Program
0000
1010
1100
0101
1001
1111
0110
1000
1100
0101
1010
0000
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Machine Interpretation
Control Signal
Specification
ALUOP[0:3] <= InstReg[9:11] & MASK
Levels of Organization
SPARCstation 20
Computer
Workstation Design Target:
25% of cost on Processor
25% of cost on Memory
(minimum memory size)
Rest on I/O devices,
power supplies, box
Processor
Memory
Devices
Control
Input
Datapath
Output
Execution Cycle
Instruction
Obtain instruction from program storage
Fetch
Instruction
Determine required actions and instruction size
Decode
Operand
Locate and obtain operand data
Fetch
Execute
Result
Compute result value or status
Deposit results in storage for later use
Store
Next
Instruction
Determine successor instruction
The SPARCstation 20
SPARCstation 20
Memory SIMMs
Memory
Controller
SIMM Bus
MBus
MBu
s
MBu
s
Disk
Slot 1
Slot 0
MSBI
SBus
Slot 1
SBus
Slot 3
SBus
Slot 0
SBus
Slot 2
SEC
MACIO
SBus
Keyboard
Floppy
& Mouse
Disk
External Bus
Tape
SCSI
Bus
The Underlying Interconnect
SPARCstation 20
SIMM Bus
Memory
Controller
Processor/Mem Bus:
MBus
Standard I/O Bus:
SCSI Bus
Sun’s High Speed I/O Bus:
SBus
MSBI
SEC
MACIO
Low Speed I/O Bus:
External Bus
Processor and Caches
SPARCstation 20
MBus
Module
Processor
MBus
MBu
s
MBu
s
Slot 1
Registers
Datapath
Internal
Cache
Control
Slot 0
External Cache
Memory
DRAM SIMM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
SIMM Slot 7
SIMM Slot 6
SIMM Slot 5
SIMM Slot 4
SIMM Slot 3
SIMM Slot 2
SIMM Slot 1
Memory
Controller
SIMM Slot 0
SPARCstation 20
Memory SIMM Bus
Input and Output (I/O) Devices
• SCSI Bus: Standard I/O Devices
• SBus: High Speed I/O Devices
• External Bus: Low Speed I/O
Device
SPARCstation 20
Disk
SBus
Slot 1
SBus
Slot 3
SBus
Slot 0
SBus
Slot 2
SBus
SEC
MACIO
Keyboard
Floppy
& Mouse
Disk
External Bus
Tape
SCSI
Bus
Standard I/O Devices
SPARCstation 20
• SCSI = Small Computer Systems Interface
• A standard interface (IBM, Apple, HP, Sun
... etc.)
• Computers and I/O devices communicate
with each other
• The hard disk is one I/O device resides on
the SCSI Bus
Disk
Tape
SCSI
Bus
High Speed I/O Devices
SPARCstation 20
• SBus is SUN’s own high speed I/O bus
• SS20 has four SBus slots where we can plug
in I/O devices
• Example: graphics accelerator, video adaptor,
... etc.
• High speed and low speed are relative terms
SBus
Slot 1
SBus
Slot 3
SBus
Slot 0
SBus
Slot 2
SBus
Slow Speed I/O Devices
SPARCstation 20
• The are only four SBus slots in SS20--”seats” are
expensive
• The speed of some I/O devices is limited by human
reaction time--very very slow by computer
standard
• Examples: Keyboard and mouse
• No reason to use up one of the expensive SBus slot
Keyboard
Floppy
& Mouse
Disk
External Bus