Technion
Electrical Engineering Department
High Speed Digital System Lab
FPGA Setting
Using FLASH
Project Documentation
Students: Dor Obstbaum
Kami Elbaz
Advisor: Moshe Porian
Project initiation: March 2011
Last update: November 2012
Table of content
1
Scope ................................................................................................................................. 7
2
Abbreviations .................................................................................................................... 7
3
General Description ........................................................................................................... 7
4
Top Architecture ................................................................................................................ 8
5
Project Requirements ........................................................................................................ 9
6
Block Details .................................................................................................................... 11
6.1
RX path ................................................................................................................... 11
6.1.1
UART RX ........................................................................................................... 12
6.1.2
Message Pack Decoder (mp_dec) ................................................................... 13
6.1.3
RAM ................................................................................................................. 14
6.1.4
CRC................................................................................................................... 14
6.1.5
Error Register ................................................................................................... 15
6.2
TX path ................................................................................................................... 16
6.2.1
BUS to encoder FSM ........................................................................................ 18
6.2.2
Message encoder ............................................................................................ 19
6.2.3
RAM ................................................................................................................. 20
6.2.4
CRC................................................................................................................... 20
6.2.5
FIFO .................................................................................................................. 20
6.2.6
UART TX ........................................................................................................... 21
6.3
Config Control Block ............................................................................................. 22
6.3.1
CCB_FSM ........................................................................................................ 24
6.3.2
RAM ................................................................................................................. 25
6.3.3
Wishbone master .......................................................................................... 25
6.4
Flash Control ......................................................................................................... 26
6.4.1
Flash FSM ......................................................................................................... 28
6.4.2
Flash Controller ............................................................................................... 30
6.4.3
Reset_enabler.................................................................................................. 31
6.4.4
RAM ................................................................................................................. 32
6.4.5
Wishbone slave................................................................................................ 32
6.5
Clock and Reset ..................................................................................................... 33
6.6
Filter ........................................................................................................................ 35
6.7
Wait - client ........................................................................................................... 37
6.7.1
6.8
LED – client ............................................................................................................ 39
6.8.1
Led Registers.................................................................................................... 40
6.8.2
LED ................................................................................................................... 42
6.9
Display – client ...................................................................................................... 43
6.9.1
Wishbone Slave ............................................................................................... 44
6.9.2
Display Registers .............................................................................................. 44
6.9.3
VESA generator ................................................................................................ 45
6.9.4
Synthetic data provider ................................................................................... 46
6.9.5
Synchronizer and clock domain crossing......................................................... 47
6.9.6
Interface, Generics and Waveform ................................................................. 49
6.10
7.
Timer................................................................................................................ 38
Wishbone Blocks and protocol ........................................................................... 51
6.10.1
Wishbone Protocol .......................................................................................... 51
6.10.2
Wishbone Intercon .......................................................................................... 53
6.10.3
Wishbone Master ............................................................................................ 54
6.10.4
Wishbone Slave ............................................................................................... 56
Graphic User Interface (GUI) ...................................................................................... 59
7.1
7.2
Getting Started ........................................................................................................ 59
FLASH Basic operations ............................................................................................... 60
7.2.1
Building a FLASH Data base (FLASH DB) .............................................................. 61
7.2.2
Register directed transactions............................................................................. 62
Write transaction............................................................................................................. 62
Read transaction.............................................................................................................. 62
8
7.3
Limitations ............................................................................................................... 62
7.4
Debug operations .................................................................................................... 63
7.4.1
Sending data from a text file ........................................................................... 63
7.4.2
Saving rx and TX data to file ............................................................................ 64
7.4.3
Changing or removing CRC, SOF, EOF.............................................................. 64
Data transfer ................................................................................................................. 65
8.1
Write transaction.................................................................................................. 65
Registers Write Message ................................................................................................. 65
Write transaction example .............................................................................................. 66
8.2
Read transaction ................................................................................................... 67
Registers Read Request ................................................................................................... 67
Registers Read Reply ....................................................................................................... 67
9
FLASH Memory .............................................................................................................. 69
10
Testability .................................................................................................................. 70
11
Synthesis .................................................................................................................... 72
11.1
Debugging the hardware ..................................................................................... 73
12
Project educational value ........................................................................................ 74
13
System analysis ......................................................................................................... 75
13.1
Reducing the total number of cycle in transaction: ............................................... 75
13.2
Parallelism ............................................................................................................... 76
13.3
Watchdog ................................................................................................................ 76
14
An application example ........................................................................................... 77
15
Appendix .................................................................................................................... 78
Table of Tables
Table 1 - RX path interface ...................................................................................................... 12
Table 2 - Uart rx interface........................................................................................................ 12
Table 3 - Uart rx generics......................................................................................................... 12
Table 4 - mp_dec interface ...................................................................................................... 13
Table 5 - mp_dec generics ....................................................................................................... 14
Table 6 - RAM interface ........................................................................................................... 14
Table 7- RAM generics ............................................................................................................. 14
Table 8 - CRC interface ............................................................................................................ 14
Table 9 - CRC generics ............................................................................................................. 14
Table 10 - Error Register interface .......................................................................................... 15
Table 11 - Error register generics ............................................................................................ 15
Table 12 - TX Path interface ................................................................................................... 17
Table 13 - TX Path generics ..................................................................................................... 17
Table 14 - BUS to encoder FSM interface ............................................................................... 18
Table 15 - BUS to encoder generic .......................................................................................... 19
Table 16 - message encoder signals ........................................................................................ 20
Table 17 - message encoder generics ..................................................................................... 20
Table 18 - FIFO signals ............................................................................................................. 21
Table 19 - FIFO Generics .......................................................................................................... 21
Table 20 - UART_TX signals ..................................................................................................... 21
Table 21 - Config Control Block interface ................................................................................ 23
Table 22 -Config Control block generics .................................................................................. 24
Table 23 - CCB FSM interface .................................................................................................. 25
Table 24 - CCB FSM generics ................................................................................................... 25
Table 25 - FLASH command encoding ..................................................................................... 26
Table 26 - Flash controle interface .......................................................................................... 27
Table 27 - Flash control generics ............................................................................................. 28
Table 28 - Flash FSM interface ................................................................................................ 29
Table 29 - Flash FSM generics ................................................................................................. 29
Table 30 - Flash Controller interface ....................................................................................... 31
Table 31 - Flash controller generics ........................................................................................ 31
Table 32 - reset enabeler interface ......................................................................................... 31
Table 33 - reset enabler generics ............................................................................................ 32
Table 34 - clock and reset interface ........................................................................................ 34
Table 35 - clock and reset generics ......................................................................................... 34
Table 36 -Filter interface ......................................................................................................... 35
Table 37 - Filter generics ......................................................................................................... 36
Table 38 - wait client signals.................................................................................................... 37
Table 39 - wait client generics ................................................................................................. 38
Table 40 - wait_client_int interface ........................................................................................ 38
Table 41 - wait_client_int generics ......................................................................................... 38
Table 42 - Timer interface ....................................................................................................... 38
Table 43 - Timer generics ........................................................................................................ 38
Table 44 - Led client interface ................................................................................................. 39
Table 45 - Led client generics .................................................................................................. 40
Table 46 - Led register mapping .............................................................................................. 40
Table 47 - Led Registers interface ........................................................................................... 41
Table 48 - Led Registers generics ............................................................................................ 41
Table 49 - Led interface ........................................................................................................... 42
Table 50 - Led generics ............................................................................................................ 42
Table 51 - Display Registers ..................................................................................................... 45
Table 52 - VESA enable_reg mapping...................................................................................... 45
Table 53 - Display Client Signals ............................................................................................. 50
Table 54 - Display Client Generics ........................................................................................... 51
Table 55 - Wishbone Master interface .................................................................................... 56
Table 56 - Wishbone Master generics ..................................................................................... 56
Table 57 - whishbone slave interface ...................................................................................... 58
Table 58 - Wishbone Slave generics ........................................................................................ 58
Table 59 - System registers...................................................................................................... 62
Table 60 - Register Write Messag ........................................................................................... 65
Tables of Figures
Figure 1 - Top Architecture........................................................................................................ 8
Figure 2 - RX path .................................................................................................................... 11
Figure 3 - TX path..................................................................................................................... 16
Figure 4 - BUS to encoder FSM ................................................................................................ 18
Figure 5 - Pack stored in CCB RAM .......................................................................................... 22
Figure 6 - Config Control Block ................................................................................................ 23
Figure 7 - CCB FSM .................................................................................................................. 24
Figure 8 - Flash control ............................................................................................................ 27
Figure 9 - Flash FSM................................................................................................................. 28
Figure 10 - Flash Controller FSM ............................................................................................. 30
Figure 11 - clk& reset............................................................................................................... 33
Figure 12 - Filter ...................................................................................................................... 35
Figure 13 - wait calient ............................................................................................................ 37
Figure 14 - LED client ............................................................................................................... 39
Figure 15 - Led waveform ........................................................................................................ 41
Figure 16 - Led unit .................................................................................................................. 42
Figure 17 - Display Client ......................................................................................................... 43
Figure 18 - Display resolution and ROI .................................................................................... 43
Figure 19 - Synthetic Data Provider......................................................................................... 46
Figure 20 - System optional pictures ....................................................................................... 46
Figure 21 - unwanted frames .................................................................................................. 47
Figure 22 - Synchronizer .......................................................................................................... 47
Figure 23 - Display Client Clock Domain Crossing ................................................................... 48
Figure 24 - Display client waveform ........................................................................................ 49
Figure 25 - Wishbone cycle waveform example ..................................................................... 52
Figure 26 - Wishbone Intercon ................................................................................................ 53
Figure 27 - Connecting a Wishbone Master ............................................................................ 54
Figure 28 - Wishbone Master FSM .......................................................................................... 55
Figure 29 - Connecting a Wishbone Slave ............................................................................... 57
Figure 30 - GUI layout .............................................................................................................. 59
Figure 31 - FLASH basic operations ......................................................................................... 60
Figure 32- FLASH DB building .................................................................................................. 61
Figure 33 -Packet Creation ...................................................................................................... 62
Figure 34- Sending data from a texts file ............................................................................... 63
Figure 35 - Saving rx and tx data to file .................................................................................. 64
Figure 36 - Changing or removing CRC, SOF, EOF................................................................... 64
Figure 37 –Waveform - DATA PROCCESSED IN THE RX PATH ................................................. 66
Figure 38 – Waveform - Data transfer from rx_path to led client .......................................... 67
Figure 39- Flash schematic symbol and schematics ................................................................ 69
Figure 40 - Top level Test Environment................................................................................... 70
Figure 41- Quartus Synthesis results ....................................................................................... 72
Figure 42 - Quartus timing analysis ......................................................................................... 72
Figure 43 - Address advancer - error causing code ................................................................ 73
1 Scope
This document aims to describe the structure of the FPGA setting using FLASH project. It
provides explanation of logic blocks, signals, functions. Documentation of all parts of the
project including testability and software is found in this document.
2 Abbreviations
CCB – Config Control Block
RAM - Random Access Memory
TX – Transmission
RX – Receive
SOF – Start of Frame
EOF – End of Frame
CRC – Cyclic Redundancy Check
FCB - Flash Control Block
IWB - Intercon Wishbone Block
EOD – End of Data
CFI - Common Flash Interface
FSM – Final State Machine
WM – Wishbone Master
WS – Wishbone Slave
VESA - Video Electronics Standards Association
ROI - Region Of Interest
3 General Description
The FPGA setting using FLASH Project consists of 3 main parts: a software component (host),
hardware on FPGA, and FLASH memory. The software component is a MATLAB based GUI
for writing, reading, and erasing data on the FLASH memory. The hardware on the FPGA is
the link between the software and the FLASH memory. It reads data stored in FLASH once
power is turned on and configures on board clients. A client is a functional hardware block,
for example: the Display client which produces a picture on a screen using VESA protocol.
The internal communication uses Wishbone protocol so connecting a client is very easy if
the client has a Wishbone interface. Communication between the host and the hardware is
done via UART protocol.
4 Top Architecture
Figure 1 - Top Architecture
5 Project Requirements
1. Configuration of clients in the FPGA would be determined by data stored and read
from FLASH.
2. Designated board is an Altera DE2 board that features an Altera Cyclone® II 2C35
FPGA.
3. System clock will be 100MHz. will be generated by a PLL from a 50MHz oscillator
onboard the DE2 card. The Display client uses a 65MHz clock also generated by the
same PLL.
4. The System would enable a Host to read and write data to FLASH and clients through
FPGA.
5. The FPGA will communicate with its PC host via UART protocol with baud rate of
115,200 bits/sec.
6. UART protocol:
a. Line not active = '1'
b. 8 bits will be wrapped by start bit, represented by '0', and stop bit,
represented by '1'.
c. Parity bit will be used in order to verify the bit physical transmission :
i. Odd - a bit will be added so the total '1' bits will be odd.
ii. Even - a bit will be added so the total '1' bits will be even.
iii. Inhibited.
7. Message Pack Structure transferred on UART lines:
a. SOF - Start of Frame: “00111100” (0x3C)– one byte.
b. Type – Indicates which client is being accessed - one byte.
c. Address – Address of the register in a client – tree byte.
d. Length - Number of Bytes of Data - two bytes.
e. Data – Data written or read from registers in clients or from the FLASH [length] bytes.
f. CRC - A check if a successful data transfer was made. CRC will be calculated
on the TYPE, ADDRESS, LENGTH and DATA blocks, in that order – one byte.
g. EOF - End of Frame: “10100101” (0xA5)– one byte.
8. Internal Communication using Wishbone protocol.
 Bus width: 8 bits
 Units with wishbone master interfaces: RX path, TX path, CCB
 Units with wishbone slave interfaces: TX path, Wait, LED, VIDEO, Flash control
 The wishbone work with a pipeline mode.
 The wishbone contains watchdog timers that avoid a system hang.
 The transactions used are:
- Read single
- Write single
- Read burst
- Write burst
9. The FLASH memory being used is 4MB Spansion.
10. Tree client can be recruited to active (as slaves):
 Wait: this client roll is to occupy the bus for given time.
 Led: this client will be used to operate 4 leds at different frequencies.
 Display: this client will control an external screen according to configuration
stored in the registers.
11. The reset of the system is filtered, and then sampled in the clock rate.
12. Signals connected to DE2 switches would be filtered in order to avoid an unstable
signal in the system. The signal CCB_disable would be filtered in the Filter block. The
signal Reset_in would be filtered in the CLK&Reset block.
13. A sleep switch will disable the PLL in the CLK&RST, and as a result, the reset will be
active.
14. The FLASH size is 4M. In the initial of the system the FLASH will transmit 256 bytes to
the CCB, where the data will be saved.
15. Data can be read, write and be erased from the FLASH.
16. The data base in the flash will begin with type and then address, length, data. The
fields meaning are as mentioned on section 7. The last pack would contain EOD (not
EOF!) in the Type field. When the CCB state machine reads the EOD value, client
configuration will end. Data transfer is explained in detail in the “Data Transfer”
section in this document.
EOD: “11110000”
Example for data pack structure:
Type
Led
Len
2
address
0
data
0
data
1
The following pack configures one led turned off and one turned on in the led block.
The values in this example are listed as decimal.
6 Block Details
6.1 RX path
Figure 2 - RX path
General Description
The RX Path processes data received from the host. It unwraps the data before it is
transferred to the CCB or other clients of the bus.
signal name
sys_clk
type
input
width (bits)
1
system clock
sys_reset
description
input
1
system reset
rx_din
input
1
input of UART data
error_led_out
output
1
‘1' when one of the error bits in the register is high
flash_error
input
1
error signal from flash client - directed to error register
ADR_O
output
addr_d_g * data_width_g
contains the address word
DAT_O
output
data_width_g
contains the data_in word
WE_O
output
1
'1' for write, '0' for read
STB_O
output
1
‘1' for active bus operation, '0' for no bus operation
CYC_O
output
1
'1' for bus transmition request, '0' for no bus transmition request
TGA_O
output
type_d_g * data_width_g
contains the type word
TGD_O
output
len_d_g * data_width_g
contains the length word
ACK_I
input
1
DAT_I
input
data_width_g
'1' when valid data is received from WS or for successful write operation
in WS
data received from WS
STALL_I
input
1
STALL - WS is not available for transaction
ERR_I
input
1
Watchdog interrupts, resets wishbone master
ADR_I
input
addr_d_g * data_width_g
WE_I
input
1
'1' for write, '0' for read
STB_I
input
1
‘1' for active bus operation, '0' for no bus operation
CYC_I
input
1
'1' for bus transmition request, '0' for no bus transmition request
TGA_I
input
type_d_g * data_width_g
contains the type word
TGD_I
input
len_d_g * data_width_g
contains the length word
ACK_O
output
1
DAT_O
output
data_width_g
contains the address word
1' when valid data is transmitted to MW or for successful write
operation
data transmit to MW
Table 1 - RX path interface
The generics of the rx_path are all its sub-units generics.
The RX path contains the following units:
6.1.1 UART RX
This unit receives data via UART protocol. It converts the data received on the UART serial
line to an 8 bit vector [dout] and sends it to the mp_dec (message pack decoder unit). When
the data is sent a valid signal is asserted. The uart_rx also detects two types of errors:
1. Stop_bit_error – if the stop bit is different than ‘1’.
2. Parity_bit_error – if the parity bit is different from the parity
result calculated in the unit.
The errors are sent to the error register in the rx_path and could be read later. An error
assertion won’t interrupt the continuation of the data transfer.
signal name
type
width (bits)
description
clk
input
1
system clock
Reset
input
1
block reset
Din
input
1
UART serial input
Dout
output
8
Parallel data out
valid
output
1
Parallel data valid
parity_err
output
1
parity error
stop_bit_err
output
1
Stop bit error
Table 2 - Uart rx interface
Actual value
generic name
parity_en_g
type
natural
parity_odd_g
Boolean
0
False
std_logic
‘1’
IDLE_ST line value
positive
115200
UART baudrate [Hz]
positive
100000000
Sys. clock [Hz]
natural
8
Number of databits
std_logic
1
uart_idle_g
baudrate_g
clkrate_g
databits_g
reset_polarity_g
description
1 to Enable parity bit, 0 to disable parity bit
TRUE = odd, FALSE = even
'0' = Active Low, '1' = Active High
Table 3 - Uart rx generics
6.1.2 Message Pack Decoder (mp_dec)
The mp_dec receives the [dout] vector transferred from the uart_rx unit and prepares the
data before transfer. It detects the start of the transmition (3C_0x) then it checks in the
TYPE, ADDRESS, LENGTH data to registers. The data that will be transferred is saved on the
RAM. Finally it requests a CRC check. After receiving the EOF byte (A5_0x) it asserts the
mp_done signal that informs the wishbone master to start the data transfer.
The mp_dec detects two types of errors:
1- Eof_error – if the EOF byte is different from A5_0x
2- Crc_error – if the CRC error received is different from the one calculated by the CRC
block.
signal name
type
width (bits)
description
Clk
input
1
clock
Rst
input
1
reset
Din
input
width_g
Input data
Valid
input
1
Data valid
mp_done
output
1
Message Pack has been received
eof_err
output
1
EOF has not found
crc_err
output
1
CRC error
type_reg
output
width_g * type_d_g
type register
addr_reg
output
width_g * addr_d_g
address register
len_reg
output
width_g * len_d_g
length register
data_crc_val:
output
1
data_crc
output
width_g
reset_crc
output
1
'1' to reset CRC value
req_crc
output
1
'1' to request for current calculated CRC
crc_in
input
width_g * crc_d_g
crc_in_val
input
1
'1' when CRC is valid
write_en
output
1
1' = Data is available (width_g length)
write_addr
output
width_g * len_d_g
Dout
output
generic name
reset_polarity_g
data_width_g
clkrate_g
type
std_logic
natural
positive
len_dec1_g
sof_d_g
type_d_g
addr_d_g
len_d_g
crc_d_g
Boolean
positive
positive
positive
positive
positive
eof_d_g
sof_val_g
eof_val_g
positive
natural
natural
'1' when new data for CRC is valid, '0' otherwise
Data to be calculated by CRC
CRC value
RAM Address
width_g
Data to RAM
Table 4 - mp_dec interface
Actual value
1
8
100000000
True
1
1
3
1
1
1
60
165
description
'0' = Active Low, '1' = Active High
defines the width of the data lines of the system
Sys. clock [Hz]
TRUE - Received length is decreased by 1 ,to save 1 bit -FALSE - Received length is the actual length
SOF Depth
Type Depth
Address Depth
Length Depth
CRC Depth
EOF Depth
(3Ch) SOF block value. Upper block is MSB
(A5h) EOF block value. Upper block is MSB
width_g
8
8
positive
positive
Data Width (UART = 8 bits)
RAM size in bytes(2^8 = 256bytes)
Table 5 - mp_dec generics
6.1.3 RAM
A 256 byte RAM.
signal name
type
width (bits)
description
Clk
input
1
clock
Rst
input
1
reset
addr_in
input
addr_bits_g
Input address
addr_out
input
addr_bits_g
Output address
aout_valid
input
1
data_in
din_valid
data_out
dout_valid
input
input
output
output
generic name
reset_polarity_g
data_width_g
clkrate_g
addr_bits_g
Output address is valid
width_in_g
Input data
1
Input data valid
width_in_g
Output data
1
Output data valid
Table 6 - RAM interface
Actual value
type
1
8
100000000
8
std_logic
natural
positive
positive
description
'0' = Active Low, '1' = Active High
defines the width of the data lines of the system
Sys. clock [Hz]
Depth of data (2^10 = 1024 addresses)
Table 7- RAM generics
6.1.4 CRC
A block that calculates the CRC value of the data transferred to it. The mp_dec uses this
block for comparing the CRC value received with the one calculated. The system uses an 8
degree polynomial calculation.
The CRC polynomial is 0xEA  x 7  x 6  x5  x3  x
Clk
Rst
signal name
type
input
input
Soc
input
1
start of calculation
Data
input
8
data in
data_valid
input
1
data in valid
Eoc
input
1
end of calculation
Crc
output
8
crc value
crc_valid
output
1
generic name
reset_polarity_g
data_width_g
clkrate_g
width (bits)
1
1
description
clock
reset
crc value validity
Table 8 - CRC interface
Actual value
type
1
std_logic
8
natural
100000000
positive
Table 9 - CRC generics
description
'0' = Active Low, '1' = Active High
defines the width of the data lines of the system
Sys. clock [Hz]
Wishbone Master
See Wishbone Master at wishbone units.
Wishbone Slave
See Wishbone Slave at wishbone units.
6.1.5 Error Register
Samples an 8 bit vector of error bits. The error vector is sampled every cycle and saved in a
register. When the rx_path’s requests the value of the register it is transferred to it and
being set to zero on the following cycle. The unit also asserts the error_led_out signal – it is
an OR operation on the error register saved bits. If this signal is ‘1’ a led would be lightened,
meaning that at least one error has occurred.
The Error Register actually contains two register. Register #1 contains the code version.
Register #0 contains the error bits which have occurred:
On the current configuration:
Error_in[0] – stop_bit_error
Error_in[1] - parity_error
Error_in[2] – eof_error
Error_in[3] – crc_error
Error_in[4] – FLASH timeout
Error_in[5..7] – not in use, set to ‘0’
signal name
Clk
Rst
error_in
error_led_out
data_out
valid_data_out
address_in
valid_in
wr_en
type
input
input
input
output
output
output
input
input
input
generic name
width (bits)
description
1
clock
1
reset
data_width_g
error vector
1
'1' when one of the error bits in the register is high
data_width_g
data sent to WS
1
validity of data directed to WS
address_width_g
address line
1
validity of the address directed from WS
1
enables reading the error register
Table 10 - Error Register interface
reset_polarity_g
data_width_g
address_width_g
type
std_logic
natural
natural
led_active_polarity_g
std_logic
error_register_address_g
natural
error_active_polarity_g
code_version_g
std_logic
natural
Actual value
1
8
8
1
0
1
description
'0' = Active Low, '1' = Active High
defines the width of the data lines of the system
defines the width of the address lines of the system
defines the active state of the error signal input: '0' active
low, '1'
defines the address that should be sent on access to the
unit
defines the polarity which the error signal is active in
0
Hardware code version
Table 11 - Error register generics
6.2 TX path
Figure 3 - TX path
General Description
The TX is activated when a read transaction is occurring.
The TX (via wishbone slave) is informed that there is a read request, the Bus_To_Enc_Fsm
receive the data request properties, transmit them to the Message Pack Encoder, and store
the data in the RAM. Afterwards, the slave will upraise acknowledge . Then the master of the
TX is activated and asks to read the required data from the FLASH or from one CLIENT.
When the TX master receives the data he wraps it in the form of the message pack structure
according to the type, address and length than Transferred over to him.
signal name
type
width (bits)
Description
clk
input
1
system clock
reset
input
1
system reset
DAT_I_S
input
(data_width_g)*(addr_d_g)
data inpute from the RX via the WB slave to the RAM
ADR_I_S_TX
input
(data_width_g)*(type_d_g)
address where the data will be write
TGA_I_S_TX
input
(data_width_g)*(len_d_g)
the type of the client that the data come from
TGD_I_S_TX
input
1
the length of the data
WE_I_S_TX
input
1
STB_I_S_TX
input
1
write enable to the RAM
1' for active bus operation, '0' for no bus operation
CYC_I_S_TX
input
1
ACK_O_TO_M
output
1
1' for bus transmition request, '0' for no bus transmition request
1' when the data were successfully write
DAT_O_TO_M
output
data_width_g
data output via WM to client
STALL_O_TO_M
output
1
stall - suspend wishbone transaction
DAT_I_CLIENT
input
data_width_g
data inpute from the client
ACK_I_CLIENT
input
1
ack from the client's slave
STALL_I_CLIENT
input
1
stall - suspend wishbone transaction from client WS
ERR_I_CLIENT
ADR_O_CLIENT
input
output
1
data_width_g)*(addr_d_g)
Watchdog interrupts, resets wishbone master
address to the WS client
DAT_O_CLIENT
output
data_width_g
data required by the client
WE_O_CLIENT
output
1
write enable to the client
STB_O_CLIENT
output
1
1' for active bus operation, '0' for no bus operation
CYC_O_CLIENT
output
1
1' for bus transmition request, '0' for no bus transmition request
TGA_O_CLIENT
output
(data_width_g)*(type_d_g)
the type of the client to be send the data to
TGD_O_CLIENT
output
(data_width_g)*(len_d_g
the length of the send data
uart_out
output
1
the UART signal output from the system, to the host
Table 12 - TX Path interface
Generic Parameter
reset_polarity_g
type
std_logic
1
Actual value
Description
'0' = Active Low, '1' = Active High
data_width_g
addr_d_g
natural
positive
8
3
defines the width of the data lines of the system
Address Depth
len_d_g
type_d_g
fifo_d_g
addr_bits_g
positive
positive
positive
positive
1
Length Depth
1
Type Depth
9
Maximum elements in FIFO
8
Depth of data
Table 13 - TX Path generics
6.2.1 BUS to encoder FSM
The BUS to encoder FSM unit is an interface between a Wishbone Bus and the message pack
encoder. Once a read request has arrived from WS, the unit asks the WM to read data from
the requested client on the bus. WM writes the data to RAM. When data reading is finished
the unit asserts the reg_ready signal for the message pack encoder to start reading data
from RAM.
Figure 4 - BUS to encoder FSM
signal name
type
width (bits)
description
Clk
input
1
system clock
reset
input
1
system reset
typ
input
(data_width_g)*(type_d_g)
Type
addr
input
(data_width_g)*(addr_d_g)
the beginning address in the client that the information will be written to
ws_data
input
data_width_g
data out to registers
ws_data_valid
input
1
data valid to registers
active_cycle
input
1
CYC_I outputed to user side
stall
output
1
stall - suspend wishbone transaction
wm_start
output
1
when '1' WM starts a transaction
wr
output
1
determines if the WM will make a read('0') or write('1') transaction
type_in
output
type_d_g * data_width_g
type is the client which the data is directed to
len_in
output
len_d_g * data_width_g
length of the data (in words)
addr_in
output
addr_d_g * data_width_g
the address in the client that the information will be written to
ram_start_addr
output
addr_bits_g
start address for WM to read from RAM
wm_end
reg_ready
input
output
1
1
when '1' WM ended a transaction or reseted by watchdog ERR_I signal
Registers are ready for reading. MP Encoder can start transmitting
type_mp_enc
output
data_width_g * type_d_g
Type register
addr_mp_enc
output
data_width_g * addr_d_g
Address register
len_mp_enc
output
data_width_g * len_d_g
Length Register
mp_done
input
1
Message Pack has been transmitted
Table 14 - BUS to encoder FSM interface
Generic Parameter
reset_polarity_g
type
std_logic
0
Actual value
reset active polarity
Description
data_width_g
addr_d_g
natural
positive
8
3
defines the width of the data lines of the system
Address Depth
len_d_g
type_d_g
addr_bits_g
reset_polarity_g
positive
positive
positive
std_logic
1
1
8
0
Length Depth
Type Depth
Depth of data in RAM
reset active polarity
Table 15 - BUS to encoder generic
6.2.2 Message encoder
Message Pack Decoder Encoder transmits data from the Type and Address registers, and
from the RAM, in a Message Pack format, wraps it and transfer the date to the UART.
This block also produces ‘mp_done’ that signal the Bus_To_Enc_Fsm while the present
transaction is still running. When the mp_done will drop to ‘0’ the Bus_To_Enc_Fsm won’t
try to write new message to the Message Encoder, but only after this signal will turn to ‘1’.
This unit also receives write enable, to allow writing the data to the RAM.
Pin Name
Clk
Rst
Direction
In
In
1
1
Fifo_full
Reg_ready
Type_reg
In
In
In
1
1
width_g * type_d_g
Addr_reg
In
width_g * addr_d_g
Len_reg
In
width_g * len_d_g
Crc_in
In
width_g * crc_d_g
Description
Clock
Reset. Reset polarity will be set according to the generic
parameter 'reset_polarity_g'
FIFO is full, and cannot receive more data from MP Encoder
Input Type, Address and Data Length registers values are ready
Input Type value. Will be valid together with the reg_ready
signal
Input Address value. Will be valid together with the reg_ready
signal
Input Data Length value. Will be valid together with the
reg_ready signal
Calculated CRC value from Checksum block
Crc_in_val
In
1
Calculated CRC value from Checksum block is valid
Din
In
Width_g
Input data (payload), from RAM
Din_valid
In
1
Input data (payload), from RAM is valid
Mp_done
Out
1
Dout
Out
Width_g
Message Pack has been successfully transmitted. This flag will
be raised together with the EOF output data
Output data, to the FIFO
Dout_valid
Out
1
Output data, to the FIFO, is valid
Data_crc_val
Out
1
Data to the CRC block is valid
Data_crc
Out
width_g
Data to the CRC, for CRC calculation
Reset_crc
Out
1
Reset the CRC value to its default value
Req_crc
Out
1
Request for calculated CRC value
Read_addr_en
Out
1
Address to RAM is valid
Read_addr
Out
width_g * len_d_g
Address to RAM
Table 16 - message encoder signals
Generic Parameter
Reset_polartiy_g
type
Std_logic
'0'
Actual value
Description
Reset active in this polarity
Len_dec1_g
Boolean
true
Sof_d_g
Type_d_g
positive
positive
1
1
TRUE to receive decreased length by 1. For example: in case actual
length is 6, 5 will be received.
SOF block depth
Type block depth
Addr_d_g
positive
3
Address block depth
Len_d_g
positive
2
Length block depth
Crc_d_g
positive
1
CRC block depth
Eof_d_g
positive
1
EOF block depth
Sof_val_g
natural
100
Initial SOF value (decimal = 64hex)
Eof_val_g
natural
200
Initial EOF value (decimal = C8hex)
Width_g
positive
8
Data width (number of bits)
Table 17 - message encoder generics
6.2.3 RAM
A 256 byte RAM. See signal and generics list at the RX path.
6.2.4 CRC
The CRC receive the data from the Message encoder, calculate it’s CRC value, return it to
the Message Encoder which insert the CRC value into the UART package. See signal and
generics list at the TX Path.
6.2.5 FIFO
This block is a general FIFO, it receiving from the message encoder the data and arrange it in
a queue before it arrive to the UART.
signal name
clk
Reset
Din
rd_en
Flush
Dout
type
input
input
input
input
input
output
width (bits)
1
1
width_g
1
1
width_g
description
system clock
block reset
Input Data
Read Enable (request for data)
Flush data
Output Data
Dout_valid
Afull
Full
output
output
output
1
1
1
Output data is valid
FIFO is almost full
FIFO is full
Aempty
Empty
output
output
1
1
Used
output
log_depth_g
FIFO is almost empty
FIFO is empty
Current number of elements is FIFO. Note the range. In case depth_g
is 2^x, then the extra bit will be used
Table 18 - FIFO signals
Generic Parameter
Reset_polartiy_g
width_g
type
Std_logic
positive
'0'
8
Actual value
Description
Reset active in this polarity
Width of data
depth_g
log_depth_g
positive
natural
9
4
almost_full_g
positive
8
Maximum elements in FIFO
Logarithm of depth_g (Number of bits to represent depth_g. 2^4=16 >
9)
Rise almost full flag at this number of elements in FIFO
almost_empty_g
positive
1
Rise almost empty flag at this number of elements in FIFO
Table 19 - FIFO Generics
6.2.6 UART TX
Receiving the data wrapped from the MESSAGE ENCODER and transmits it out to the HOST.
The UART require rate of 115,200 Kbit/sec.
signal name
type
width (bits)
description
clk
input
1
system clock
Reset
input
1
block reset
Din
input
databits_g
Parallel data in
fifo_din_valid
input
1
FIFO Ready to transmitted new data to TX
fifo_empty
input
1
FIFO is not empty
fifo_rd_en
output
1
Controls FIFO rd_en
Dout
output
1
Serial data out
Table 20 - UART_TX signals
See generics list at the RX Path.
Wishbone Master
See Wishbone Master at wishbone units.
Wishbone Slave
see Wishbone Slave at wishbone units.
6.3 Config Control Block
General Description
1.
2.
3.
4.
5.
6.
The Config Control Block (CCB) has a wishbone master interface (WBM 3), a final
state machine (CCB_FSM) and a RAM.
Clock: sys_clk (100MHz)
When power is turned on the CCB would initiate a transaction to Flash control (WBS
6), causing the data stored in the Flash to be transferred by the wishbone Bus to the
CCB.
The data from the Flash would be stored in an internal RAM in the CCB, before it is
transferred to the clients. RAM size is 256 rows x 8 bits.
When all the data from Flash is stored in the RAM, it will be sent to the clients. The
data transfer would include the following fields defined in generics:
- Type – which client is being accessed – 1byte
- Len – length of data in bytes –1 bytes
- Add – address of registers in clients – 3 byte
- Data – the data being transferred – [len] x bytes
- EOD – End Of Data 0x7D (01001101) - When the CCB reads this Type data
transfer stops– 1 byte
CCB switches:
CCB switches are signals which the user sets their value by a switch on DE2 board.
Both signals go through a filter block, thus need to be stable for a time defined by
generic (stable_time_g).
CCB_disable: prevents the CCB from accessing FLASH control and configuring clients
once power is on. The signal is active on ccb_disable_polarity_g.
Config_again: on rising or falling edge (defined by config_again_polarity_g generic)
all the clients are reseted and the CCB reconfigures the clients by the data in its RAM
(doesn’t make another transaction to FLASH control).
7. Data pack structure stored in the CCB RAM has the following format:
Figure 5 - Pack stored in CCB RAM
Figure 6 - Config Control Block
signal name
type
width (bits)
description
sys_clk
input
1
system clock
sys_reset
input
1
system reset
ccb_disable
input
1
disables ccb data upload from flash
config_again
input
1
configures clients again from data already stored in the RAM
client_reset
output
1
resets clients on when user chooses config_again
ADR_O
output
addr_d_g * data_width_g
contains the addr word
DAT_O
output
data_width_g
contains the data_in word
WE_O
output
1
'1' for write, '0' for read
STB_O
output
1
'1' for active bus operation, '0' for no bus operation
CYC_O
output
1
1' for bus transmition request, '0' for no bus transmition request
TGA_O
output
type_d_g * data_width_g
contains the type word
TGD_O
output
len_d_g * data_width_g
contains the len word
ACK_I
input
1
1 - valid data is received from WS or successful write operation
DAT_I
input
data_width_g
data received from WS
STALL_I
input
1
STALL - WS is not available for transaction
ERR_I
input
1
Watchdog interrupts, resets wishbone master
Table 21 - Config Control Block interface
Generic Parameter
reset_polarity_g
data_width_g
type_d_g
addr_d_g
len_d_g
addr_bits_g
ccb_disable_polarity_g
config_again_polarity_g
eod_g
initial_address_g
reset_cycles_g
type
std_logic
natural
positive
positive
positive
positive
std_logic
std_logic
std_logic_vector
std_logic_vector
natural
Actual value
0
reset active polarity
Description
8
1
3
1
8
0
0
4d
0
10
defines the width of the data lines of the system
Type Depth
Address Depth
Length Depth
Depth of data (2^8 = 256 addresses)
disable polarity of the CCB
polarity of the config_again signal
the value that Indicates end of the dada at the RAM
initial address
number of cycles client reset is active
Table 22 -Config Control block generics
8.
The Config Control Block contains the following units:
6.3.1 CCB_FSM
The FSM starts its operation when the DE2 switch that defines the ccb_disable signal does
not equal to ccb_disable_polarity_g.
There is an option for a user to read from FLASH and configure clients when the DE2 switch
that define the config_again signals equals to config_again_polarity_g.
Figure 7 - CCB FSM
signal name
type
width (bits)
description
clk
input
1
system clock
reset
input
1
system reset
ccb_disable
input
1
disables ccb data upload from flash
config_again
input
1
configures clients again from data already stored in the RAM
client_reset
output
1
resets clients on when user chooses config_again
ram_select
output
1
MUX selector to read type ,addr,len from RAM
ram_valid_rd
input
1
1' is received when the data from RAM is valid
ram_data_rd
input
data_width_g
data received from RAM
ram_addr_valid_rd
output
1
1' is when request to read from RAM
ram_addr_rd
output
data_width_g
address in RAM to be read
wm_start
output
1
WM start command
wr_en
output
1
write enable
type_out
output
type_d_g*data_width_g
type is the client which the data is directed to
addr_out
output
addr_d_g*data_width_g
the address in the client that the information will be written to
len_out
output
len_d_g*data_width_g
length of the data (in words)
ram_start_addr
output
addr_bits_g
RAM write address
wm_end
input
1
1' is received when WM ends its operation
Table 23 - CCB FSM interface
Generic Parameter
reset_polarity_g
type
std_logic
Actual value
0
reset active polarity
Description
data_width_g
type_d_g
addr_d_g
len_d_g
addr_bits_g
ccb_disable_polarity_g
config_again_polarity_g
eod_g
initial_address_g
reset_cycles_g
natural
positive
positive
positive
positive
std_logic
std_logic
std_logic_vector
std_logic_vector
natural
8
1
3
1
8
0
0
4d
0
10
defines the width of the data lines of the system
Type Depth
Address Depth
Length Depth
Depth of data in RAM (2^8 = 256 addresses)
ccb_disable active polarity
config_again active polarity
End Of Data
initial address
number of cycles client reset is active
Table 24 - CCB FSM generics
6.3.2 RAM
A 256 byte RAM. See signal and generics list at the RX path chapter.
6.3.3 Wishbone master
See Wishbone Master at wishbone units.
6.4 Flash Control
General Description
1. The Flash Control Block (FCB) is responsible for transactions with FLASH
memory. The block can:
-
2.
3.
4.
5.
6.
Read FLASH memory up to its RAM size ( 2addr _ bits _ g ) at a time
- Write data to FLASH memory – up to 2addr _ bits _ g bytes at a time.
- Erase a sector at FLASH memory
- Reset FLASH
Interface:
- BUS: using Wishbone protocol by a wishbone slave unit (WBS 6).
- FLAHS: using CFI by flash_controller unit.
The FCB consists of the following sub-blocks:
- Flash FSM – manages the transaction
- Flash controller – executes a FLASH operation using CFI protocol
- Reset enabler – prevents client reset during FLASH operation
- RAM
- Wishbone Slave
Initiative read - the FCB would fill its RAM with FLASH data from a known
address on power on. This data is read by the Config Control block later. This
feature enhances system performance for the ‘FPGA setting using FLASH’
system. This option could be cancelled by setting the config_on_start_g generic to
FALSE.
FLASH memory – The FLASH memory used in the system is a 4MB S29AL032D by
Spansion which is placed on the DE2 board.
FLASH command encoding – The commands are encoded on the Wishbone bus
TGA field (which contains the ‘type’). The following table specifies what the TGA
value should be for each FLASH command.
command
read(phase 1)
read(phase 2)
Write
Reset
erase section
configure (read)
from
rx
TX
rx
rx
rx
CCB
to
TGA(Type) binary
TX
11000010
flash_client
00000110
flash_client
01000110
flash_client
10000110
flash_client
11000110
flash_client
00000110
Table 25 - FLASH command encoding
Blue numbers:
red and green numbers
TGA (Type) hex
0xC2
0x06
0x46
0x86
0xC6
0x06
TGA (Length)
any
any
any
00
00
any
Figure 8 - Flash control
signal name
type
width (bits)
description
sys_clk
input
1
system clock
sys_reset
input
1
system reset
flash_error
output
1
asserted on FLASH timeout
ADR_I
input
(data_width_g)*(addr_d_g)
contains the addr word
DAT_I
input
data_width_g
contains the data_in word
WE_I
input
1
'1' for write, '0' for read
STB_I
input
1
'1' for active bus operation, '0' for no bus operation
CYC_I
input
1
'1' for bus transmition request, '0' for no bus transmition request
TGA_I
input
(data_width_g)*(type_d_g)
contains the type word
TGD_I
input
(data_width_g)*(len_d_g)
contains the len word
ACK_O
output
1
'1' when valid data is transmitted to MW or for successful write operation
DAT_O
output
data_width_g
data transmit to MW
STALL_O
output
1
STALL - WS is not available for transaction
FL_ADDR
output
flash_size_g
FLASH Address
FL_DQ
input
data_width_g
FLASH data input and output
FL_OE_n
output
1
FLASH Output Enable
FL_CE_n
output
1
FLASH Chip Enable
FL_WE_n
output
1
FLASH Write Enable
FL_RST_n
output
1
FLASH Reset
Table 26 - Flash controle interface
Generic Parameter
reset_polarity_g
data_width_g
addr_bits_g
type_d_g
addr_d_g
len_d_g
initial_address_g
flash_size_g
flash_wr_time_g
flash_sec_er_time_g
clk_freq_g
reset_cycles_g
config_on_start_g
6.4.1
type
std_logic
natural
positive
positive
positive
positive
std_logic_vector
natural
natural
natural
natural
natural
Boolean
Actual value
0
Description
reset active polarity
8
8
1
3
1
000000
22
9
700000
defines the width of the data lines of the system
Size of RAM (2^8 = 256 addresses)
Type Depth
Address Depth
Length Depth
initial address accessed to FLASH by system
log2 of flash size [22 => 4MB]
FLASH write period [usec]
FLASH section erasure period [usec]
System clock frequency (valid values in[MHz]:25,50,100,or more than
100000000
200)
10
number of cycles client reset is active
TRUE
if true: controller reads data from initial_address_g to RAM on start
Table 27 - Flash control generics
Flash FSM
FLASH FSM translates Wishbone Bus commands to FLASH commands for
flash_controller. It also read and writes to RAM data from the Bus and data
received from FLASH.
Figure 9 - Flash FSM
signal name
type
width (bits)
description
clk
input
1
system clock
reset
input
1
system reset
type
input
(data_width_g)*(type_d_g)
addr
input
(data_width_g)*(addr_d_g)
Type
the beginning address in the client that the information will be written
to
len
input
(data_width_g)*(len_d_g)
Length of data received in bytes
we_en
input
1
write enable
ws_data
input
data_width_g
data out to registers
ws_data_valid
input
1
data valid to registers
reg_data
output
data_width_g
data to be transmitted to the WM
reg_data_valid
output
1
data to be transmitted to the WM validity
active_cycle
input
1
CYC_I outputed to user side
stall
output
1
stall - suspend wishbone transaction
oDATA
input
data_width_g
FLASH input data (read from FLASH)
iDATA
output
data_width_g
FLASH output data (to be written to FLASH)
iADDR
output
flash_size_g
FLASH output Address
iCMD
output
2
FLASH output Command
oDone
input
1
FLASH input Ready
iStart
output
1
FLASH output Start FLASH operation
ram_wr_addr
output
addr_bits_g
RAM Input address
ram_wr_dout
output
data_width_g
RAM Input data
ram_wr_dout_valid
output
1
RAM Input data valid
ram_rd_aout
output
addr_bits_g
RAM Output address
ram_rd_aout_valid
output
1
RAM Output address is valid
ram_rd_din
input
data_width_g
RAM Output data
ram_rd_din_valid
input
1
Generic Parameter
reset_polarity_g
data_width_g
flash_size_g
addr_bits_g
type_d_g
addr_d_g
len_d_g
initial_address_g
config_on_start_g
type
std_logic
natural
natural
positive
positive
positive
positive
std_logic_vector
Boolean
RAM Output data valid
Table 28 - Flash FSM interface
Actual value
0
Description
reset active polarity
8
defines the width of the data lines of the system
22
log2 of flash size [22 => 4MB]
8
Size of RAM (2^8 = 256 addresses)
1
Type Depth
3
Address Depth
1
Length Depth
00000
Start of data structure to be read from FLASH
true
if true: controller reads data from initial_address_g to RAM on start
Table 29 - Flash FSM generics
6.4.2
Flash Controller
FLASH controller of the s29al032d_03_04 FLASH Device.
Controller Commands:
CMD_READ
=
"00"
CMD_WRITE
=
"01"
CMD_RESET
=
"10"
CMD_SEC_ERA
=
"11"
To start command operation user must assert iStart and supply valid values on:
iCMD, and iADDR iDATA if needed.
Command finishes its execution on oDone rising edge.
mCLK cycle time which is a FLASH access cycle time is set to 80nsec and could be
changed by clk_divide_c generic.
The clock supplied to flash_controller (and defined by the generic clk_freq_g)
must be one of the following values:
50[MHz], 100[MHz], 125[MHz] or more than 200[MHz]
otherwise flash_controller may not work or work incorrectly.
Figure 10 - Flash Controller FSM
signal name
type
width (bits)
description
FL_ADDR
output
flash_size_g
FLASH Address
FL_DQ
input
data_width_g
FLASH data input and output
FL_OE_n
output
1
FLASH Output Enable
FL_CE_n
output
1
FLASH Chip Enable
FL_WE_n
output
1
FLASH Write Enable
FL_RST_n
output
1
FLASH Reset
oDATA
output
data_width_g
Output data (read from FLASH)
iDATA
input
data_width_g
Input data (to be written to FLASH)
iADDR
input
flash_size_g
Input Address
iCMD
input
2
Input Command
oDone
output
1
Output Ready
oBusy
output
1
Output FLASH busy
oError
output
1
Output Error (FLASH timeout)
iStart
input
1
Input Start FLASH operation
iCLK
input
Input Clock
iRST_n
input
1
1
Input Reset
Table 30 - Flash Controller interface
Generic Parameter
reset_polarity_g
type
std_logic
Actual value
0
reset active polarity
Description
data_width_g
flash_size_g
flash_wr_time_g
flash_sec_er_time_g
clk_freq_g
natural
natural
positive
positive
natural
8
22
9
700000
100000000
defines the width of the data lines of the system
log2 of flash size [22 => 4MB]
FLASH write period [usec]
FLASH section erasure period [usec]
System clock frequency (valid values in[MHz]:25,50,100,or more than 200)
Table 31 - Flash controller generics
6.4.3
signal name
Reset_enabler
The reset_enabler does not enable flash_client reset while FLASH is busy.
The flash_client is reseted once the FLASH memory finishes its operation.
While waiting for the FLASH to finish, the Odone signal from flash_controller
is masked in order not to send an unnecessary ACK on the bus.
type
width (bits)
description
clk
input
1
system clock
reset
input
1
system reset
flash_busy
input
1
FLASH busy with an operation
reset_client
output
1
reset flash_client
mask_odone
output
1
mask Odone signal
Table 32 - reset enabeler interface
Generic Parameter
reset_polarity_g
reset_cycles_g
type
std_logic
0
Actual value
reset active polarity
Description
natural
10
number of cycles client reset is active
Table 33 - reset enabler generics
6.4.4
RAM
A 256 byte RAM. See signal and generics list at the RX Path.
6.4.5
Wishbone slave
See Wishbone Slave wishbone units.
6.5 Clock and Reset
Figure 11 - clk& reset
General Description
1. The Clk & Reset unit would generate the clock and reset signals for the system.
2. Inputs:
- Fpga_clk – input clock from the DE2 to the FPGA, 50MHz.
- Fpga_rst – reset signal from the FPGA.
- Client_rst - reset clients only by the CCB.
- Sleep - asynchronic reset , a sleep switch.
3. Outputs:
- System_clk – output clock to the system, 100MHz.
- Vesa_clk – output clock to the veza, 65MHz.
- sync_system_rst - Synchronized reset of the 100MHz clock.
- sync_vesa_rst - Synchronized reset of the 65MHz clock.
- sync_client_rst - reset clients only by the CCB.
- sync_fpga_rst - Synchronized fpga reset of the 50MHz clock.
4. The Clk & Reset block would consist of two major sub – blocks:
- Clock_block_top: generate 100MHz & 65MHz clocks from an inner PLL , for
the system and vesa clocks.
- Reset_block_top: contain a reset debouncer that assert reset only if the DE2
reset button is pressed for at least 5 system clock cycles. And a Synchronous
Reset Generator.
5. The PLL block is be generated by Quartus Megawizard.
** Due to Quartus Megawizard PLL limitations the VESA clock generated is
64.285714 MHz instead of 65 MHz. The difference does not affect the display
quality.
Signals
fpga_clk
signal name
input
Type
width (bits)
1
description
Input clock to the FPGA (50MHz)
fpga_rst
input
1
Input reset from FPGA
client_rst
input
1
Input reset clients only by the CCB
sleep
input
1
Input asynchronic reset (sleep switch)
system_clk
output
1
Output system clock (100MHz)
vesa_clk
output
1
Output VESA clock (65MHz)
sync_system_rst
output
1
Output Synchronized reset - 100MHz
sync_vesa_rst
output
1
Output Synchronized reset - 65MHz
sync_client_rst
output
1
Output reset clients only by the CCB
sync_fpga_rst
output
1
Output Synchronized fpga reset - 50MHz
pll_locked
output
1
PLL locked indication.
Table 34 - clock and reset interface
Generic Parameter
reset_polarity_g
type
std_logic
Actual value
1
When '1' - Reset
sleep_polarity_g
std_logic
1
When '1' - Sleep
sys_clkrate_g
positive
100000000
Sys. clock [Hz]
vesa_clkrate_g
positive
65000000
VESA clock [Hz]
sim_clk_gen_g
BOOLEAN
FALSE
Description
Swapping PLL with simulation clock-generator
Table 35 - clock and reset generics
6.6 Filter
Figure 12 - Filter
General Description
1. The Filter block filters a signal originated by an on board switch. The signal is
sampled a number of times defined by a generic and if the signal keeps its polarity
the output is updated.
2. In the system there are two Filter blocks which receive the ccb_disable and
config_again signals from user (a switch on DE2 board). More detail on these signals
on CCB chapter.
3. The input signal is generated using a DE2 switch, therefore it could be unstable. The
Filter block samples the signal a given amount of times defined by its generics.
4. Sig_in could be sampled once or twice (defined by a generic). Sampling the signals
twice helps to avoid metastability.
5. Generics:
- sample_depth_g – the number of samples needed before the filtered signal
(Sig_filtered) can change from one state to another.
- default_start_value_g – the default value of sig_filtered (0 or 1) before the
arrival of enough samples (defined by sample_depth_g).
- reset_activity_polarity_g – the value of which resets the Filter block (reset is
done by the Sys_reset signal)
- sample_twice_en – defines if sig_in would be sampled once or twice.
Signals
signal name
sig_in
clk (100MHz)
sys_reset
sig_filtered
Type
Input
Input
Input
Output
width (bits)
1
1
1
1
description
the signal which needs filtering
system clock
block reset
signal after filtering
Table 36 -Filter interface
Generic Parameter
reset_polarity_g
type
std_logic
0
Actual value
sample_depth_g
positive
300000
Description
'0' = Active Low, '1' = Active High
the number of samples needed before the filtered signal output updates
(default:3msec)
default_start_value_g
std_logic
1
the default value of sig_filtered
sample_twice_en_g
std_logic
1
'1' sample the input twice to prevent metastability
Table 37 - Filter generics
6.7 Wait - client
Figure 13 - wait calient
General Description
1. The Wait Block would occupy the bus on demand from master (CCB) for a given
amount of time
2. The Wait client has a wishbone slave interface.
3. The counter in the wait control and the timer will calculate the needed time to
occupy the bus: The timer will raise the ‘timer_tic’ signal every time unit (generic)
for one cycle time, the counter will count the number of time_unit tics, when the
counting will arrive to ‘wait_reg’ – the value saved in the register- the wait control
will raise ‘finish’ to signify that this transaction is finish.
Pin Name
Direction
Description
Sys_clk
Sys_reset
in
In
Clock
Reset. Reset polarity will be set according to the generic parameter 'reset_polarity_g'
Dat_in
In
Data output from the wishbone slave – NOT USED
We_in
In
The wishbone write enable signal. When ‘1’ write to the unit
Stb_in
In
The wishbone STB signal
Cyc_in
In
The wishbone CYC signal
Ack_output
out
Indicate that the unit finish to wait, and free the BUS
Table 38 - wait client signals
Generic Parameter
type
reset_activity_polarity_g
Std_logic
Actual
value
‘1’
block_enable_polarity_g
std_logic
‘1’
defines the active block enable polarity : '0' active low, '1' active high
finish_activity_polarity_g
std_logic
‘1’
defines finish active polarity: '0' active low, '1' active high
natural
8
width of the wait_reg vector
wait_value_width_g
Description
defines reset active polarity: '0' active low, '1' active high
timer_freq_g
positive
100
clk_freq_g
positive
10000
timer_en_polarity_g
std_logic
timer_tick will raise for 1 sys_clk period every timer_freq_g. units: [Hz]
the clock input to the block. this is the clock used in the system containing
the timer unit. units: [Hz]
‘1’
defines the polarity which the timer enable (timer_en) is active on: '0'
active low, '1' active high
Table 39 - wait client generics
Wait_client_ins: This unit will count number of wait_reg ‘ticks’ from the timer and then will
upraise the finish signal.
Pin Name
Direction
Description
Sys_clk
Input
clock
Sys_reset
Input
Reset. Reset polarity will be set according to the generic parameter
'reset_polarity_g'
Enable
Input
determines if the wait client is enables
wait_reg
Input
The waiting time value received from registers
finish
Output
this signal signify the end of the wait transaction
Table 40 - wait_client_int interface
Generic Parameter
reset_activity_polarity_g
block_enable_polarity_g
finish_activity_polarity_g
wait_value_width_g
type
Std_logic
Std_logic
Std_logic
Actual value
1'
1'
1'
8
natural
Description
defines reset active polarity: '0' active low, '1' active high
defines the active block enable polarity : '0' active low, '1' active high
defines finish active polarity: '0' active low, '1' active high
width of the wait_reg vector
Table 41 - wait_client_int generics
6.7.1 Timer
A timer unit is placed inside every Led unit and function as detailed in the Led description.
signal name
sys_clk
sys_reset
timer_en
timer_tick
generic name
reset_polarity_g
type
input
input
input
output
type
std_logic
positive
timer_freq_g
width (bits)
description
1
system clock
1
system reset
1
determines if the timer is enabled
1
asserted for 1 cycle every 100,000 cycles
Table 42 - Timer interface
Actual value
1
10
positive
clk_freq_g
100000000
description
'0' = Active Low, '1' = Active High
timer_tick will raise for 1 sys_clk period every timer_freq_g. units: [Hz]
the clock input to the block. this is the clock used in the system
containing the timer unit. units: [Hz]
std_logic
timer_en_polarity_g
1
defines the active state of the timer: '0' active low, '1' active high
Table 43 - Timer generics
6.8 LED – client
Figure 14 - LED client
General Description
1. The LED block would be used to operate a led at different frequencies or at steady
on/off state.
2. The LED client has a wishbone slave interface.
3. The client will contains 4 LEDs, each one of them will have led control and timer.
4. The Led client contains a register block that will hold the data of the LEDs
requirement:
5. The Timer in the LED block generates a timer_tick every 100,000 cycles which are 1
msec.
6. All the information regarding the leds is loaded to the led_registers block.
signal name
type
width (bits)
description
sys_clk
input
1
system clock
sys_reset
input
1
system reset
DAT_I
input
data_width_g
ADR_I
input
addr_d_g * data_width_g
WE_I
input
1
'1' for write, '0' for read
STB_I
input
1
1' for active bus operation, '0' for no bus operation
CYC_I
input
1
'1' for bus transmition request, '0' for no bus transmition request
TGA_I
input
type_d_g * data_width_g
contains the type word
TGD_I
input
len_d_g * data_width_g
contains the length word
ACK_O
DAT_O
STALL_O
led_activate_1
led_activate_2
led_activate_3
led_activate_4
output
output
output
output
output
output
output
data received from WS
contains the address word
1
1 for valid data is transmitted to MW or for successful write operation
data_width_g
data transmit to MW
1
STALL - WS is not available for transaction
1
this signals activates the led number 1
1
this signals activates the led number 2
1
this signals activates the led number 3
1
this signals activates the led number 4
Table 44 - Led client interface
generic name
reset_polarity_g
data_width_g
type_d_g
addr_d_g
len_d_g
en_reg_address_g
freq_reg_1_address_g
freq_reg_2_address_g
freq_reg_3_address_g
freq_reg_4_address_g
type
std_logic
natural
positive
positive
positive
natural
natural
natural
natural
natural
active_state_polarity_g
std_logic
Actual value
1
8
1
3
1
0
1
2
3
4
1
description
'0' = Active Low, '1' = Active High
defines the width of the data lines of the system
Type Depth
Address Depth
Length Depth
enable register address
frequency register 1 address
frequency register 2 address
frequency register 3 address
frequency register 4 address
defines the active state of the led: '0' active low, '1' active high
1
block_enable_polarity_g
std_logic
defines the active block enable polarity: '0' active low, '1' active high
1
freq_enable_polarity_g
freq_width_g
std_logic
natural
timer_freq_g
positive
defines freq_en input active state: '0' active low, '1' active high
width of the frequency vector
8
1000
100000000
clk_freq_g
positive
timer_en_polarity_g
std_logic
timer_tick will raise for 1 sys_clk period every timer_freq_g. units: [Hz]
the clock input to the block. this is the clock used in the system
containing the timer unit. units: [Hz]
1
defines the active state of the timer: '0' active low, '1' active high
Table 45 - Led client generics
The led clients generics are all its sub-units generics.
The Led client contains the following units:
6.8.1 Led Registers
Contains 5 registers which control the functionality of the leds. It receives this data from the
wishbone slave of the led_client. The registers:
 Enable register: enables led operation and flickering in the following way.
Each led has the following bits:
Enable bit: ‘0’ to disable the led and ‘1’ to enable it.
Frequency enable bit -‘0’ signify that the led is turned on without flashing (if
Enable equal to '1') and ‘1’ signify that the led will flash.
The bits are mapped as follow:
7
Led 4
enable
6
Led 4
frequency
enable
5
Led 3
enable
4
Led 3
frequenc
y enable
3
Led 2
enable
2
Led 2
frequency
enable
1
Led 1
enable
0
Led 1
frequenc
y enable
Table 46 - Led register mapping

Frequency register (4 instances) – These registers include the frequency that
the led will flash when the frequency enable is ‘1’.
The frequency of the flickering will be (time_unit_g) *(Frequency value) .
Figure 15 - Led waveform
Example: A led that will receive 01_0x on its frequency input would count: 2 timer
ticks before it inverts the active signal. The timer tick will be asserted for one cycle
every 100,000 system clock cycles – thus 1msec.
signal name
sys_clk
sys_reset
data_out
valid_data_out
address_in
data_in
valid_in
wr_en
CYC_I
STB_I
en_out
freq_out_1
freq_out_2
freq_out_3
freq_out_4
generic name
reset_polarity_g
data_width_g
addr_d_g
en_reg_address_g
freq_reg_1_address_g
freq_reg_2_address_g
freq_reg_3_address_g
freq_reg_4_address_g
type
input
input
output
output
input
input
input
input
input
input
input
output
output
output
output
width (bits)
description
1
system clock
1
system reset
data_width_g
data sent to WS
1
validity of data directed to WS
addr_d_g * data_width_g address line
data_width_g
data sent from WS
1
validity of the address directed from WS
1
write enable: '1' for write, '0' for read
1
active wishbone cycle
1
active wishbone operation within a cycle
data_width_g
enable data sent to led_1, led_2, led_3, led_4
data_width_g
frequency data sent to led_1
data_width_g
frequency data sent to led_2
data_width_g
frequency data sent to led_3
data_width_g
frequency data sent to led_4
Table 47 - Led Registers interface
Actual value
Type
description
1
std_logic
'0' = Active Low, '1' = Active High
8
Natural
defines the width of the data lines of the system
3
Positive
Address Depth
0
Natural
enable register address
1
Natural
frequency register 1 address
2
Natural
frequency register 2 address
3
Natural
frequency register 3 address
4
Natural
frequency register 4 address
Table 48 - Led Registers generics
6.8.2 LED
(4 instances)
Every register value would be transferred to a led block that will function accordingly. The
block’s output will be connected to a LED on the DE2 board. Inside every led unit there is a
timer unit which raises a timer tick every given amount of clock cycles (set by the timer_freq_g
generic).
Figure 16 - Led unit
sys_clk
sys_reset
enable
freq_en
freq
signal name
type
input
input
input
input
input
led_activate
output
generic name
reset_polarity_g
data_width_g
type
std_logic
natural
block_enable_polarity_g
std_logic
freq_enable_polarity_g
freq_width_g
std_logic
natural
timer_freq_g
positive
width (bits)
1
1
1
1
freq_width_g
1
this signals activates the led: '1' led is turned on, '0' led is turned off
Table 49 - Led interface
Actual
value
1
8
1
positive
std_logic
description
'0' = Active Low, '1' = Active High
defines the width of the data lines of the system
defines the active block enable polarity: '0' active low, '1' active high
1
defines freq_en input active state: '0' active low, '1' active high
width of the frequency vector
8
1000
timer_tick will raise for 1 sys_clk period every timer_freq_g. units: [Hz]
100000000
clk_freq_g
timer_en_polarity_g
description
system clock
system reset
determines if the led is enables
enables led flickering
led flickering frequency received from registers
1
the clock input to the block. this is the clock used in the system
containing the timer unit. units: [Hz]
defines the active state of the timer: '0' active low, '1' active high
Table 50 - Led generics
Wishbone Slave - see wishbone units.
6.9 Display – client
Figure 17 - Display Client
General Description
1. The display client would control an external screen in 1024X768 resolution. The ROI
(region of interest) is 800X600.
Figure 18 - Display resolution and ROI
2. The display client has a wishbone slave interface. WS number 5.
3. An image can be display on the screen in one form a line, column or squares
(Damka) format according to register values. The Image would be displayed with a
graduate change of colors from line to line (or column to column, or square to
square)
4. The display interface to the display will be with VESA protocol which operates with
a 65MHz clock.
5. In order to fit the system clock of 100 MHz to the VESA clock of 65 MHz we will use
Clock Domain Crossing (CDC) hardware.
6. The display unit does not cope with an out of boundary values of the ROI. The
location_reg will only receive values that for them all the ROI will be inside the
screen. The host’s GUI would be responsible to check the legality of these values.
6.9.1 Wishbone Slave
See Wishbone Slave at wishbone units.
6.9.2 Display Registers
The Display registers block is a set of 23 registers that sets the Display client configuration.



The block uses a 100MHz clock.
Data to registers is written or read threw Wishbone Slave.
The system includes the following registers:
 Key :
Line registers
Column
Damka registers General
registers
registers
Reg#
0
1
Name
Enable_reg*
x_line_location_reg
2
y_line_location_reg
3
x_column_location_r
eg
y_column_location_r
eg
x_damka_location_re
g
y_damka_location_re
g
line_width_reg
column_width_reg
damka_width_reg
r_line_jump_reg
g_line_jump_reg
b_line_jump_reg
r_column_jump_reg
4
5
6
7
8
9
10
11
12
13
Description
Enables the client’s configuration (more description below)
The X location of the top left corner of the ROI using line
mode
The Y location of the top left corner of the ROI using line
mode
The X location of the top left corner of the ROI using column
mode
The Y location of the top left corner of the ROI using column
mode
The X location of the top left corner of the ROI using damka
mode
The Y location of the top left corner of the ROI using damka
mode
the width of a single line
the width of a single column
the width of the side of a single square
the difference of the red color between each line
the difference of the green color between each line
the difference of the blue color between each line
the difference of the red color between each column
Legal values
All
0-224
0-168
0-224
0-168
0-224
0-168
All
All
All
All
All
All
All
14
15
16
17
18
19
20
21
22
g_column_jump_reg
b_column_jump_reg
r_damka_jump_reg
g_damka_jump_reg
b_damka_jump_reg
green_start_reg
blue_start_reg
red_start_reg
register_valid_reg**
the difference of the green color between each column
the difference of the blue color between each column
the difference of the red color between each damka cube
the difference of the green color between each damka cube
the difference of the blue color between each damka cube
the start value of the green color
the start value of the blue color
the start value of the red color
updates the synthetic_data_provider when registers are
updated
All
All
All
All
All
All
All
All
0 or 1
Table 51 - Display Registers
*Enable_reg – enabling parameters:
- VESA enable – enables the operation of the VESA block
- Picture enable – enables picture displaying. If the VESA enable is enabled and
the picture enable is not, then a default constant display will be displayed.
- Line enable – enables line framing
- Column enable – enable column framing
- Damka enable – enables square framing
Bit 7
Not
used
Bit 6
Not
used
Bit 5
Not
used
Bit 4
Bit 3
Bit 2
Damka Column Line
Enable enable enable
Bit 1
Picture
enable
Bit 0
VESA
enable
Table 52 - VESA enable_reg mapping
**register_valid_reg - when registers are updated, this registers is set to 0x00 first and in
the end set to 0x01. While the register’s value is 0x00, the data in the other 22 registers is
not updated at the synthetic data provider. This feature prevents the display client from
displaying a partial configuration. Such a partial configuration occurs when the host writes
makes a group of write transactions to a single register at a time.
.
6.9.3 VESA generator
created in the Runlen project and integrated in the display client. The VESA generator
transmits data to a screen using VESA protocol. It gets the RGB values of each pixel from the
Synthetic Data provider.
6.9.4
Synthetic data provider
Figure 19 - Synthetic Data Provider
The synthetic data provider colors each pixel of each frame according to the values sampled
at the registers block. The pixel’s RGB data is passed to the VESA generator block that
transmits it to the screen using VESA protocol.
1. The block uses a 65MHz clock (VESA clock).
2. There are 4 sort of pictures the block can generate: lines, columns, damka or
default(blue screen).
Figure 20 - System optional pictures
3. For each format the user can determine the width and the RGB color difference
between each shape (line, column, square).
4. The block consists of 3 main parts:
Control Process – determines the format to be transmitted and its parameters by
the value sampled from the registers block.
Transmit Process – calculates the correct RGB values according to control signals
generated by the control process. Drives this values to the block’s RGB outputs.
Auxiliary Processes – a set of processes used for synchronization. These processes
detect when the registers are updated and when a frame is being transmitted in
order to transmit a correct and accurate frame.
5. The block contains a set of 22 shadow registers, registers that hold the block’s
configuration and therefore sampled only between active frames and never while an
active frame is being transmitted in order to prevent frames such as these:
Figure 21 - unwanted frames
6. The shadow registers are updated only after on a rising edge of the data_valid signal
(one bit) and not while an active frame is transmitted. If a frame is transmitted and
the data_valid signal rises the shadow registers are update when the frame
transmission ends. The data_valid signal is the LSB of the register_valid_reg in the
registers block. It gets the ‘0’ value while the register block is updated and ‘1’ when
the update is finished.
6.9.5 Synchronizer and clock domain crossing
The Display clock has 2 clock regions: system clock (100MHz) and VESA clock (65MHz), Thus
a clock domain crossing is needed. The Synchronizer samples a single bit once by the fast
clock (100MHz) and twice by the slow clock (65MHz) as seen in the figure.
Figure 22 - Synchronizer
The following configuration prevents the signal from reaching metastability. The signals in
the display client that are synchronized are:
-
register_valid_sig – 1 synchronizer
enable_reg_sig(4:0) - 5 synchronizers
By synchronizing these signals the whole domain crossing is implemented because the
Synthetic data provider (VESA clock region) will sample the registers at the registers block
(System clock Region) only on a register_valid_sig rising edge. The system architecture
ensures that by the time the register_valid_sig has a rising edge all the signals sampled at
the VESA clock region are stable. An exception are the enable signals which have their own
synchronizer.
Figure 23 - Display Client Clock Domain Crossing
6.9.6
Interface, Generics and Waveform
Figure 24 - Display client waveform
signal name
type
width (bits)
description
sys_clk
input
1
system clock (100MHz)
sys_reset
input
1
system reset
sys_clk
input
1
VESA clock (65MHz)
vesa_reset
input
1
VESA reset
DAT_I
input
data_width_g
ADR_I
input
addr_d_g * data_width_g
WE_I
input
1
'1' for write, '0' for read
STB_I
input
1
1' for active bus operation, '0' for no bus operation
CYC_I
input
1
'1' for bus transmition request, '0' for no bus transmition request
TGA_I
input
type_d_g * data_width_g
contains the type word
TGD_I
input
len_d_g * data_width_g
contains the length word
ACK_O
output
1
DAT_O
output
data_width_g
STALL_O
OUTPUT
r_out
output
data_width_g
Output Red Pixel
g_out
output
data_width_g
Output Green Pixel
b_out
output
data_width_g
Output Blue Pixel
blank_out
output
1
1
data received from WS
contains the address word
'1' when valid data is transmitted to MW or for successful write operation
data transmit to MW
stall - suspend wishbone transaction
Blanking signal
hsync_out
output
1
vsync_out
output
1
generic name
HSync Signal
VSync Signal
Table 53 - Display Client Signals
type
description
reset_polarity_g
data_width_g
type_d_g
addr_d_g
len_d_g
data_width_g
hsync_polarity_g
vsync_polarity_g
enable_polarity_g
valid_polarity_g
change_frame_clk_g
hor_pres_pixels_g
ver_pres_lines_g
hor_active_pixels_g
ver_active_lines_g
red_width_g
green_width_g
blue_width_g
blank_polarity_g
red_default_color_g
green_default_color_g
blue_default_color_g
std_logic
natural
positive
positive
positive
positive
std_logic
std_logic
std_logic
std_logic
positive
positive
positive
positive
positive
positive
positive
positive
std_logic
natural
natural
natural
'0' = Active Low, '1' = Active High
defines the width of the data lines of the system
Type Depth
Address Depth
Length Depth
data width
hsync polarity
vsync polarity
enable polarity
valid polarity
Change frame position each 'change_frame_clk_g' clocks
horizantal pixels in frame
vertical pixels in frame
active pixels per line
active lines
Default std_logic_vector size of Red Pixels
Default std_logic_vector size of Green Pixels
Default std_logic_vector size of Blue Pixels
When '0' - Blanking signal to the VGA
Default Red pixel for Frame
Default Green pixel for Frame
Default Blue pixel for Frame
req_delay_g
positive
Number of clocks between the "req_data" request to the
"data_valid" answer
req_lines_g
hor_left_border_g
hor_right_border_g
hor_back_porch_g
hor_front_porch_g
hor_sync_time_g
ver_top_border_g
ver_buttom_border_g
ver_back_porch_g
ver_front_porch_g
ver_sync_time_g
enable_reg_g
x_line_location_reg_g
y_line_location_reg_g
x_column_location_reg_g
y_column_location_reg_g
x_damka_location_reg_g
y_damka_location_reg_g
line_width_reg_g
column_width_reg_g
damka_width_reg_g
r_line_jump_reg_g
g_line_jump_reg_g
positive
natural
natural
integer
integer
integer
natural
natural
integer
integer
integer
natural
natural
natural
natural
natural
natural
natural
natural
natural
natural
natural
natural
Number of lines to request from image transmitter, to hold in
its FIFO
Horizontal Left Border (Pixels)
Horizontal Right Border (Pixels)
Horizontal Back Porch (Pixels)
Horizontal Front Porch (Pixels)
Horizontal Sync Time (Pixels)
Vertical Top Border (Lines)
Vertical Bottom Border (Lines)
Vertical Back Porch (Lines)
Vertical Front Porch (Lines)
Vertical Sync Time (Lines)
register numbering
register numbering
register numbering
register numbering
register numbering
register numbering
register numbering
register numbering
register numbering
register numbering
register numbering
register numbering
b_line_jump_reg_g
r_column_jump_reg_g
g_column_jump_reg_g
b_column_jump_reg_g
r_damka_jump_reg_g
g_damka_jump_reg_g
b_damka_jump_reg_g
green_start_reg_g
blue_start_reg_g
red_start_reg_g
register_valid_reg_g
default_reset_value_g
natural
register numbering
natural
register numbering
natural
register numbering
natural
register numbering
natural
register numbering
natural
register numbering
natural
register numbering
natural
register numbering
natural
register numbering
natural
register numbering
natural
register numbering
std_logic
synchronizer's default reset value
Table 54 - Display Client Generics
Generics Key:
Common
Synthetic Data
Provider
VESA
generator
Display
Registers
6.10 Wishbone Blocks and protocol
6.10.1 Wishbone Protocol
The Internal communication system uses the international Wishbone protocol. The
Wishbone Bus is an open source hardware computer bus intended to let the parts of an
integrated circuit communicate with each other. The aim is to allow the connection of
differing cores to each other inside of a chip.
There are two types of clients on the wishbone bus: master and slave.
1 – wishbone master (WM) – active unit. Initiates bus cycles and ends them.
2 – wishbone slave (WS) - passive unit. Writes or reads data according to master request.
In our system we use the following signals in order to activate the wishbone bus.
CYC – '1' for bus transmition request, '0' for no bus transmition request
STB – '1' for active bus operation, '0' for no bus operation
DAT(sent from WM to WS) – data sent on the bus
ADR – initial address for transaction
TGA – type of client being accessed
TGD – length of the data ( length[data] -1)
WE – write enable
DAT – data sent on the bus
ACK(sent from WS to WM) - successful read or write operation ended by WS.
STALL – indicate that the slave is not available for transaction.
ERR - Watchdog interrupts, resets the wishbone master.
Wishbone cycle example: In the following waveform a master performs a write transaction.
The assertion of the CYC signal indicates the beginning of the new transaction, while the STB
signal is high it indicates the data package transmission.
STB would de-asserted when master finishes sending or requesting data.
The maser will count the numbers of received ack’s (equal to the numbers of cycle the
acknowledge was high) and after all the acks will are received, the CYC signal will drop and
the transaction would end.
Figure 25 - Wishbone cycle waveform example
This mode of work is a pipeline mode, in that way all the bytes are transmit one after the
other, without waiting for an acknowledge after every byte.
*More about the advantage of a pipeline mode compared to the standard mode in the
system analysis chapter.
Numbering: Each master and slave has a unique number that characterizes it. For the
wishbone slaves this number is the TGA signal.
Wishbone master 1 – RX path
Wishbone master 2 – TX path
Wishbone master 3 – Config Control Block (CCB)
Wishbone slave 1 – RX path
Wishbone slave 2 – TX path
Wishbone slave 3 – Wait client
Wishbone slave 4 – Led client
Wishbone slave 5 – Display client
Wishbone slave 6 – Flash control
As seen above there are three masters in the systems. Only one master can make a
transaction on the bus. Therefore there is a routing policy implemented in the
wishbone_intercon unit.
6.10.2 Wishbone Intercon
The Wishbone Intercon consists of a router and an arbiter. The router directs the wishbone
signals from the operating master to the chosen slave through a series of muxes. The arbiter
is a FSM which enables only one master to use the wishbone bus. Every master that wants to
make a transaction asserts CYC. Only the master that is enabled by the arbiter FSM gets its
signals passed to the intended slave and can get back an ACK sig.
At the wishbone intercon a watchdog timer was implemented: If a transaction does not end
within a TimeOut, determine by generics (clk_freq_g/watchdog_timer_freq_g), the master
that hold the bus will be reseted by assertion of his ERR_I signal, and the transaction will
end.
The arbiter FSM operates as follow. If no master is using the bus than the master that asserts
CYC firsts can use the bus. If more than one master requests the bus at the same time, the
priority is:
WM 1 -> WM 2 -> WM3
Figure 26 - Wishbone Intercon
6.10.3 Wishbone Master
The Wishbone Master is the unit that initiates and manages a transaction on the wishbone
bus. The wishbone mode supported is pipeline mode defined in the Wishbone B4 spec.
Therefore, a respond to Wishbone request can be replied as soon as one cycle after it is
broadcast on a bus.
Connecting a Wishbone Master:
To make a transactions using a wishbone master a requesting unit should be connected and
a RAM. The requesting unit should supply the following data to make a transaction:
1. Assert wm_start for 1 cycle.
2. When asserting wm_start - provide valid values on:
- wr – ‘1’ for write transaction. ‘0’ for read transaction.
- len_in – length of the read/write.
- type_in – client being accessed in the transaction
- addr_in – address being accessed in the transaction
- ram_start_addr – the RAM address WM will write values received in a read
transaction or read from in a write transaction.
3. When transaction ends wm_end output would be asserted for 1 cycle to notify that the
WM has ended the current transaction and is ready for another one.
An example of how to connect a wishbone master is shown in the following figure.
Figure 27 - Connecting a Wishbone Master
Important signals:
STALL_I - A signal received from a client indicating the client is not ready for a
transaction. When stall is asserted WM holds the transaction and waits for STALL_I
to be de-asserted.
ERR_I – A signal received from Wishbone Intercon and indicates a bus timeout.
When ERR_I is asserted the WM is reseted and the transaction ends. The wm_end
output is asserted by the WM to notify the requesting unit that the transaction
ended.
The Wishbone Master FSM consists of 2 main branches:
Read – for a reading transaction
Write – for a writing transaction
Figure 28 - Wishbone Master FSM
signal name
sys_clk
sys_reset
ADR_O
DAT_O
type
input
input
output
output
width (bits)
1
1
addr_d_g * data_width_g
data_width_g
description
system clock
system reset
contains the address word
contains the data_in word
WE_O
STB_O
output
output
1
1
CYC_O
output
1
TGA_O
TGD_O
output
output
type_d_g * data_width_g
len_d_g * data_width_g
ACK_I
input
1
DAT_I
STALL_I
ERR_I
ram_addr
ram_dout
ram_dout_valid
ram_aout
ram_aout_valid
ram_din
ram_din_valid
wm_start
input
input
input
output
output
output
output
output
input
input
input
data_width_g
1
1
addr_bits_g
data_width_g
1
addr_bits_g
1
data_width_g
1
1
wr
input
1
type_in
len_in
input
input
type_d_g * data_width_g
len_d_g * data_width_g
addr_in
input
addr_d_g * data_width_g
ram_start_addr
input
addr_bits_g
wm_end
output
data_width_g
'1' for write, '0' for read
1' for active bus operation, '0' for no bus operation
1' for bus transmition request, '0' for no bus transmition
request
contains the type word
contains the length word
1' when valid data is received from WS or for successful write
operation in WS
data received from WS
STALL - WS is not available for transaction
Watchdog interrupts, resets wishbone master
RAM Input address
RAM Input data
RAM Input data valid
RAM Output address
RAM Output address is valid
RAM Output data
RAM Output data valid
when '1' WM starts a transaction
determines if the WM will make a read('0') or write('1')
transaction
type is the client which the data is directed to
length of the data (in words)
the address in the client that the information will be written
to
start address for WM to read from RAM
when '1' WM ended a transaction or reseted by watchdog
ERR_I signal
Table 55 - Wishbone Master interface
generic name
reset_polarity_g
data_width_g
type_d_g
addr_d_g
len_d_g
addr_bits_g
Actual value
type
description
std_logic
1
'0' = Active Low, '1' = Active High
natural
8
defines the width of the data lines of the system
positive
1
Type Depth
positive
3
Address Depth
positive
1
Length Depth
8
positive
Log2 of the size of the RAM connected to master
Table 56 - Wishbone Master generics
6.10.4 Wishbone Slave
Wishbone Slave is the client’s interface to the system. The unit is based on the same
principles as the wishbone master. It has the simplest hardware that can handle the
wishbone communication. Therefore it only responds to wishbone master signals and passes
any information received to its host’s units without any processing.
Important: The Wishbone mode of work implemented is pipeline mode. Therefore , the
slave automatically responds to a write transaction with an ACK after one cycle.
A read request could be answered by the client at any time.
Connecting a Wishbone Slave:
A Wishbone Slave could be connected to a register unit, RAM or any other unit that could
save the data once it is broadcasted on the bus.
The WS signals should be connected as followed:
Always connected: Reg_data, reg_data_valid, wr_en, ws_data, ws_data_valid, address.
Optional: typ, len, active_cycle
Stall signal: The stall signal should be driven by the client or alternatively connected
constantly to ‘0’.
An example for a connection of a Wishbone Slave to a registers unit is shown in the
following figure.
Figure 29 - Connecting a Wishbone Slave
signal name
type
width (bits)
description
sys_clk
input
1
system clock
sys_reset
input
1
system reset
ADR_I
input
(data_width_g)*(addr_d_g)
contains the addr word
DAT_I
input
data_width_g
contains the data_in word
WE_I
STB_I
input
input
1
1
CYC_I
input
1
'1' for write, '0' for read
'1' for active bus operation, '0' for no bus operation
'1' for bus transmition request, '0' for no bus transmition
request
TGA_I
input
(data_width_g)*(type_d_g)
contains the type word
TGD_I
input
(data_width_g)*(len_d_g)
contains the len word
ACK_O
output
1
'1' when valid data is transmitted to MW or for successful write
operation
DAT_O
output
data_width_g
data transmit to MW
STALL_O
output
1
STALL - WS is not available for transaction
typ
output
(data_width_g)*(type_d_g)
Type
addr
output
(data_width_g)*(addr_d_g)
the beginning address in the client that the information will be
written to
len
output
(data_width_g)*(len_d_g)
Length
wr_en
output
1
data out to registers
ws_data
output
data_width_g
write data
ws_data_valid
output
1
data valid to registers
reg_data
input
data_width_g
data to be transmitted to the WM
reg_data_valid
input
1
data to be transmitted to the WM validity
active_cycle
output
1
CYC_I outputed to user side
stall
input
1
generic name
reset_polarity_g
data_width_g
type_d_g
addr_d_g
len_d_g
stall - suspend wishbone transaction
Table 57 - whishbone slave interface
Actual value
type
description
std_logic
1
'0' = Active Low, '1' = Active High
natural
8
defines the width of the data lines of the system
positive
1
Type Depth
positive
3
Address Depth
1
positive
Length Depth
Table 58 - Wishbone Slave generics
7. Graphic User Interface (GUI)
7.1
Getting Started
The ‘FPGA setting using FLASH’ system GUI is the system’s software host, thus most of the
user operations are initiated from it. The GUI has supplies the most basic operations such as
reading, writing and erasing FLASH data. It also has some more advanced options and strong
debugging capabilities.
The GUI consists of the following regions:
Figure 30 - GUI layout
1- Register control panel – A region for building a packet aimed for a specific client.
Used both for debug and for building a data base to be stored on FLASH.
2- Packet Viewer – Packet built by the register control panel is viewed in this window.
3- FLASH control panel – A region for all FLASH operations: Read, Write, Erasure, Reset
and Storing a data base.
4- FLASH data – Data being read from FLASH is displayed here.
5- Debug options – Special features for testability such as accessing a specific client
and using text files for system transactions.
6- Message window – Displays messages for user.
7- RX & TX messages – Displays packets being sent to FPGA (RX), and packets sent
from FPGA to Host (TX).
7.2
FLASH Basic operations
The basic FLASH operations are: Read, Write, Erase and Reset.
The operations are available on the FLASH control panel:
Figure 31 - FLASH basic operations
Read – user should supply an address in the format of 6 hexadecimal bits. The address range
is 0x000000 – ox3FFFFF. 256 bytes of data read from FLASH are displayed on the ‘FLASH
data’ window (see Figure 30 - GUI layout). The data read could also be saved to a text file.
Write - user should supply an address in the format of 6 hexadecimal bits. The address range
is 0x000000 – ox3FFFFF. Data is written from a chosen text file using the ‘Browse’ button.
The text file should contain 256 data bytes at most. The format should be hexadecimal.
Every byte should be separated by a white space. for example:
Erase – Only a full sector could be erased at a time. For sector erasure user should pick a
sector from the list and press the ‘Erase Sector’ button.
Reset – Sends a reset command to the FLASH device. No reset is needed prior to other
transactions. The reset option is mostly for debug purposes.
7.2.1 Building a FLASH Data base (FLASH DB)
The ‘FPGA setting using FLASH’ system reads a data base from FLASH on system initiation.
Such a data base could be built using the GUI. To build a FLASH DB follow the steps:
1. Build a packet using the register region.
Choose:
- Read/Write <= ‘Write’
- Client
<= selected client
- Registers <= selected register
- Value
<= one hexadecimal byte
And press ‘add to packet’.
Data would be visible on the packet window
2. When done building a packet
choose ‘Add packet’ in the
FLASH region. For packet
removal choose the packet
and hit ‘Remove Packet’.
Space left on DB is written
just below the DB window.
‘Clear DB list’ button would
clear the current DB being
built.
3. Before writing the DB to
FLASH check that address
0x000000 – 0x0000FF is
erased (all bytes should be
‘FF’) by reading data. If not
than sector should be
erased.
4. Write DB to FLASH using the
‘Write DB to FLASH’ button.
The DB could be saved to file
by marking the ‘save DB to file’ checkbox.
Figure 32- FLASH DB building
7.2.2 Register directed transactions
The GUI has access to each register in the system. The GUI can make a write or read
transaction to a specific client at a time. Data Sent and data being read is available on the RX
and TX message windows.
Write transaction
Build a packet on the register region. Choose:
- Read/Write <= ‘Write’
- Client
<= selected client
- Registers <= selected register
- Value
<= one hexadecimal byte
And press ‘add to packet’.
Data would be visible on the packet window
Figure 33 -Packet Creation
When done building a packet hit
button.
Read transaction
Build a packet on the register region. Choose:
- Read/Write <= ‘Read’
- Client
<= selected client
- Registers <= first read address
- Value
<= read length
And press ‘add to packet’.
After packet is ready hit
button. If the reading request is too long a message
would be shown to user and packet won’t be sent.
7.3 Limitations
The GUI allows only specific values to specific registers. In case of a violation by the user, a
message would be shown on the message window.
The allowed values for each register are listed in the following table. For further data see the
‘FPGA setting using FLASH’ project document.
Table 59 - System registers
Client
Wait
Leds
Register #
0
0
Description Allowed Values
wait time
Enable reg
0x00 - 0xFF
0x00 - 0xFF
Leds
Leds
Leds
Leds
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Display
Error Register
Error Register
7.4
1
2
3
4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
0
1
led 1 freq
led 2 freq
led 3 freq
led 4 freq
Enable reg
line ROI - x
line ROI - y
column ROI - x
column ROI - y
damka ROI - x
damka ROI - y
line width
column width
damka width
line - R diff
line - G diff
line - B diff
column - R diff
column - G diff
column - B diff
damka - R diff
damka - G diff
damka - B diff
G start color
B start color
R start color
reg valid
Error vector
code version
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xE0
0x00 - 0xA8
0x00 - 0xE0
0x00 - 0xA8
0x00 - 0xE0
0x00 - 0xA8
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
read only
read only
Debug operations
The GUI allows user to perform debug operations. By performing debug operations some of
the system’s hardware could be tested as well as the GUI itself.
7.4.1 Sending data from a text file
This option lets the user to send data from text files similar to text files
run on simulations. For a text file transaction:
1- Choose a text file and mark the *‘update from file’ checkbox.
2- Hit ‘Send to registers’ button.
Figure 34- Sending data from a texts file
*as long as the *‘update from file’ checkbox is marked data would be sent from text file
and not by the Registers build in tool.
Important note: Text file data is not being checked for its correctness by the GUI.
7.4.2 Saving rx and TX data to file
For saving rx and TX data to file the ‘save rx to file’ and/or ‘save TX
to file’ checkboxes should be marked prior to a transaction. Then,
the data showed on the RX and TX message windows (see Figure 30
- GUI layout) would be saved to a text file chosen by the user.
Figure 35 - Saving rx and tx data to file
7.4.3 Changing or removing CRC, SOF, EOF
CRC, SOF, and EOF values may be changed or removed by marking
the checkboxes in the figure.
This option would affect only packets
Sent by the register tool and not packets sent from
Text file or FLASH tool.
Figure 36 - Changing or removing CRC, SOF, EOF
8
Data transfer
8.1 Write transaction
Registers Write Message
Value Content
0x3C SOF
remarks
Write Register Type ID
Address [23:16]
Address [15:8]
Address [7:0]
Length [7:0]
Data #1[7:0]
Data #2[7:0]
0x03 – Wait, 0x04 – Leds, 0x05 - Display
.
.
.
0xA5
Data #N[7:0]
CRC [7:0]
EOF
Polynom is 0xEA
Table 60 - Register Write Messag



Min burst is 1
Max burst is 256 limited by the size of the RAM in the RX path
Address has 24 bits to access 4MB of FLASH memory.
When data is written to a client on the system it goes through the following stages:
1 - User enters in the Matlab GUI the data to be sent.
2 – The GUI checks correctness of the data input. If the check passes data is sent on the
UART line to the RX path else an error message is displayed to the user.
3 – Data on the UART line enters the RX path in the uart_rx block, one byte at a time. The
data received is in the following format (the length in bytes is written inside the brackets
[***]):
SOF (Start Of Frame)[1] => Type [1] => Address [3] => Length [1] => Data [#data_bytes] =>
CRC[1] => EOF (End Of Frame)
4 – The uart_rx converts the data received on the UART line to an 8 bit vector and transfers
it to the mp_dec (Message Pack Decoder).
5 – The type, address and length fields are saved to registers in the mp_dec. The data bytes
are saved on the rx_path’s RAM. The CRC byte received is compared to the CRC value
calculated by the CRC block.
6 – If no errors are received (CRC error for example) the type, address and length data is
transferred to wishbone master in order to start data transfer.
7 – The wishbone master reads data from RAM and starts a wishbone bus transaction.
8 – If the bus is not occupied by another master, the WM transfers the data using wishbone
protocol to the client via wishbone_intercon unit which does the correct routing using the
type field.
9 – When successful writing of a burst is done the master will receive the ACK signal from
his slave, When the number of ACK assertion reaches the <Length + 1> the wishbone
master will end the transaction.
Write transaction example
In this example 5 data bytes are going to be written to the Led Client.



Data is entered in GUI
The following data is sent on the UART line:
3C - SOF
04 – Led client type
00 00 00 – Initial address
04 – Length of data minus one
F3 11 12 13 FF – five data bytes
1C – CRC value
A5 – EOF
Data is received by uart_rx and transferred to mp_dec. Data bytes are
written to RAM. CRC check is done.
Figure 37 –Waveform - DATA PROCCESSED IN THE RX PATH

Data are been read from the RAM to the wishbone bus via the master. The
data is received by clients and saved in registers.
Figure 38 – Waveform - Data transfer from rx_path to led client
8.2 Read transaction
Registers Read Request
Value Content
remarks
0x3C SOF
Read Register Type ID
0x62 – Wait, 0x82 – Leds, 0xA2 - Display
Address [23:16]
Address [15:8]
Address [7:0]
0x00 Length [7:0]
Always 0 on read transaction
Data [7:0]
Length of the data to be read
CRC [7:0]
Polynom is 0xEA
0xA5 EOF
**Packet is delivered first to TX_path, therefore its length is 1.
Registers Read Reply
Value Content
remarks
0x3C SOF
Read Register Type ID
Address [23:16]
Address [15:8]
Address [7:0]
Length [7:0]
Data #1[7:0]
Data #2[7:0]
0x03 – Wait, 0x04 – Leds, 0x05 - Display
.
.
.
Data #N[7:0]
Error! Reference source
not found. [7:0]
Polynom is 0xEA
0xA5 EOF
 Min burst is 1
 Max burst is 256 limited by the size of the RAM in the TX path
The read transaction is different from the write transaction and has more units participating
in it. A read request is sent to the TX path which reads the data from the client and sends the
data back to host via UART line. The following stages are made:
1 – Stages 1 to 9 of the write transaction are made with the following exceptions:
-
WM1 (rx_path) writes to WS2 (tx_path).
The length field is always 00_0x. The reason is because only one word is
written to WS2.
The data field contains the length of the data to be read.
The Type field includes both the client that should be read and the tx_path’s
wishbone slave in the following pattern:
Type[3 to 0] = “0010” which is WS2 on the tx_path
Type[7 to 5] = <type of client that will be read>
2 – WS2 sends the data received to the message encoder in the tx_path.
Host to Flash
Data from host to FLASH makes the following path:
1. From Host to RX Path via UART_IN line.
2. The RX Path unwraps the data and transfers it to through the Wishbone bus to the
FCB and then to the Flash.
Flash to Clients
Data from FLASH to clients makes the following path:
1. The FCB initiates a reading transaction and reads data from Flash.
2. All data for a specific configuration is transferred to the RAM on CCB using the FCB.
3. The CCB sends all the data to the clients via Wishbone bus.
Data sent back to host from Flash - Debug
Data sent back to host from FLASH makes the following path.
1. WBM1 (RX Path) initiates the transaction and orders WBS1 (TX Path) to begin a
read transaction.
2. WBM2 (TX Path) orders the FCB to transfer data from Flash.
3. Data is transferred to RAM on TX Path via FCB and Wishbone bus.
4. Data is wrapped and sent to host via UART_OUT line.
9
FLASH Memory
Figure 39- Flash schematic symbol and schematics
1. The flash
memory used in the system is the spansion S29AL032D included in the Altera DE2
development board. The flash uses Common Flash Interface (CFI) in its interface
with the Cyclone II FPGA. CFI has been created to allow a system designer the
flexibility to design products now that can use both current and future flash memory
devices, as well as the security of knowing that second source products may be used
without system software modifications.
2. Pin Configuration:
A0-A20
DQ0-DQ14
DQ15/A-1 DQ15
address inputs
15 data inputs/outputs
(data input/output, word mode), A-1 (LSB address input, byte
BYTE#
CE#
OE#
WE#
RESET#
WP#/ACC
ACC
Selects 8-bit or 16-bit mode
Chip enable
Output enable
Write enable
Hardware reset pin
Hardware Write Protect input/Programming Acceleration input.
Hardware Write Protect input
mode)
10 Testability
TOP LEVEL TESTING WAS DONE USING THE CONFIGURATION SEEN IN THE FIGURE:
Figure 40- Top level Test Environment
The uart_tx_gen_model integrated from the RunLen project is a unit that reads data from a
text file and sends it to the RX path via UART protocol.
Top Synthesis contains all the system on the FPGA as seen on figure 1.
VESA picture collector integrated from the RunLen project collects the data broadcast to the
screen by the display client and exports a BMP file for each frame.
Uart_rx and Uart_rx_compare_model sample the uart_out output and compare it to the
expected data that should arrive on a read transaction.
The FLASH simulation model (s29al032d_03_04.v) simulates the FLASH memory.
The GUI has the ability to create a text file of a transaction chosen by the user. It can also
read text files used for simulation and transmit them to the hardware.
This test environment gives an easy way to simulate the system behavior. By editing text
files or generating text files using the GUI a variety of scenarios can be tested. A test is
determined successful or not by examining the waveforms and comparing them to the
expected waveforms. If the test examines the display client it can be determined successful
or not by observing the picture generated by the VESA picture collector.
The following tests were run on the system:
1234567-
5 word write transaction to Led client.
1 word write transaction to Led client.
Two sequent write transactions to Led Client.
3 words read transaction with Led client.
1 word read transaction with Led client.
Two sequent read transactions to Led Client.
3 sequent transactions with led client: write => read => write.
89101112131415161718192021222324252627282930313233343536373839404142434445464748-
Write to a Led register the value 00_0x.
Write transaction to Wait client.
2 sequent write transactions to Wait client.
Write 00_0x to Wait client.
Sequent transactions to different clients: Write to Led => Write to wait => Read from
Led
Reading the error register value (WS1 – inside the rx_path).
System reset while a wishbone active cycle occurs.
2 successive read transactions for each client.
Display lines picture
Display columns picture
Display damka picture
Display default picture
Register update while an active frame is being transmitted
Display frame, change the ROI, display another frame
Check ROI max and min values
Enabling more 2 formats [(lines, columns) or (lines, damka) or (damka, columns) ]
Enabling 3 formats
Reset while a frame transmission takes place.
Functionality while vesa_enable = ‘0’
Functionality while vesa_enable = ‘1’ and picture_enable = ‘0’
Reading from display registers (single, burst, 2 successive reads).
Change lines width
Change lines color difference
Change columns width
Change columns color difference
Change damka width
Change damka color difference
Changing the start colors
Test the display client with different generics (Runlen project generics).
First configure of the flush with the entire size of the RAM.
A flash reads transaction with different size of data including 1 and 256 bytes.
A flash writes transaction with different size of data including 1 and 256 bytes.
An erasure of a sector in the flush.
A sequential read & write transactions.
Executing reset while read transaction.
Entering to sleep mode and returning to active mode.
Read request in the middle of transaction.
Forcing the ccb_disable, and config_again switches.
Configuration of read and write with different clocks rate (200MHz, 205MHz).
Watchdog testing.
Write request to illegal address.
11 Synthesis
As seen in Quartus report below the system withstands timing analysis and uses 13% of the
FPGA’s total logic elements.
Figure 41- Quartus Synthesis results
The maximum frequency is 134.25MHZ which is far above the maximum required
frequency:100MHz.
Figure 42 - Quartus timing analysis
11.1 Debugging the hardware
After code generation and simulations, the synthesis phase does not always go smooth so
we needed to overcome some obstacles. It is never fun to encounter bugs in the design, but
these bugs also grant us knowledge for future work. Below we represent problems we
handled and solved during the debug process.
Problem: First programming on FPGA…nothing happens
Source: The reset button on the DE2 board is active low while our generic for reset is active
high
Solution: Change the reset_activity_polarity_g generic to ‘0’.
Conclusion: The ‘Programming indication led’ is found useful.
Problem: Writes effect only register address 0.
Source: A FF was not implemented by synthesis because ‘clk’ signal was not mentioned in a
process sensitivity list
Figure 43 - Address advancer - error causing code
Solution: Using signaltap found a bug at the address advancer (inside clients registers)
Conclusion: When a problem occurs at the hardware but not on simulation, take a look at
Quartus warnings and compilation report
Problem: No Display
Source: Forgot to allocate one pin in the pin allocation script
Solution: Using signaltap found hardware is OK. Pin allocation script was repaired
Conclusion: Double check the pin allocation script
12 Project educational value
Besides creating a functional working hardware the project has an educational value.
Throughout the project we’ve learned:
•
Planning and Specifying a Project
•
Writing reusable generic code
•
Protocols: UART, Wishbone, VESA
•
Integration of many components
•
Verify logic correctness using waveforms, text files, BMP files and scripts
•
Testing our hardware using GUI and debug with signaltap
•
Documentation of the work done
•
Code Review and running a project diary are useful tools
13 System analysis
The system is implemented with effort to stand at good throughput and delay.
Thing that was taken into account while implementation:
13.1 Reducing the total number of cycle in transaction:
At the beginning the wishbone communication was implemented as the classic standard:
After that one byte was send, The system waited to receives his acknowledge, and just then
the next byte was send. That’s means that there was a wasted time.
T(time_sending_one_byte_std) = 12 cyc
We improved the system throughput by adding pipeline mode:
All the bytes are sends one after the other, and the received ack’s are counted to ensure all
byte was successfully received. In that way while waiting for the acknowledges, other byte
are sends. Every cycle one byte is sends and his acknowledge is receiving in the next cycle.
T(time_sending_one_byte_pipe) = 1 cyc
Speedup = T(time_sending_one_byte_std) / T(time_sending_one_byte_pipe) = 12
13.2 Parallelism
We saw in chapter 6.6 – Filter that the CCB can activate the Flash only when the
ccb_disable signal is not(ccb_disable_polarity_g), after he was stabilized from his DE2
switch.
The filter block output the stable signal after 3 msec.
When the CCB will activate the flash control, it will take 20 usec to load all the data to the
flash control’s RAM (70 nsec per byte x 256 bytes).
Instead of waiting idle while the ccb_disable is stabilized and just then start to load the data
from the flush, the data will be load from the flash to the RAM anyway, and ONLY if the
ccb_disable signal will stabilize on the right polarity, the CCB will read the data. That way
the total time waited for the data will be 3msec instead of 3msec+20 usec.
13.3 Watchdog
In order to avoid from a system hang possibility, we implemented in the wishbone master a
watchdog timer, that will prevent the case that a master will wait a very long time for his
slave response, that maybe by error (BUG) won’t be send, and all that time the bus will be
busy.
When a master will wait for a response from his slave for timeout time, the wishbone
intercone will reset this master and prevent a hang on the system
14 An application example
In this project, FPGA setting using FLASH, we implemented a system that enables the user
to configure clients according to data that stored in memory.
Why this is good?
Let’s think about a servo that control many different devices, by determine for every device
his unique Pulse-width modulation (PWM is a commonly used technique for controlling
power & frequency to inertial electrical devices).
In order to prevent the case that when the servo is switch back on there will be some
default garbage value on the frequency input of the devices, the servo will function as a
client of the FPGA setting using FLASH system, and will load from the Flash memory the
right configuration for every devices.
Another aspect, Instead that after every re-boot of the servo someone will have to update
the data that control the right frequency for all the devices, all will have to be done is load
the data from the flash memory.
15
Appendix

Project in SVN:
http://fpga-setting-using-flash.googlecode.com/svn/

GUI user guide in SVN:
http://fpga-setting-using-flash.googlecode.com/svn/DOC/Project%20document/GUI_user_guide/

Final A video:
http://youtu.be/1WO0tO4A9YY

Final B video:
http://www.youtube.com/watch?v=LWtR658IBrc&list=HL1354090092&feature=mh
_lolz