MSP430 Teaching Materials
Chapter 4
MSP430 Architecture
Hacettepe University
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Anatomy of a Typical Small
Microcontroller
Central processing unit
 Arithmetic logic unit (ALU), which
performs computation.
 Registers needed for the basic operation
of the CPU, such as the program
counter (PC), stack pointer (SP), and
status register (SR) and some registers
to hold temporary results.
 Instruction decoder and other logic to
control the CPU, handle resets, and
interrupts, and so on
 Memory for the program: Nonvolatile (readonly memory, ROM), retains its contents when
power is removed.
 Memory for data: Random-access memory
(RAM) and usually volatile.
 Input and output ports: To provide digital
communication with the outside world.
 Address and data buses: To link these
subsystems to transfer data and instructions.
 Clock: To keep the whole system synchronized.
It may be generated internally or obtained from a
crystal or external source; modern MCUs offer
considerable choice of clocks
Peripherals to add?
 Timers: Most microcontrollers have at least one timer
because of the wide range of functions that they provide.
 The time at which transitions occur on an input can be
recorded. This may be used to deduce the speed of a
bicycle, for instance, if the input is driven by a sensor
that gives a pulse every time the wheel completes a
revolution.
 Outputs can be driven on and off automatically at a
specified frequency. This is used for pulse-width
modulation to control the speed of the motor in a
washing machine, described previously.
 They provide a regular “tick” that can be used to
schedule tasks in a program.
 Many programs are awakened periodically by the timer
to perform some action—measure the temperature and
transmit it to a base station, for example—then go to
sleep (enter a low-power mode) until awakened again.
This conserves power, which is vital in battery-powered
applications.
 Watchdog timer: This is a safety feature, which resets the processor
if the program becomes stuck in an infinite loop.
 Communication interfaces: Several choice of interfaces are
available to exchange information with another IC or system. They
include serial peripheral interface (SPI), inter-integrated circuit (I²C or
IIC), asynchronous (such as RS-232), universal serial bus (USB),
controller area network (CAN), ethernet, and many others.
 Nonvolatile memory for data: This is used to store data whose
value must be retained when power is removed. Serial numbers for
identification and network addresses are two obvious candidates.
 Analog-to-digital converter: This is very common because so many
quantities in the real world vary continuously.
 Digital-to-analog converter: This is much less common, because
most analog outputs can be simulated using PWM. An important
exception used to be sound, but even here, the use of PWM is growing
in what are called class D amplifiers.
 Real-time clock: These are needed in applications that must track the
time of day.
 Monitor, background debugger, and embedded emulator: These
are used to download the program into the MCU and communicate with
a desktop computer during development
Memory
 Volatile: Loses its contents when power is removed. RAM
 Nonvolatile: Retains its contents when power is removed and is
therefore used for the program and constant data. Usually slower
than writing to RAM
 Masked ROM: The data are encoded into one of the masks
used for photolithography and written into the IC during
manufacture. This memory really is read-only. Used for the
high-volume production of stable products, because any
change to the data requires a new mask to be produced at
great expense. Some MSP430 devices can be ordered with
ROM, shown by a C in their part number. For ex:
MSP430CG4619.
 EPROM (electrically programmable ROM): As its name
implies, it can be programmed electrically but not erased.
Devices must be exposed to ultraviolet (UV) light for about ten
minutes to erase them. The usual black epoxy encapsulation is
opaque, so erasable devices need special packages with quartz
windows, which are expensive. These were widely used for
development before flash memory was widely available.
 OTP (one-time programmable memory): This is just
EPROM in a normal package without a window, which means
that it cannot be erased. Devices with OTP ROM are still widely
used and the first family of the MSP430 used this technology.
Memory
 Flash memory: This can be both programmed and erased
electrically and is now by far the most common type of
memory. It has largely superseded electrically erasable,
programmable ROM (EEPROM). The practical difference is
that individual bytes of EEPROM can be erased but flash can
be erased only in blocks. Most MSP430 devices use flash
memory, shown by an F in the part number
Harvard and von Neumann Architectures
 The volatile (data) and nonvolatile (program)
memories are treated as separate systems, each
with its own address and data bus.
 Simulataneous Access!
 Individually Optimized.
 Microchip PICs, the Intel 8051 and the
ARM9.
 Von Neumann
 Easier architecture.
 MSP430, Freescale HCS08, and the ARM7.
Software Choices
 C: The most common choice for small microcontrollers nowadays.
A compiler translates C into machine code that the CPU can
process. This brings all the power of a high-level language—data
structures, functions, type checking and so on—but C can usually
be compiled into efficient code. Compiler produces machine code
directly.
 C++: An object-oriented language that is widely used for larger
devices. A restricted set can be used for small microcontrollers
but some features of C++ are notorious for producing highly
inefficient code. Embedded C++ is a subset of the language
intended for embedded systems.
 Java is another object-oriented language, but it is interpreted
rather than compiled and needs a much more powerful processor.
 BASIC: Available for a few processors, of which the Parallax
Stamp is a well-known example. The usual BASIC language is
extended with special instructions to drive the peripherals. This
enables programs to be developed very rapidly, without detailed
understanding of the peripherals. Disadvantages are that the code
often runs very slowly and the hardware is expensive if it includes
an interpreter.
Contents
UBI
 MSP430 architecture:
 Main characteristics
 Architecture topology
 Address space
 Interrupt vector table
 Central Processing Unit (MSP430 CPU)
 Central Processing Unit (MSP430X CPU)
 Addressing modes
 Instructions set
 Quiz
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Introduction
UBI
 A comprehensive description of the MSP430
architecture, covering its:
 Main characteristics;
 Device architecture;
 Address space;
 Interrupt vector table;
 Central Processing Unit (MSP430 CPU and MSP430X CPU);
 7 seven addressing modes and instruction set composed of:
• 27 base opcodes;
• 24 emulated instructions.
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Microcontroller characteristics
UBI
 Integration: Able to implement a whole design onto a single
chip.
 Cost: Are usually low-cost devices (a few $ each);
 Clock frequency: Compared with other devices
(microprocessors and DSPs), MCUs use a low clock frequency:
 MCUs today run up to 100 MHz/100 MIPS (Million
Instructions Per Second).
 Power consumption: Low power (battery operation);
 Bits: 4 bits (older devices) to 32 bits devices;
 Memory: Limited available memory, usually less than 1 MByte;
 Input/Output (I/O): Low to high (8 to 150) pin-out count.
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MSP430 main characteristics (1/3)
UBI
 Low power consumption:
 0.1 A for RAM data retention;
 0.8 A for real-time clock mode operation;
 250 A/MIPS during active operation.
 Low operation voltage (from 1.8 V to 3.6 V);
 < 1 s clock start-up;
 < 50 nA port leakage;
 Zero-power Brown-Out Reset (BOR).
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MSP430 main characteristics (2/3)
UBI
 On-chip analogue features:
 10/12/16-bit Analogue-to-Digital Converter (ADC);
 12-bit dual Digital-to-Analogue Converter (DAC);
 Comparator-gated timers;
 Operational Amplifiers (Op Amps);
 Supply Voltage Supervisor (SVS).
 16 bit Von Neumann RISC CPU:
 Compact core design reduces power consumption and cost;
 16-bit data bus;
 27 core instructions;
 7 addressing modes;
 Extensive vectored-interrupt capability.
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MSP430 main characteristics (3/3)
UBI
 Flexibility:
 Up to 256 kByte Flash;
 Up to 100 pins;
 USART, I2C, Timers;
 LCD driver;
 Embedded emulation;
 And many more peripherals modules…
 Microcontroller performance:
 Instruction processing on either bits, bytes or words
 Reduced instructions set;
 Compiler efficient;
 Wide range of peripherals;
 Flexible clock system.
 1.8–3.6V operation
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MSP430 Architecture
UBI
 Block diagram:
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Address Space
UBI
 Mapped into a single, contiguous address space:
 All memory, including RAM, Flash/ROM, information
memory, special function registers (SFRs), and peripheral
Memory Address
Description
Access
registers.
End:
0FFFFh
Interrupt Vector Table
Word/Byte
Start:
End:
 Memory Map:
Flash/ROM
Start *:
End *:
Start:
End:
Start:
End *:
Start:
End:
Start:
End:
Start:
End:
Start:
>> Contents
0FFE0h
0FFDFh
0F800h
01100h
010FFh
0107Fh
01000h
0FFFh
0C00h
09FFh
027Fh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
Word/Byte
Information Memory
(Flash devices only)
Boot Memory
(Flash devices only)
Word/Byte
RAM
Word/Byte
Word/Byte
16-bit Peripheral modules
Word
8-bit Peripheral modules
Byte
Special Function Registers
Byte
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Address Space
UBI
 Random access memory: Used for variables. This always starts at
address 0x0200 and the upper limit depends on the size of the RAM.
The F2013 has 128 B.
 Bootstrap loader: Contains a program to communicate using a
standard serial protocol, often with the COM port of a PC. This can
be used to program the chip but improvements in other methods of
communication have made it less important than in the past,
particularly for development. All MSP430s had a bootstrap loader
until the F20xx, from which it was omitted to improve security.
 Information memory: A 256B block of flash memory for storage of
nonvolatile data. Such as an address for a network, or variables that
should be retained even when power is removed. For example, a
printer might remember the settings from when it was last used and
keep a count of the total number of pages printed.
 Code memory: Holds the program, including the executable code
itself and any constant data. The F2013 has 2KB but the F2003 only
1KB.
 Interrupt and reset vectors: Used to handle “exceptions,” when
normal operation of the processor is interrupted or when the device
is reset. This table was smaller and started at 0xFFE0 in earlier
devices.
>> Contents
Interrupt vector table
UBI
 Mapped at the very end of memory space (upper 16 words of
Flash/ROM): 0FFE0h - 0FFFEh (4xx devices);
 Priority of the interrupt vector increases with the word
address.
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Central Processing Unit (MSP430 CPU)
(1/7)
UBI
 RISC (Reduced Instructions Set Computing)
architecture:
 Instructions are reduced to the basic ones (short set):
• 27 physical instructions;
• 24 emulated instructions.
 This provides simpler and faster instruction decoding;

Interconnect by a using a common memory address bus
(MAB) and memory data bus (MDB) - Von Neumann
architecture:
• Makes use of only one storage structure for data and
instructions sets.
• The separation of the storage processing unit is implicit;
• Instructions are treated as data (programmable).
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UBI
Central Processing Unit (MSP430 CPU)
(2/7)
 RISC (Reduced Instructions Set Computing) type
architecture:
 Uses a 3-stage instruction pipeline containing:
• Instruction decoding;
• 16 bit ALU;
• 4 dedicated-use registers;
• 12 working registers.
 Address bus has 16 bit so it can address 65 kB (including
RAM + Flash + Registers);
 Arithmetic Logic Unit (ALU):
 Addition, subtraction, comparison and logical (AND, OR,
XOR) operations;
 Operations can affect the overflow, zero, negative, and carry
flags of the SR (Status Register).
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Central Processing Unit (MSP430 CPU)
(3/7)
UBI
 Incorporates sixteen 16-bit registers:
• 4 registers (R0, R1, R2 and R3) have dedicated functions;
• 12 register are working registers (R4 to R15) for general
use.
 R0: Program Counter (PC):
 Points to the next instruction to be read from memory and
executed by the CPU.
 R1: Stack Pointer (SP):
 1st: stack can be used by user to store data for later use
(instructions: store by PUSH, retrieve by POP);
 2nd: stack can be used by user or by compiler for subroutine
parameters (PUSH, POP in calling routine; addressed via offset
calculation on stack pointer (SP) in called subroutine);
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Central Processing Unit (MSP430 CPU)
(4/7)
UBI
 R1: Stack Pointer (SP) (continued):
 3rd: used by subroutine calls to store the program counter
value for return at subroutine's end (RET);
 4th: used by interrupt - system stores the actual PC value
first, then the actual status register content (on top of stack)
on return from interrupt (RETI) the system get the same
status as just before the interrupt happened (as long as none
has changed the value on TOS) and the same program
counter value from stack.
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Central Processing Unit (MSP430 CPU)
(5/7)
UBI
 R2: Status Register (SR):
 Stores status and control bits;
 System flags are changed automatically by the CPU;
 Reserved bits are used to support the constant generator.
15
14
13
12
11
10
9
8
Reserved for CG1
Bit
7
V
6
SCG1
5
SCG0
OSCOFF
4
CPUOFF
3
GIE
2
N
1
Z
C
Description
8
V
Overflow bit. V = 1  Result of an arithmetic operation overflows the signed-variable range.
7
SCG1
System clock generator 0. SCG1 = 1
SMCLK
6
SCG0
System clock generator 1. SCG0 = 1
5
OSCOFF
Oscillator Off. OSCOFF = 1
4
CPUOFF
CPU off. CPUOFF = 1
3
GIE
General interrupt enable. GIE = 1
2
N
Negative flag. N = 1

1
Z
Zero flag. Z = 1
result of a byte or word operation is 0.
0
C
Carry flag. C = 1
>> Contents






DCO generator is turned off – if not used for MCLK or
FLL+ loop control is turned off
turns off LFXT1 when it is not used for MCLK or SMCLK
disable CPU core.

enables maskable interrupts.
result of a byte or word operation is negative.
result of a byte or word operation produced a carry.
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24
UBI
 CPUOFF, OSCOFF, SCG0, and SCG1, which control the
mode of operation of the MCU. Setting various
combinations of these bits puts the MCU into one of its lowpower modes, which is described in the section “Low-Power
Modes of Operation”
 All bits are clear in the full-power, active mode. This is the
main effect of setting each bit in the MSP430F2xx:
 CPUOFF disables MCLK, which stops the CPU and any
peripherals that use MCLK.
 SCG1 disables SMCLK and peripherals that use it.
 SCG0 disables the DC generator for the DCO (disables the
FLL in the MSP430x4xx family).
 OSCOFF disables VLO and LFXT1.
>> Contents
UBI
>> Contents
Central Processing Unit (MSP430 CPU)
(6/7)
UBI
 R2/R3: Constant Generator Registers (CG1/CG2):
 Depending of the source-register addressing modes (As)
value, six constants can be generated without code word or
code memory access to retrieve them.
 This is a very powerful feature which allows the
implementation of emulated instructions, for example,
instead of implement a core instruction for an increment the
constant generator is used.
Register
As
Constant
Remarks
R2
00
-
Register mode
R2
(0)
R2
01
10
00004h
Absolute mode
+4, bit processing
R2
11
00008h
+8, bit processing
R3
00000h
R3
R3
00
01
10
00001h
00002h
0, word processing
+1
+2, bit processing
R3
11
0FFFFh
-1, word processing
>> Contents
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UBI
Central Processing Unit (MSP430 CPU)
(7/7)
 R4 - R15: General–Purpose Registers:
 These general-purpose registers are adequate to store data
registers, address pointers, or index values and can be
accessed with byte or word instructions.
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UBI
Central Processing Unit (MSP430X CPU)
(1/10)
 Main features of the MSP430X CPU architecture:
 The MSP430X CPU extends the addressing capabilities of the
MSP430 family beyond 64 kB to 1 MB;
 To achieve this, some changes have been made to the
addressing modes and two new types of instructions have
been added;
 One instruction type allows access to the entire address
space, and the other is designed for address calculations;
 The MSP430X CPU address bus has 20 bits, although the
data bus still has 16 bits. Memory accesses to 8-bit, 16-bit
and 20-bit data are supported;
 Despite these changes, the MSP430X CPU remains
compatible with the MSP430 CPU, having a similar number
of registers.
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UBI
Central Processing Unit (MSP430X CPU)
(2/10)
 Organization of the MSP430X CPU:
 Although the MSP430X CPU structure is
similar to that of the MSP430 CPU, there
are some differences that will now be
highlighted;
 With the exception of the status register
SR, all MSP430X registers are 20 bits;
 The CPU can now process 20-bit or 16bit data.
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UBI
Central Processing Unit (MSP430X CPU)
(3/10)
 The MSP430X CPU has 16 registers, some of which have
special use:
 R0 (PC) Program Counter:
 Has the same function as the MSP430 CPU, although now it
has 20 bits.
 R1 (SP) Stack Pointer:
 Has the same function as the MSP430 CPU, although now it
has 20 bits.
 R2 (SR) Status Register:
 Has the same function as the MSP430 CPU, but it still has 16
bits.
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UBI
Central Processing Unit (MSP430X CPU)
(4/10)
 R2 (SR) Status Register:
 Description of the SR bits:
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UBI
Central Processing Unit (MSP430X CPU)
(5/10)
 R2 (SR/CG1) and R3 (CG2) Constant Generators:
 Registers R2 and R3 can be used to generate six different
constants commonly used in programming, without adding
an additional 16-bit word to the instruction;
 The constants are fixed and are selected by the (As) bits of
the instruction. (As) selects the addressing mode.
 Values of constants
generated:
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UBI
Central Processing Unit (MSP430X CPU)
(6/10)
 R2 (SR/CG1) and R3 (CG2) Constant Generators:
 Whenever the operand is one of the six constants, the
registers are selected automatically;
 Therefore, when used in constant mode, registers R2 and R3
cannot be used as source registers.
 R4-R15 – General-purpose registers:
 Have the same function as in the MSP430 CPU, although
they now have 20 bits;
 These registers can process 8-bit, 16-bit or 20-bit data;
 If a byte is written to one of these registers it takes bits 7:0,
the bits 19:8 are filled with zeroes. If a word is written to
one of these registers it takes bits 15:0, the bits 19:16 are
filled with zeroes.
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UBI
Central Processing Unit (MSP430X CPU)
(7/10)
 R4-R15 – General-purpose registers:
 Handling byte data (8 bits) using the suffix .B:
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UBI
Central Processing Unit (MSP430X CPU)
(8/10)
 R4-R15 – General-purpose registers:
 Handling word data (16 bits) using the suffix .W:
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UBI
Central Processing Unit (MSP430X CPU)
(9/10)
 R4-R15 – General-purpose registers:
 Manipulation of a 20-bit address using the suffix .A:
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UBI
Central Processing Unit (MSP430X CPU)
(10/10)
 All other differences in the addressing modes, instruction
set and other details for the CPUX architecture present in
MSP430 devices which have over 64kB of on chip
memory are described in much greater depth in text
book.
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Addressing modes
UBI
 7 addressing modes for the source operand:
 4 addressing modes for the destination operand:
 Register mode; Indexed mode; Symbolic mode; Absolute
mode.
 For the destination operand, two additional addressing
modes can be emulated.
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Register Mode
UBI
 mov.w R5 ,R6 ; move (copy) word from R5 to
R6
 The PC is incremented by 2 while the instruction
is being fetched, before it is used as a source.
 The constant generator CG2 reads 0 as a source.
 Both PC and SP must be even because they
address only words, so the lsb is discarded if they
are used as the destination.
 SR can be used as a source and destination in
almost the usual way although there are some
details about the behavior of individual bits.
 As = 00
>> Contents
Indexed Mode
UBI
 mov.b 3(R5),R6 ; load byte from address 3+(R5)
into R6
 Indexed addressing can be used for the
source, destination, or both
 R5 is used for the index here
 C takes account of the size of the object when
calculations are performed with pointers.
Suppose that Words[] is an array of words. In
C the two expressions Word[i] and *(Word+i)
are equivalent. The corresponding indexed
address would be Word(R5) with R5=2i
because each word is 2 bytes long.
 As = 01
>> Contents
Symbolic Mode (PC Relative)
UBI
 mov.w LoopCtr ,R6 ; load word LoopCtr into R6 ,
symbolic mode
 Similar to mov.w X(PC),R6 ; load word
LoopCtr into R6 , symbolic mode
 Memory contents before operation:
Location FOO=1000 Location BAR=A5A5
Operation:
mov FOO,BAR ; Copies contents of FOO into BAR
 Memory contents before operation:
Location FOO=1000 Location BAR=1000
 As = 01
>> Contents
Absolute Mode
UBI
 mov.b &P1IN ,R6 ; load byte P1IN into R6 ,
absolute mode
 mov.b P1IN(SR),R6 ; load byte P1IN into R6 ,
absolute mode
 where P1IN is the absolute address of the
register
 As = 01
>> Contents
Indirect Register Mode
UBI
 mov.w @R5 ,R6 ; load word from address
(R5)=4 into R6
 The address of the source is 4, the value in R5.
Thus a word is loaded from address 4 into R6.
The value in R5 is unchanged.
 Indirect addressing cannot be used for the
destination so indexed addressing must be
used
• mov.w R6 ,0( R5) ; store word from R6 into address
0+(R5)=4
>> Contents
Indirect Autoincrement Register Mode
UBI
 available only for the source
 mov.w @R5+,R6
 A word is loaded from address 4 into R6 and the
value in R5 is incremented to 6 because a word
(2 bytes) was fetched.
 Useful when stepping through an array or table,
where expressions of the form *c++ are often
used in C. Instead use:
 mov.w R6 ,0( R5) ; store word from R6 into
address 0+(R5)=4
 incd.w R5 ; R5 += 2
 For indirect register mode W(S) = 10.
 For indirect autoincrement mode, W(S) = 11.
>> Contents
Immediate Mode
UBI
 mov.w @PC+,R6 ; load immediate word into R6
 PC is automatically incremented after the
instruction is fetched and therefore points to the
following word.
 The instruction loads this word into R6 and
increments PC to point to the next word, which in
this case is the next instruction. The overall effect
is that the word that followed the original
instruction has been loaded into R6.
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Instruction set
UBI
 27 core instructions;
 24 emulated instructions;
 The instruction set is orthogonal;
 The core instructions have unique opcodes decoded by
the CPU, while the emulated ones need assemblers and
compilers for their mnemonics;
 There are three core-instruction formats:
 Double operand; add.w src, dst, dst += src
 Single operand;
 Program flow control - Jump.
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Quiz (1/7)
UBI
 1. The number and types of instructions used by the
MSP430 CPU are:
(a) 27 core instructions;
(b) 20 core instructions and 14 emulated ones;
(c) 27 core instructions and 24 emulated ones;
(d) 24 core instructions.
 2. The MSP430 RISC type CPU is:
(a) Based on a reduced instruction set;
(b) Based on pure pattern matching and absence of
instructions;
(c) Based on a complex instruction set;
(d) A CPU without peripherals connections.
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Quiz (2/7)
UBI
 3. The von Neumann architecture used for the MSP430:
(a) Has the data storage entirely contained within the data
processing unit;
(b) Has physically separate storage and signal pathways for
instructions and data;
(c) Has a separate bus just for peripherals;
(d) Has program, data memory and peripherals all sharing a
common bus structure.
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Quiz (3/7)
UBI
 4. The ALU in the MSP430 CPU handles:
(a) Addition, subtraction, multiplication and division operations;
(b) Addition, subtraction, comparison and logical (AND, OR,
XOR) operations;
(c) Addition, subtraction, multiplication and comparison
operations;
(d) Addition, subtraction, multiplication and logical (AND, OR,
XOR) operations.
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Quiz (4/7)
UBI
 5. The MSP430 CPU incorporates:
(a) 14 registers (2 for dedicated functions and 12 for work);
(b) 16 registers (6 for dedicated functions and 10 for work);
(c) 18 registers (4 for dedicated functions and 14 for work);
(d) 16 registers (4 for dedicated functions and 12 for work).
 6. The Program Counter (PC):
(a) Stores the return addresses of subroutine calls and
interrupts;
(b) Points to the next instruction to be read from memory and
executed by CPU;
(c) Stores state and control bits;
(d) Points to the next instruction to be written in memory.
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51
Quiz (5/7)
UBI
 7. The result of the Status Register SR = 0x0104 indicates:
(a) Arithmetic operation result overflows the signed-variable
range and produced a carry;
(b) Arithmetic operation result overflows the signed-variable
range which result is negative, when maskable interrupts are
enabled;
(c) Arithmetic operation result is negative and produced a carry;
(d) CPU is disabled and the maskable interrupts are enabled.
 8. The MSP430 Status Register (SR) bit:
(a) V is set when the result of a byte or word operation
overflows;
(b) Z is set when the result of a byte or word operation is zero;
(c) all of the above;
(d) none of the above.
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Quiz (6/7)
UBI
 9. The MSP430 supports on two-address-instructions:
(a) Seven addressing modes for the source operand and three
addressing modes for the destination operand;
(b) Six addressing modes for the source operand and four
addressing modes for the destination operand;
(c) Seven addressing modes for the source operand and four
addressing modes for the destination operand;
(d) Six addressing modes for the source operand and three
addressing modes for the destination operand.
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53
Quiz (7/7)
UBI
 Answers
 1. (c) 27 core instructions and 24 emulated instructions.
 2. (a) Based on a reduced instruction set.
 3. (d) has program, data memory and peripherals all
sharing a common bus structure.
 4. (b) Addition, subtraction, comparison and logical (OR,
AND, XOR) operations.
 5. (d) 16 registers (4: dedicated functions and 12 working).
 6. (b) Points to the next instruction to be read from memory
and executed by the CPU.
 7. (b) Arithmetic operation result overflows the signedvariable range when result is negative, when maskable
interrupts are enabled.
 8. (c) all of the above.
 9. (c) Seven for the source operand and four addressing
modes for the destination operand.
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