Low Cost FPGAs
March 2006
Bringing the Best Together
LatticeECP2 – Low Cost & High Performance
 Low Cost, LUT-based FPGA
–
–
–
–
6K to 70K LUT4s
12K to 136K bits distributed memory
95 to 628 I/O
High volume prices as low as $0.50 per 1K LUTs
 Flexible sysIOTM Buffers
– LVCMOS 33/25/18/15/12, PCI
– SSTL3/2/18 & HSTL15 & HSTL18
– Bus-LVDS, MLVDS, LVPECL & LVDS
 Pre-engineered Source Synchronous I/Os
– DDR2 (400Mbps)
Low Cost
840Mbps Parallel I/O
Bitstream Encryption
28 GMAC DSP
400Mbps DDR2
 sysDSPTM High Performance DSP Support
– 12 to 88 18x18 multipliers
 sysMEMTM Block Memory
– 55K to 1M bits
 sysCLOCKTM PLL and DLL
 Enhanced Configuration Support
– Configuration bitstream encryption
– Transparent updates
– Dual boot support
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
LatticeECP2 – Architecture
Flexible sysIO
Buffers:
LVCMOS,
HSTL,SSTL,
LVDS, ++
Programmable
Function Units
(PFUs)
DSP Blocks
Multiply and
Accumulate
Support
Pre-Engineered
Source
Synchronous
Support
DDR2 – 400Mbps
Generic – 840Mbps
sysMEM Block
RAM 18kbit
Dual Port
Flexible Routing
Optimized for
Speed, Cost and
Routability
sysCLOCK PLLs
& DLLs
Frequency
Synthesis & Clock
Alignment
Config. Logic
Inc Dual Boot,
Encryption &
Transparent
Updates
On-Chip Oscillator
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Configuration Port
Breakthrough!
Bringing the Best Together
Optimized Programmable Function Unit (PFU)
Carry Chain
SLICE 3
LUT4
 PFU Resources Optimized
– Best match to applications
– Best speed
– Best cost
LUT4
SLICE 2
LUT4
FF
 Tools Tuned To Optimally Use
Available Resources
LUT4
FF
From
Routing
SLICE 1
To
Routing
LUT4
FF
LUT4
FF
SLICE 0
LUT4
FF
LUT4
FF
Logic Block (PFU)
Slice 0
Slice 1
Slice 2
Slice 3
LUT4
ROM
Carry
FF
RAM1
















1. Available in 25% of the PFUs
Carry Chain
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
Extensive High Performance Clocking
 High Performance Clock Distribution
– Eight global clock networks
– Eight regional secondary clocks
– Two low-skew edge clocks per side
 sysCLOCK PLL and DLL Technology
– 2 to 6 PLLs per device
» External capacitor allows operation as low as 1MHz
» Dynamic phase shift capability
– 2 DLLs per device
» Includes slave delay for source synchronous implementations
 On-Chip Oscillator (Typ 130MHz)
 Edge Clock Divider
– X2, X4, X8
– For high speed source synchronous implementations
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
sysCLOCK PLL
Dynamic Adjust
Dynamic Adjust
CLOCK IN
(From pin or
routing)
Feedback
(From post scalar
divider, clock net
or external pin)
LOCK
Input Clock
Divider
(CLKI)
Feedback
Divider
(CLKFB)
Delay
PLL
Adjust*
Post Scalar
Divider
(CLKOP)
CLOCK OUT
CLOCK OUT
+/- 8 Steps
130ps Nominal
Optional
External Capacitor







Phase &
Duty
Select
Secondary
Clock
Divider
(CLKOK)
CLOCK OUT
* GPLL Only
Two General Purpose PLLs (GPLLs) Per Device
Up To Four Standard PLLs (SPLLs) Per Device
Frequency Range 1 to 420MHz
Programmable Phase / Duty Cycle (22.5 degree steps)
Programmable Dividers
Internal and External Feedback
PLLs Filter Jitter
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
sysCLOCK DLL
sysCLOCK DLL
Feedback
(DLL Internal,
clock net or
external pin)
Output Mux
(From pin
or routing)
Phase
Comparator
Clock In
ALU
50%
Duty
Cycle
2/4
50%
Duty
Cycle
Clock
Out
Clock
Out
Lock
Clock In
(From pin
or routing)
– Calibrated delay
– Clock injection
removal
– Clock match
 100 to 500MHz
Operation
Delay
Line
Delay
Line
 Flexible DLL
Provides 3 Modes:
Matched Delay
Clock
Out
 DLLs Maintain
Clock and Data
Alignments
Note: Simplified diagram
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
On-Chip Oscillator
OSCD
OSC
 On-Chip Oscillator
Provides Low Cost Clock
– Ideal for non-timing-critical
state machines
 Drives Internal Routing
Oscillator Primitive
COMPONENT OSCD
-- synthesis translate_off
– Can be routed off chip
GENERIC
(NOM_FREQ: string := 2.5);
 Nominal Frequency Can
Be Set 2.5 to 130Mhz
-- synthesis translate_on
 Easily Implemented With
ispLEVER Design Tools
END COMPONENT;
PORT (OSC:OUT std_logic);
attribute NOM_FREQ : string;
attribute NOM_FREQ of OSCins0: signal
is “2.5”;
Example VHDL Usage
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
High-Performance sysDSP Block
sysDSP Block
 Programmable Multiplier
– One 36x36 or four 18x18 or
9x9
X
eight
 Programmable Addition,
Subtraction & Accumulate
+-
X
 Programmable Pipelining
+
– Input / Intermediate / Output
 325MHz Performance
X
+-
X
– Provides up to 28.6 GMAC/second per
device
 Suitable For Wide Range of DSP
Functions Including
– FIR Filters, FFTs and complex arithmetic
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
Pre-Engineered Source Synchronous I/O
DDR to SDR
Conversion
 Implement High Speed
Memory Interfaces
PIO A
Tri-state
Register Block
(2 Flip/flops)
– DDR1/2
 Implement High Speed
Source Synchronous
Interfaces
– SPI4.2
– ADC/DAC
2:1 Gearbox
(Optional)
Shared With
PIO B
 Pre-Engineered I/O Logic
Support
– DDR to SDR conversion
– Gearbox logic
– DQS/Strobe alignment
PIC
Output
Register Block
(2 Flip/flops)
Input
Register Block
(5 Flip/flops)
Input
DQS/Strobe Delay and
Transition Detect*
PIO B
(Detail Not Shown)
* Selected
blocks
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
2:1 Gearbox For
Operation Up to
Breakthrough!
840Mbps
Precision
Strobe/DQS
Alignment
Bringing the Best Together
sysIO Support
sysIO Buffer Support
Standard
Chip Level Support
LVTTL, LVCMOS
Clock
Speed
166MHz
Clock
Speed
333Mbps
3.3/2.5/1.8/1.5/1.2 V
PCI*
66MHz
66MHz
SSTL 18/2/3 (I, II)
200MHz
400Mbps
HSTL 18/15 (I, II**)
200MHz
400Mbps
LVDS***
420MHz
840Mbps
Differential HSTL
200MHz
400Mbps
Differential SSTL
200MHz
400Mbps
Standard
DDR1/2 Memory
PCI
Generic Source Synch.
Speed
400Mbps
66MHz
840Mbps
* Includes PCI clamping diode. Bottom I/Os only
** HSTL II outputs only supported for 1.8-volts
*** Drivers on 50% of pairs left and right side of the device only
**** LVPECL and BLVDS can be supported through emulation
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
LVCMOS/LVTTL I/O Features
 Hotsocketing Capable
– Input leakage less than 1mA during power-up/power-down
– Power supplies can be sequenced in any order
 Programmable Slew Rate
 Programmable Drive Strength
–
–
–
–
–
4 to 20mA (3.3-volts)
4 to 20mA (2.5-volts)
4 to 16mA (1.8-volts)
4 to 8mA (1.5-volts)
2 to 6mA (1.2-volts)
 Programmable Pull-up, Pull-down, Bus-friendly
 Programmable Open Drain
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
I/O Banking Scheme
Bank 1
Bank 2
VREF2(7)
Bank 7
VCCIO7
VREF1(7)
GND
VREF2(1)
VREF1(1)
VCCIO1
GND
VREF2(0)
VREF1(0)
VCCIO0
Bank 0
 Eight General Purpose I/O
Banks Per Device
Bank 3
Bank 6
VCCIO6
VCCIO3
VREF1(3)
VREF2(3)
GND
Bank 8
GND
VREF2(4)
VREF1(4)
VCCIO4
Bank 4
GND
VREF2(5)
VREF1(5)
Bank 5
VCCIO5
VREF2(2)
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
VCCIO8
GND
 Output Standard Support
Dependent on VCCIO
 Referenced Inputs
Dependent on VREF
 LVCMOS Inputs
– 12, 25 & 33 independent of
VCCIO
– 15 & 18 dependent on VCCIO
 Multiple Compatible I/O
Standards In A Bank
GND
VREF2(6)
VREF1(2)
GND
GND
VREF1(6)
VCCIO2
– Configuration pins in
separate bank
Breakthrough!
Bringing the Best Together
Soft Error Detect (SED) Logic
 LatticeECP2 Devices Contain
Hard SED Logic
– Not available in Spartan/Cyclone
LatticeECP2
 Checks Configuration Bits In
Background
– Compares to CRC
– Ignores EBR and distributed
memory
Configuration
Bits
 In Case of Error Optionally:
– Generates an error flag
– Background reconfigures logic
– Initiates a full reconfiguration
 Target This Feature for High
Reliability Applications
Configuration
Logic
Hard SED
Logic
– SED is a “non-issue” for most
applications
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
Encryption
LatticeECP2
Configuration
Memory
128-bit AES
Encrypted
Bitstream
Decrypted Data
Configures FPGA
Decryption
Engine
128-bit Key
128-bit Key In OTP
Non-Volatile
Memory
 Design Security Increasingly Important
– Overbuilding, reverse engineering and cloning all too common
 Encrypt Bitstreams With 128-bit AES Using ispVM
 On-Chip OTP 128-bit Decryption Key Storage
– Choose your own unique key
 On-Chip 128-bit AES Decryption Engine
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
Dual Boot Mode
SPI Configuration
Memory
Sector 0
Sector 1
Golden (A)
Configuration
Active (B)
Configuration
LatticeECP2
Read Data
Control
LatticeECP2 Loads Active
Configuration (B) at Power
Up. If This Fails
Configuration A is Used
 Store Active and Backup (Golden) Configurations In
SPI Configuration Memory
 LatticeECP2 Will Automatically Use Golden
Configuration If Active Configuration is Invalid
 Increase System Reliability When Configurations are
Field Updated
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
TransFR I/O For Live Field Updates
Step 1
Load New Config. To
Configuration Memory
Step 2
Lock The I/Os In
The Desired State
Step 3
Apply New
Configuration
Step 4
FPGA Regains
Control of I/O
Config. Memory
Config. Memory
Config. Memory
Config. Memory
(Config. 2)
(Config. 2)
(Config. 2)
(Config. 2)
LatticeECP2
LatticeECP2
LatticeECP2
LatticeECP2
Config. 1
Config. 1
Config.2
Config.2


Field Update FPGAs and Maintain High System Uptime
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
Support Designs Over 300MHz
Element
Performance (MHz)
PFU
375MHz*
sysCLOCK PLL
Input Range
1 – 420MHz
Global Clock
500MHz
sysMEM EBR
350MHz
sysDSP Block
325MHz
sysIO Buffer
400Mbps (DDR1/2 memory)
840Mbps (Generic Source Synch.)
* Simple functions (For example 16-bit decoder, 16-bit counter)
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
LatticeECP2 Family
Device
ECP2 6
ECP2 12
ECP2 20
ECP2 35
ECP2 50
ECP2 70
6.0
12
21
32
48
68
sysMEM Blocks
3
12
15
18
21
56
sysMEM (Kbits)
55
221
276
331
387
1,032
Distributed RAM (Kbits)
12
24
42
65
96
136
# 18x18 Multipliers
12
24
28
32
72
88
PLLs/DLLs
2/2
2/2
2/2
2/2
4/2
6/2
95
95
LUTs (K)
Package & IO Combinations
144-pin TQFP (20x20mm)
208-pin PQFP (28x28mm)
256-ball fpBGA (17x17mm)
192
484-ball fpBGA (23x23mm)
127
127
192
192
297
332
332
339
363
452
500
672-ball fpBGA (27x27mm)
900-ball fpBGA (31x31mm)
Samples
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
500
628
Q4
Q2
Q3
Breakthrough!
Q3
Q1
Q4
Bringing the Best Together
LatticeECP2M Family
Device
ECP2M 20
ECP2M 35
ECP2M 50
ECP2M 70
ECP2M 100
LUTs (K)
19
34
48
67
95
sysMEM Blocks
54
98
201
222
264
sysMEM (Kbits)
995
1,806
3,705
4,092
4,866
Distributed RAM (Kbits)
41
71
101
145
202
# 18x18 Multipliers
24
32
88
96
168
PLLs/DLLs
8/2
8/2
8/2
8/2
8/2
301
287
402
387
449
457
Package & IO Combinations
256-ball fpBGA (17x17mm)
163
484-ball fpBGA (23x23mm)
301
672-ball fpBGA (27x27mm)
900-ball fpBGA (31x31mm)
455
1156-ball fpBGA (31x31mm)
Samples
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
601
TBD
Q2
Breakthrough!
TBD
TBD
TBD
Bringing the Best Together
ECP2 Timeline
 Family Publicly Announced, Collateral
Available Now
 Limited ECP2-50 Prototypes Available Now
– Broad sample availability during Q2
– Whole family planned for production by the end of 2006
 Pricing As Low As $0.50 Per KLUT
– Lowest speed grade, highest volume
 ECP2-50 Supported in ispLEVER 5.1 SP2
 Extensive IP Support Planned For 2006
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
Advanced Configuration Support
 Flexible Configuration Options
– Low cost SPI boot memory,
microprocessor, JTAG
 Encrypted Bit Stream
– On-chip 128-bit AES decryption
– Encryption key securely stored on-chip
 Automatic SPI Dual Boot
– Allows recovery if power or communication
fails during field update
 Simple Field Configuration
– Define I/O state during field configuration
– Reconfigure FPGA while system operates
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together
ECP2 Compared to ECP
Feature
Logic
Clocks
PLLs
DLLs
Memory
ECP
8 LUTs/PFU
8 Registers/PFU
25% Dist. Memory
4 Primary
4 Secondary
2–4
25MHz – 420MHz
0
9Kb EBRs
I/O
sysIO Buffer
DDR Mux
DQS Alignment
Config.
SPI PROM
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
ECP2
8 LUTs/PFU
6 Registers/PFU
12.5% Dist. Memory
8 Primary
8 Regional
2 Edge/side
2–6
1MHz – 420MHz
2
18Kb EBRs
Impact
Lower Cost
sysIO Buffer (inc DDR2)
DDR Mux + Gearbox
DQS Alignment
Generic DDR
SPI PROM
Dual boot
Encryption
Higher Speed I/O
Breakthrough!
Higher Speed
Clocking
Flexibility
Flexibility
Lower Cost
Improved
Configuration
Bringing the Best Together
LatticeECP2 Competitive Comparison
Feature
Spartan3E
Cyclone II
LatticeECP2
DSP
Basic 18x18
Multiplier
Basic 18x18
Multiplier
Full-Featured
sysDSP Block
DDR /
Source
Synch
333Mbps DDR2
DDR Registers
333Mbps DDR2
DQS Alignment
Config.
SPI PROM
400Mbps DDR2
DQS Alignment
DDR Registers
Clock Transfer
Gearbox Logic
Proprietary PROM SPI PROM
Exceptional
Performance
Encryption
Dual-boot
Distributed
Memory
Logic
50% - Inefficient
None
TransFR
Optimized 12.5%
LUT4 + Register
LUT 4 + Register
Optimized
75% LUT4+FF
Uncommon
Value
25% LUT
Copyright © Lattice Semiconductor 2006
S1 Low-Cost FPGAs - February/March, 2006 – Page
Breakthrough!
Bringing the Best Together