LHO 12 Interfacing
1
A simple bus
• Wires:
– Uni-directional or bi-directional
– One line may represent multiple wires
• Bus
rd'/wr
Processor
– Set of wires with a single function
• Address bus, data bus
Memory
enable
addr[0-11]
data[0-7]
– Or, entire collection of wires
• Address, data and control
• Associated protocol: rules for
communication
bus
bus structure
2
Timing Diagrams
• Most common method for describing a
communication protocol
• Time proceeds to the right on x-axis
• Control signal: low or high
– May be active low (e.g., go’, /go, or
go_L)
– Use terms assert (active) and deassert
– Asserting go’ means go=0
• Data signal: not valid or valid
• Protocol may have subprotocols
– Called bus cycle, e.g., read and write
– Each may be several clock cycles
• Read example
– rd’/wr set low,address placed on addr
for at least tsetup time before enable
asserted, enable triggers memory to
place data on data wires by time tread
rd'/wr
enable
addr
data
tsetup
tread
read protocol
rd'/wr
enable
addr
data
tsetup
twrite
write protocol
3
Microprocessor interfacing: I/O
addressing
• A microprocessor communicates with other
devices using some of its pins
– Port-based I/O (parallel I/O)
• Processor has one or more N-bit ports
• Processor’s software reads and writes a port just like a register
• E.g., P0 = 0xFF; v = P1.2; -- P0 and P1 are 8-bit ports
– Bus-based I/O
• Processor has address, data and control ports that form a single
bus
• Communication protocol is built into the processor
• A single instruction carries out the read or write protocol on the
bus
4
Types of bus-based I/O:
memory-mapped I/O and
standard I/O
• Processor talks to both memory and peripherals using
same bus – two ways to talk to peripherals
– Memory-mapped I/O
• Peripheral registers occupy addresses in same address space as memory
• e.g., Bus has 16-bit address
– lower 32K addresses may correspond to memory
– upper 32k addresses may correspond to peripherals
– Standard I/O (I/O-mapped I/O)
• Additional pin (M/IO) on bus indicates whether a memory or peripheral
access
• e.g., Bus has 16-bit address
– all 64K addresses correspond to memory when M/IO set to 0
– all 64K addresses correspond to peripherals when M/IO set to 1
5
Memory-mapped I/O vs.
Standard I/O
• Memory-mapped I/O
– Requires no special instructions
• Assembly instructions involving memory like MOV and ADD
work with peripherals as well
• Standard I/O requires special instructions (e.g., IN, OUT) to
move data between peripheral registers and memory
• Standard I/O
– No loss of memory addresses to peripherals
– Simpler address decoding logic in peripherals possible
• When number of peripherals much smaller than address space
then high-order address bits can be ignored
– smaller and/or faster comparators
6
Consider a simple processor.
I call it the simple processing unit
(SPU).
7
The memory read and I/O read timing
for a simple processor is shown below.
8
The Memory write and I/O write
timing for a simple processor is shown
below.
9
I/O Ports
10
11
Some Real processors
No separate I/O address
space.
MRD  VMA  R / W
MWR  VMA  R / W
12
No separate I/O address
space.
MRD  R / W
MWR  R / W
13
MRD  RD  IO / M  RD  IO / M
MWR  WR  IO / M  WR  IO / M
IORD  RD  IO / M  RD  IO / M
IOWR  WR  IO / M  WR  IO / M
14
MRD  RD  MREQ  RD  MREQ
IORD  RD  IOREQ
MWR  WR  MREQ  WR  MREQ
IOWR  WR  IOREQ
15
RD
WR
MRD  RD  M / IO  RD  M / IO
MWR  WR  IO / M  WR  M / IO
IORD  RD  M / IO  RD  M / IO
IOWR  WR  M / IO  WR  M / IO
16
U4
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
29
30
The 8051
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
PSEN
U1
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
X1
X2
ALE/PROG
EA/VPP
RST
VCC
8751
39
38
37
36
35
34
33
32
39
38
37
36
35
34
33
32
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
19
18
19
18
31
9
31
9
40
40
Atmel AVR
PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
PB0/T0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
XTAL1
XTAL2
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4
PD5/OC1A
PD6/WR
PD7/RD
ALE
OC1B
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
30
29
ICP
RST
VCC
AT90S8515
17
18
8051
19
20
21
A basic memory protocol
P0
P2
Q
Adr. 7..0
Data
P0
Q
D
/CS
Adr. 15…8
ALE
G
Adr. 7…0
/RD
A<0...15>
/OE
/WE
74373
8
ALE
D<0...7>
P2
/WR
/RD
/PSEN
8051
CS2
/CS1
HM6264
/CS
D<0...7>
A<0...14>
/OE
27C256
• Interfacing an 8051 to external memory
– Ports P0 and P2 support port-based I/O when 8051
internal memory being used
– Those ports serve as data/address buses when external
memory is being used
– 16-bit address and 8-bit data are time multiplexed; low
8-bits of address must therefore be latched with aid of
22
ALE signal
8051 instructions for addressing external code and data
memory.
23
D<0...7>
Q
D
P0
A<0...15>
/CS
74373
/OE
G
ALE
HM6264
/WE
CS2
8051
P2
/CS1
8
/WR
/CS
/RD
/PSE
N
D<0...7>
27C256
Ex: XM(0)  XM(1)
MOV
DPTR,#0
MOVX A,@DPTR
INC
DPTR
MOV
R7,A
MOVX A,@DPTR
XCH
A,R7
MOVX @DPTR,A
DEC
DPTR
XCH
A,R7
MOVX @DPTR,A
A<0...14>
/OE
Ex: XM(0)  XM(1)
CLR
P2
CLR
R0
MOV
R1,#1
MOVX A,@R0
MOV
R7,A
MOVX A,@R1
MOVX @R0,A
MOV
A,R7
MOVX @R1,A
24
5 Vd
5 Va
C10
AIN
R5
200
U8
.1uF
1
1
ANAIN
Vdig
2
Vana
BNC
R4
50
R6
33.2K
2.2uF
C8
2
3
4
2.2uF
C9
5
23
25
14
GND DIG
AGND1
REF
CAP
AGND2
BY TE
CS
DGND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
BUSY
R/C
AD976/S0
28
27
U9
22
21
20
19
18
17
16
15
13
12
11
10
9
8
7
6
D0
D1
D2
D3
D4
D5
D6
D7
39
38
37
36
35
34
33
32
26
#busy
PORTF0
24
R/#C
PORTF1
1
2
3
4
5
6
7
8
19
18
31
9
40
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
X1
X2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
PSEN
ALE/PROG
EA/VPP
RST
VCC
8751
RnC
n_BUSY
BYTE
EQU P1.1
EQU P1.2
EQU P1.3
25
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
29
30
RnC
EQU P1.1
n_BUSY EQU P1.2
BYTE
EQU P1.3
CLR RnC
SETB RnC
JNB n_BUSY,$
MOV R7,P0
CPL BYTE
MOV R6,P0
26
The 8255
27
28
29
30
31
Change individual bits on Port C
32
U4
21
22
23
24
25
26
27
28
/WR
/RD
10
11
12
13
14
15
16
17
29
30
P 2.0/A 8
P 2.1/A 9
P 2.2/A 10
P 2.3/A 11
P 2.4/A 12
P 2.5/A 13
P 2.6/A 14
P 2.7/A 15
P 3.0/RX D
P 3.1/T X D
P 3.2/INT0
P 3.3/INT1
P 3.4/T 0
P 3.5/T 1
P 3.6/W R
P 3.7/RD
P SE N
P 0.0/A D0
P 0.1/A D1
P 0.2/A D2
P 0.3/A D3
P 0.4/A D4
P 0.5/A D5
P 0.6/A D6
P 0.7/A D7
P 1.0
P 1.1
P 1.2
P 1.3
P 1.4
P 1.5
P 1.6
P 1.7
X1
X2
A LE /P ROG
E A/VP P
RST
V CC
D0
D1
D2
D3
D4
D5
D6
D7
39
38
37
36
35
34
33
32
1
2
3
4
5
6
7
8
19
18
31
9
D0
D1
D2
D3
D4
D5
D6
D7
5
36
9
8
35
6
U3
D0
D1
D2
D3
D4
D5
D6
D7
A LE
3
4
7
8
13
14
17
18
11
1
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
U1
34
33
32
31
30
29
28
27
2
5
6
9
12
15
16
19
D0
D1
D2
D3
D4
D5
D6
D7
P A0
P A1
P A2
P A3
P A4
P A5
P A6
P A7
RD
WR
A0
A1
RES ET
CS
P B0
P B1
P B2
P B3
P B4
P B5
P B6
P B7
P C0
P C1
P C2
P C3
P C4
P C5
P C6
P C7
LE
OE
40
74 LS3 73
87 51
4
3
2
1
40
39
38
37
18
19
20
21
22
23
24
25
14
15
16
17
13
12
11
10
82 C55 A
D0
D1
D2
D3
D4
D5
D6
D7
U2
34
33
32
31
30
29
28
27
5
36
9
8
35
6
D0
D1
D2
D3
D4
D5
D6
D7
P A0
P A1
P A2
P A3
P A4
P A5
P A6
P A7
RD
WR
A0
A1
RES ET
CS
P B0
P B1
P B2
P B3
P B4
P B5
P B6
P B7
P C0
P C1
P C2
P C3
P C4
P C5
P C6
P C7
33
82 C55 A
4
3
2
1
40
39
38
37
18
19
20
21
22
23
24
25
14
15
16
17
13
12
11
10
RESET_8255 EQU P1.0
CTL1 EQU 111111111011B
PRTA1 EQU 111111111000B
PRTB1 EQU 111111111001B
PRTC1 EQU 111111111010B
CTL2 EQU 111111110111B
PRTA2 EQU 111111110100B
PRTB2 EQU 111111110101B
PRTC2 EQU 111111110110B
;ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #1
;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1
;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1
;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1
;ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #2
;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2
;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2
;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2
CLR RESET_8255 ;REMOVE RESET FROM 8255
;DO ADDITION C2|C1 <-- A2|A1 + B2|B1
MOV DPTR,#(CTL1 AND CTL2);POINT DPTR TO CONTROL REG OF 8255 #1 AND #2
MOV A,10010010B ;PRTA, PRTB IN, PRTC OUT
MOVX @DPTR,A
;OUTPUT TO BOTH CONTROL REGS AT SAME TIME
MOV DPTR,#PRTA1 ;SELECT PORT A OF 8255 #1
MOVX A,@DPTR
;GET PRTA1
MOV R7,A
;SAVE IT
MOV DPTR,#PRTB1 ;SELECT PORT B OF 8255 #1
MOVX A,@DPTR
;READ PORT B OF 8255 #1
ADD A,R7
;ADD PRTA1 TO PRTB1
MOV DPTR,#PRTC1 ;SELECT PORT C OF 8255 #1
MOVX @DPTR,A
;OUTPUT TO PRTC1
END
34
U4
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
/WR
/RD
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
29
30
P 2.0/A 8
P 2.1/A 9
P 2.2/A 10
P 2.3/A 11
P 2.4/A 12
P 2.5/A 13
P 2.6/A 14
P 2.7/A 15
P 3.0/RX D
P 3.1/T X D
P 3.2/INT0
P 3.3/INT1
P 3.4/T 0
P 3.5/T 1
P 3.6/W R
P 3.7/RD
P SE N
P 0.0/A D0
P 0.1/A D1
P 0.2/A D2
P 0.3/A D3
P 0.4/A D4
P 0.5/A D5
P 0.6/A D6
P 0.7/A D7
P 1.0
P 1.1
P 1.2
P 1.3
P 1.4
P 1.5
P 1.6
P 1.7
X1
X2
A LE /P ROG
E A/VP P
RST
V CC
D0
D1
D2
D3
D4
D5
D6
D7
39
38
37
36
35
34
33
32
1
2
3
4
5
6
7
8
19
18
D0
D1
D2
D3
D4
D5
D6
D7
U1
34
33
32
31
30
29
28
27
5
36
9
8
35
6
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
D0
D1
D2
D3
D4
D5
D6
D7
P A0
P A1
P A2
P A3
P A4
P A5
P A6
P A7
RD
WR
A0
A1
RES ET
CS
P B0
P B1
P B2
P B3
P B4
P B5
P B6
P B7
P C0
P C1
P C2
P C3
P C4
P C5
P C6
P C7
31
9
40
87 51
4
3
2
1
40
39
38
37
18
19
20
21
22
23
24
25
14
15
16
17
13
12
11
10
82 C55 A
D0
D1
D2
D3
D4
D5
D6
D7
U2
34
33
32
31
30
29
28
27
5
36
9
8
35
6
D0
D1
D2
D3
D4
D5
D6
D7
P A0
P A1
P A2
P A3
P A4
P A5
P A6
P A7
RD
WR
A0
A1
RES ET
CS
P B0
P B1
P B2
P B3
P B4
P B5
P B6
P B7
P C0
P C1
P C2
P C3
P C4
P C5
P C6
P C7
35
82 C55 A
4
3
2
1
40
39
38
37
18
19
20
21
22
23
24
25
14
15
16
17
13
12
11
10
U1
39
38
37
36
35
34
33
32
1
2
3
4
5
6
7
8
19
18
31
9
40
PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
PB0/T0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
XTAL1
XTAL2
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4
PD5/OC1A
PD6/WR
PD7/RD
ALE
OC1B
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
30
29
ICP
RST
VCC
AT90S8515
36
37
U2
D0
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
11
1
U1
D0
D1
D2
D3
D4
D5
D6
D7
39
38
37
36
35
34
33
32
1
2
3
4
5
6
7
8
Y1
8 MHz
C1
22 pf
19
18
C2
22 pf
31
9
40
PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
PB0/T0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
XTAL1
XTAL2
8D
7D
6D
5D
4D
3D
2D
1D
C
OC
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
74LS373
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4
PD5/OC1A
PD6/WR
PD7/RD
ALE
OC1B
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
A8
A9
A10
A11
A12
A13
A14
A15
19
16
15
12
9
6
5
2
A0
A1
A2
A3
A4
A5
A6
A7
U4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
n_RD
n_WR
24
31
22
32
n_WR
n_RD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
OE
WE
CE
VCC
VCC
AT49BV001N
30
29
ICP
RST
VCC
VCC
AT90S8515
Figure 1. AT90S8515 with expanded memory. What should we do with A16? Answer: connect it to an unused port pin.
Question: How could we map the entire 128K bytes of memory to the top 32 Kbytes of the AVR address space.
Answer: Connect AVR A15 to /CE on U4. Now the memory is selected only when the AVR addresses the top have of the memory address space
where A15 = 1. Connect A15 and A16 of U4 to unused AVR port pins. By changing these port pin, any of the four 32 K byte pages of U4 memory
can be switched in and out of the AVR address space.
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