2012 EU ALSA Training
P8P67 Series
Confidential
Agenda
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P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
Agenda
•
•
•
•
•
•
•
•
•
P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
P67 Platform
• Sandy Bridge CPU Architecture
–
–
–
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–
–
LGA 1155
Integrated Memory Controller (IMC)
Integrated Graphics support (P67 chipset)
Dual-channel DDR3
Intel Turbo Boost 2.0 Technology
Intel Hyper-Threading Technology (up to 4
cores, 8 threads)
– PCIE Gen2 for 1x16 & 2x8 option
• Intel P67/H67 Chipset Features
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–
–
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–
2 ports SATA 6Gb/s Support
4 ports SATA 3Gb/s Support
RAID 0, 1, 5, 10 Support
14 ports USB2.0
8 Lane PCIE gen2 for x4 & x2 & x1
No PCI support
Agenda
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•
•
•
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P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
New Feature
DIGI+ VRM
DIGI+ VRM Load-line Calibration
Change Load-line slope
Regular, Medium, High, Ultra High, Extreme
DIGI + Current Capability
Increase over current protect point
100%, 110%, 120%, 130%, 140%
DIGI + VRM Frequency
Change switch frequency
Auto: SSC on or off, Fix: 300MHz~500MHz with 10MHz/step
DIGI+ VRM Phase Control
VCORE phase number switch by different setting
Standard: by CPU P-state, Optimize: load best profile, Extreme: full
phase,
Manual: user decide interval value
New Feature
EFI BIOS
• Graphical Interface & OS-like Operation
• Mouse-controlled Support
More Settings
Display System
Information
System
Performance
Settings
Boot Priority
New Feature
ASUS BT GO!
Agenda
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•
•
•
•
•
•
•
•
P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
P8P67 Deluxe Architecture
P8H67-M LE Architecture
P8H61-M LX Architecture
P8P67 Series SPEC Table
P8P67 Deluxe
CPU Socket
P8P67 EVO
P8P67 PRO
P8P67
LGA1155 socket for 2nd Generation Intel® Core™ i7/Core™ i5/Core™ i3 Processors
Chipset
Intel® P67 Express Chipset
Memory
DDR3 2133(O.C.)/1866(O.C.)/1600/1333MHz
Power
Design
PCIex16
Slots
Multi-GPU
Gbit LAN
DIGI+ VRM
DIGI+ VRM
DIGI+ VRM
DIGI+ VRM
4+1
3
3
3
2
2
CrossFireX/SLI
CrossFireX/SLI
CrossFireX/SLI
CrossFireX
CrossFireX
2 (Intel/Realtek)
2 (Intel/Realtek)
1 (Intel)
1
1
16+2
Bluetooth
Audio
Storage
USB
1394a
P8P67 LE
12+2
12+2
12+2
Bluetooth v2.1 + EDR
8-ch HD, DTS
8-ch HD, DTS
8-ch HD, DTS
4* SATA 6Gb/s
4* SATA 3Gb/s
2* eSATA (1*PWR eSATA)
-8-ch HD, DTS
8-ch HD
4* SATA 6Gb/s
4* SATA 3Gb/s
1* eSATA (by
bracket)
1* Ultra DMA
3* SATA 6Gb/s
4* SATA 3Gb/s
1* eSATA
4* USB 3.0 (2 ports at back panel, 2 ports at mid-board)
12* USB 2.0
2 ports (one at mid-board, one at back panel)
2* USB 3.0 (back)
Agenda
•
•
•
•
•
•
•
•
•
P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
P67 Chipset Introduction
P8P67 Deluxe Clock Distribution
P8P67 Deluxe Clock Distribution
P8P67 Deluxe – PCI Buffer
(6G SATA)
+1V_CG
+2.5V_DA
S_PLTRST#
(PCI)
(PESATA)
Agenda
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•
•
•
•
•
•
•
•
P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
P8P67 Deluxe Critical Power On
Ex: P8P67 PRO
P8H61-M LX Critical Power On
P8P67 Deluxe Critical Power On
 CPU:
 VCORE
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Processor core power with VRM 12 design
Default voltage base on SVID
Offset mode: ±0.005~ ±0.635V, 0.005V/step
Manual mode: 0.8~1.99V, 0.005V/step
 VCCIO
• Processor I/O supply voltage for other than DDR3 (PCIE, DMI, Processor hot..)
• Default 1.05V for Sandy Bridge processor (1.00V for future CPU)
• OV range: 0.8V~1.7V, 0.00625V/step
 VCCSA
• Voltage for the system agent (memory controller)
• Default 0.925V for Sandy Bridge processor (0.85V for future CPU)
• OV range: 0.8V~1.7V, 0.00625V/step
LGA 1155 Socket
P8P67 Deluxe Critical Power On
 CPU:

1.5VDUAL
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•
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•

1.8SFR
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•
•

Processor I/O supply voltage for DDR3
DRAM Device voltage
Default value is 1.5V
OV range: 1.2V~2.2V, 0.00625V/step
PLL supply voltage
Default value is 1.8V
OV range: 1.2V~2.2V, 0.00625V/step
VTTDDR
•
•
•
DDR3 termination voltage
Default value is 0.75V
OV range: None
LGA 1155 Socket
P8P67 Deluxe Critical Power On
• PCH:
– 1.05PCH:
•
•
•
•
Core power for Cougar Point
SATA, USB, DMI PLL power source
Default value is 1.05V
OV range: 0.8V~1.7V, 0.01V/step
– 3VSB:
• Power for suspend I/O buffers
• Shut off only in G3 state (unless EuP S5)
• Default value is 3.33V
– 3V:
• Power for core I/O buffers
• Shut off in all state unless S0
• Default value is 3.33V
f
P8P67 Deluxe Critical Power On
– VCCIO:
• Power to drive the processor interface signals
• Default value is 1.05V (Base on CPU type)
• OV range: 0.8V~1.7V, 0.00625V/step
– 1.8SFR
• PLL supply voltage
• Default value is 1.8V
• OV range: 1.2V~2.2V, 0.00625V/step
f
P8P67 Deluxe Critical Power On
• OV Method:
– From EC SMBUS:
• VCORE: Set SVID by EC SMBUS
– From EC DAC circuit:
•
•
•
•
1.8SFR: Set reference voltage by EC DAC output
VCCIO: Set reference voltage by EC DAC output
VCCSA: Set reference voltage by EC DAC output
1.5VDUAL: Set reference voltage by EC DAC output
– From 3933:
• 1.05PCH: Sink or source current to adjust feedback voltage
P8P67 Deluxe Critical Power On
• HW Monitor
– From EC:
•
•
•
•
1.05PCH: Detect by EC AD input
VCCIO: Detect by EC AD input
1.8SFR: Detect by EC AD input
1.5VDUAL: Detect by EC AD input
– From SIO:
•
•
•
•
VCORE: Detect by SIO CPUVCORE input pin directly
+3V: Detect by SIO VCC input pin
+5V: Divide to 1V and detect by VIN1 input pin
+12V: Divide to 1V and detect by VIN0 input pin
Agenda
•
•
•
•
•
•
•
•
•
P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
P8 Power Sequence
P8P67 Deluxe Power Sequence
1. Battery:
Battery
a. RTCRST#
b. S_RTCRST#
Signal
2. AC Power:
a. 5VSB_ATX, 3VSB_ATX
b. 5VSB, 3VSB_ADV, 3VSB
3. RSMRST
SIO
4. REF Voltage:
a. P_1.5VDUAL_REF_10
b. P_+VCCSA_REF_10
c. P_+VCCIO_REF_10
d. P_1.8SFR_REF_10
RSMRST
3.2VCC
EC
O2_ECRST#
P_1.5VDUAL
P_+VCCSA
P_+VCCIO
P_1.8SFR
P8P67
Deluxe
PowerPower
Sequence
P8P67
Deluxe
Sequence
5. Power On:
a. O_PWRBTN#IN
b. O_PWRBTN#
SIO
PANEL
6. SLP_S3&S4:
SIO
7. PS_ON:
SIO
8. 12V, 5V, 3V
9. ATX_PWRGD
10. VCCIO, 1.5V_DUAL, VTTDDR, 1.8SFER, 1.1V, 1.05PCH
Power
Supply
P8P67
Deluxe
- Power
Sequence
P8P67
Deluxe
Power
Sequence
11. H_VCCIOPWRGD
1156
CPU
12. S_DRAMPWRGD
13. All Clock
14. VCORE (initial is 1V), VCCSA
15. P_VCORE_VRRDY_6
16. VRMPWRGD#
17. SIO_PWROK
18. O_PWROK
MB Logic
Circuit
SIO
P8P67
Deluxe
- Power
Sequence
P8P67
Deluxe
Power
Sequence
19. H_CPUPWRGD
20. H_VIDALERT#, H_VIDCLK, H_VIDDATA
21. S_SPLRST
22. O_PCIRST#_PCIEX16_1&2&3
23. H_CPURST#
24. VAUX
1156
CPU
1156
CPU
Agenda
•
•
•
•
•
•
•
•
•
P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
P67 Chipset Introduction
P67 Chipset Introduction
Power Interface:
RTC, Power Mgmt, Misc Signals, Processor Interface
Communication Interface/ Main Signals:
SPI, Direct Media Interface, LPC Interface, SMBus Interface,
Interrupt Interface, Clock
Function Interface:
PCI, USB, Serial ATA, Audio, PCI Express Interface, FAN Control
P67 Chipset Power/ RTC Interface (1)
1. RTC:
S_ICH_RTCX1
S_ICH_RTCX2
input clock (the real-time clock)
Connect with a 32.768 Crystal & 3V Battery
2. Processor Interface:
H_THERMTRIP
Thermal Trip: When low, this signal indicates that a thermal trip
from the processor occurred, and the Cougar Point will immediately
transition to a S5 state
H_CPUPWRGD
PCH send signal for processor and processor will give the real VID
to produce real VCORE for processor
3. Misc Signal:
S_INTVRMEN/ S_DSWVRMEN
This signal enables the internal 1.05V regulators. It must be always pulled-up to VccRTC.
RTCRST#/ SRTCRST#
This signal resets the manageability register bits in the RTC well when the RTC
battery is removed.
INIT3_3V#
P67 Chipset Power/ RTC Interface (2)
4. Power Mgmt:
SLP_S3, SLP_S4
SLP_S3# is for power plane control. This signal
shuts off power to all non-critical systems when in
S3 (Suspend To RAM), S4 (Suspend to Disk), or S5
(Soft Off) states.
S_PDWROK
Power OK Indication for the VccDSW3_3 voltage
rail. This input is tied together with RSMRST# on
platforms that do not support Deep status.
DRAMPWROK
This signal should connect to the Processor’s
SM_DRAMPWROK pin. The PCH asserts this pin to
indicate when DRAM power is stable.
PLTRST#
Platform Reset: The Cougar Point asserts PLTRST#
to reset devices on the platform (e.g., SIO, FWH,
LAN, Processor, etc.)
PWRBTN#
P67 Chipset Power/ RTC Interface (3)
4. Power Mgmt:
O_PWROK
PWROK can be driven asynchronously. When
PWROK is negated, the cougar Point asserts
PLTRST#.
O_RING#
This signal is an input from a modem. It can be
enabled as a wake event, and this is preserved
across power failures.
RSMRST#
Resume Well Reset: This signal is used for resetting
the resume power plane logic
VRMPWRGD
SYS_PWROK is used to inform the Cougar Point
that power is stable to some other system
component(s) and the system is ready to start the
exit from reset.
O_RSTCON
S_SUSACK#
S_SUSWARN#
S_SLPSUS#
Communication Interface/ Main Signals (1)
1. DMI:
H_DMI_TXP[3:0]
H_DMI_TXN[3:0]
H_DMI_RXP[3:0]
H_DMI_RXN[3:0]
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and Cougar
Point chipset.
H_DMI_COMP
Impedance Compensation and it connects with 1.05V
2. LPC:
F_LAD#[3:0]
F_FRAME#
F_DRQ0#
3. Interrupt Interface:
F_SERIRQ
Communication Interface/ Main Signals (2)
4.
SPI:
SPI_CS#
SPI_MISO
SPI Master IN Slave OUT: Data input pin for Cougar
Point.
SPI_MOSI
SPI Master OUT Slave IN: Data output pin for
Cougar Point.
SPI_CLK
5.
SMBus:
S_SMBDATA_PCI / S_SMBCLK_PCI
6.
Clock:
P67 Chipset Function Interface & Others
1.
2.
3.
4.
SATA:
USB:
Audio:
Fan Speed Control
5.
PCI Express Interface
P67 Chipset support 8 PCIE
USB3.0
X1
USB3.0
X1
LAN
X1
PCIE Buffer
X1
PCIEX16
X4
P67 Chipset Power
+1.05PCH
+BAT_3V
+1.05PCH
+3VSB
+1.8SFR
+1.05PCH
+1.05PCH
+3V
P67 Chipset Power
+5V
+5VSB
+1.05PCH
+3V
+1.05ME
+VCCIO
+VCCIO
+VCCIO
3VSB_SB
P67 Chipset PIN Strap
Pin Straps:
When booting on, some pins CPU/PCH/SIO will detect high/ low status.
According these status, CPU/PCH/SIO will set different response.
If strap is abnormal, it would cause CPU/PCH do the wrong action=>can’t boot up
BIOS Straps:
EX: P8P67 Deluxe
Bit11:
K_GNT_#1_PCH
Bit10:
N14465937
Bit11
Bit10
Boot BIOS
Destination
0
1
Reserved
1
0
PCI
1
SPI
0
LPC
1
0
+VCCIO
P8P67 Deluxe – EC Introduce
Power PIN:
PIN6, 18, 54, 61: +O2_3.2V_AVCC
PIN35: +3VSB
Clock PIN:
PIN9, (C_PCI_EC)
PIN58, 59 (O2_XCLI) 32.769 Crystal
Reset PIN:
PIN22 (O2_ECRST)
PIN10 (S_PLTRST#)
P8P67 Deluxe – EC Introduce
SPI Flash : PIN56, 67, 62, 64
MISO 56 (read control signal)
MOSI 57 (write control signal)
SPICLK 62 (clock output)
SPICS# 64 (chip select signal)
SMB Bus : PIN45, 46
SCL0 45 (SMBUS clock)
SDA0 46 (SMBUS data)
Low Pin Count PIN:
P8P67 Deluxe – EC Introduce
P8P67 Deluxe – EC Introduce
Digital-to-Analog Converter : PIN36, 38, 39, 40
(8bit D/A converter output)
P_1.5VDUAL_REF_10
P_VCCA_REF_10
P_VCCIO_REF_10
P_1.8FSR_REF_10
Others Signals:
PIN24: O2_TP_TEST (High: normal mode using 32KHz oscillator)
PIN29: O2_DAC_SWITCH
PIN51: J_SILENT#
PIN13: SMB_SWITCH
PIN63: H_VCCIO_SEL#
(Let EC to choose this PIN to be low or high)
If VCCIO_SEL is low, VCCIO must be 1V;
If VCCIO_SEL is high, VCCIO must be 1.05V.
Agenda
• Repair Notice & Trouble Shooting Guide
–
–
–
–
–
–
RTC/Battery
Power on
VCORE
Display/VGA/DVI
Memory
LAN/USB/other function
• Experience Sharing
P8P67 Deluxe Power – RTC/CMOS/Battery
Repair Process & Analysis:
1. Visually Inspect:
2. CLR_COMS:
Check CMOS button is normal or not
3. Voltage:
3V(+BAT_3V>2.4V)
4. Frequency:
(1)Check 32.768 (SX1), voltage and CLK of 2 pins
need to be normal
(2)If SX1 has no power and CLK, check PCH
BAT/VSB voltage and related circuit is normal
first.
5. Others signal:
(1)Measure 1Kohm+BAT_R(SR73)
(2)Measure the leakage current at SR100
(1uA~10uA)
(3) S_SRTCRST#
(4)S_RSTRST#
P8P67 Deluxe Power – Can’t Power On (1)
Repair Process & Analysis:
1. Visually Inspect:
2. Press power switch:
(1)Check PWRBTN can be pulled low
(2)Check PSON# can be pulled low
3. Voltage:
(1)BAT
(2)5VSB_ATX, 3VSB_ATX
(3)5VSB, 3VSB_ADV, 3VSB
If BIOS enable EuP, only ATX exist at S5 state
4. Signals:
(1)SIO:
a. RSMRST#
b. O_PWRBTN#
c. O_PWRBTN#IN _R
d. PSON#
P8P67 Deluxe Power – Can’t Power On (2)
Repair Process & Analysis:
(2)EC:
a. O_PWRBTN#IN
b. P_1.5VDUAL_REF_10 (About 1.5V)
c. P_VCCA_REF_10
(About 0.7V)
d. P_VCCIO_REF_10
(About 0.7V)
e. P_1.8FSR_REF_10
(About 1.8V)
f. O2_ECRST
g. O2_DAC_SWITCH
(3)PCH:
a. S_SLPS3#
b. S_SLPS4#
c. DSWVRMEN
g. INTVRMEN
(above 2V)
(above 2V)
(4)Others:
a. 32.768 Crystal
b. H_SKTOCC#
When installing CPU, this pin should be low.
Normal is under 0.8V.
P8P67 Deluxe Power – Can’t Power On (3)
Repair Process & Analysis:
(4)Others:
a. 32.768 Crystal
b. H_SKTOCC#
When installing CPU, this pin should be low.
Normal is under 0.8V.
Status
Level
(H_SKTOCC#)
Level
(O_CPU_REMOVE#)
Without CPU
High
High
Installing
CPU
Low
Low
P8P67 Deluxe Power – DEEPS5 to S5 (1)
• Some high end MB will be set S5 status at default.
• Other MB are set in DeepS5 status to save the power energy
SIO
SIO
Power
S5 with EuP off S5 with EuP on (DeepS5)
5VSB_ATX, 3VSB_ATX
O
O
+5VSB
O
X
+3VSB_ADV
O
X
+3VSB
O
X
+5V_DUAL_USBKB
O
X
+3V_DUAL_LAN
O
X
P8P67 Deluxe Power – DEEPS5 to S5 (2)
5VSB
3. Low level
1.Pull low
2. Low level
(0.42V)
P8P67 Deluxe Power – 5VSB to 3VSB
• 5VSB through the circuit to provide voltage for +3VSB_ADV
• +3VSB_ADV through the circuit to transfer power for 3VSB
Low
level
P8P67 Deluxe Power – USBKB Voltage
1
2
3
4
P8P67 Deluxe – VCORE (1)
+12V
Before P8 VCORE Design
BOOT
VCC
UGATE
Drive PHASE
PWM
FB Circuit
LGATE
+5V
+12V
+5V
+Vcore
BOOT
VFB VCC
COMP
VCC
1K
PWM1
VSEN
10K
VIDn
PWM2
PGOOD
…..
CPU
VCORE_EN
Drive PHASE
PWM
LGATE
Main
Control
VID2
VID1
VID0
VCORE
UGATE
VID
PWM3
.
.
.
.
ISEN1
ISEN2
FS
EX: 0 0 1 1 0 1 1
+12V
ISEN3
.
.
.
BOOT
GND
VCC
VCC
PWM
UGATE
Drive PHASE
LGATE
PWM Control
P8P67 Deluxe – VCORE (2)
4
2
Low
POQ1014 can’t
be conducted
1
3
X
P8P67 Deluxe – VCORE (3)
+12V
P8 VCORE Design
BOOT
VCC
UGATE
Drive PHASE
PWM
FB Circuit
LGATE
+12V
+5V
+Vcore
BOOT
VFB VCC
COMP
PWM1
VSEN
VCORE_EN
PWM2
PGOOD
CPU
H_VIDALERT#
H_VIDCLK
H_VIDDATA
VCC
Drive PHASE
PWM
LGATE
Main
Control
PWM3
.
.
.
.
ISEN1
ISEN2
+12V
ISEN3
.
.
.
FS
BOOT
GND
VCC
VCC
PWM
UGATE
Drive PHASE
LGATE
PWM Control
VCORE
UGATE
P8P67 Deluxe - VCORE (4)
4
X
2
3
Low
POQ101 can’t
be conducted
1
P8P67 Deluxe – VCCSA
2
1
Low
POQ1014 can’t
be conducted
3
X
4
P8P67 Deluxe – No VCORE (1)
Repair Process & Analysis:
1. Visually inspect:
2. VCORE MOS:
Check MOS is normal or not.
3. Voltage can’t be short:
(Check signals as below are normal)
(1) The impedance of VCORE
(2) The impedance of 12V_8PIN
(3) The impedance of 12V_8PIN & VCORE
4. VCORE IC & driver main power:
PU100 PIN4 P_VRMVCC_20 3V
PU102~109 PIN3 12V, P_VCORE_BST*_20 12V
5. Enable signal:
Measure PU100 PIN21 has 1.1V
P8P67 Deluxe - No VCORE (2)
Repair Process & Analysis:
6. VID signal:
Measure the impedance of H_VIDALERT#,
H_VIDCLK, H_VIDDATA and compare with
golden sample
7. PWM signal:
P_VCORE_PWM*_5 need to have Square wave
8. PWRGD signal:
P_VCORE_VRRDY_6 has 1.1V
P8P67 Deluxe PCIEX16 Slot
Repair Process & Analysis:
PCIEX16 SLOT1,2
1156
CPU
1. Visually inspect:
2. Voltage :
(1) 12V
(2) 3V
(3) 3VSB
PCIEX16 SLOT 3
3. CLK signal:
A13, 14 has C_PCIEX16_1, C_PCIEX16#_1
(PCH send these signal to PCIEX16)
4. Reset signal:
Check PCIEX16 Slot Pin A11
O_PCIRST#_PCIEX16_1,
SIO PIN79 send O_PCIRST#_PCIEX16_1 for PCIEX16
Check the
capacitors
Compare with P8P67 Deluxe Display
Repair Process & Analysis:
1. Visually inspect:
2. Voltage :
Main Power is GFX voltage
3. Control signal:
Check each device impedance for normal
(Power, RGB signals, …)
Control signal
4. FDI Bus Signal:
H_FDI_COMP
H_FDI_FSYNC0
H_FDI_FSYNC1
H_FDI_INT
H_FDI_LSYNC0
H_FDI_LSYNC1
Display Port,
Like: VGA, DVI,
HDMI
GFX
FDI
BUS
For P8H61, P8H67
Series chipset
P8P67 Deluxe Memory (1)
Repair Process & Analysis:
1. Visually inspect:
(1) check memory slot if it has break line or
PIN impairment (CID).
(2) check if memory’s capacitors, inductors,
resistances and other components are lost
or damaged.
(3) check if transmission line between
memory and CPU is broken.
S_SMBDATA_MAIN
1.5VDUAL
3V
VTT_DDR
S_SMBCLK_MAIN
2. BIOS setting :
3. Voltage
(1)Check 1.5VDUAL, normal is1.5V.
(2)Check +VTTDDR(PU202 PIN4) is 0.75
(3) Check DIMM_A1/A2 PIN67 D3_VREFCA_A, ,normal is 0.75V
Check DIMM_B1/B2 PIN67 D3_VREFCA_B, ,normal is 0.75V
Check DIMM_A1/A2 PIN1 D3_VREFDQ_A, normal is 0.75V
Check DIMM_B1/B2 PIN1 D3_VREFDQ_B, normal is 0.75V；
P8P67 Deluxe Memory (2)
(4)checkPIN238
(5)check each slot of PIN118 S_SMBCLK_MAIN , after d3 is 3.3V
(6)check each slot of PIN238 S_SMBDATA_MAIN , after d3 is 3.3V
(7)Check S_DRAMPWRGD signal is good (connect with 1.5VDUAL)
4. Frequency
memory clock is controlled by CPU :
D3_MA_CLK0 ~ D3_MA_CLK3 ; D3_MA_CLK#0 ~ D3_MA_CLK#3
D3_MB_CLK0 ~ D3_MB_CLK3 ; D2_MB_CLK#0 ~ D2_MB_CLK#3
5. Address, Data and Control Line
check Ad signal and control signal for good:
D3_DQ_A0~D3_DQ_A63 ; D3_DQS_A0~D3_DQS_A17 ; D3_DQS_A#0~D3_DQS_A#17
D3_DQ_B0~D3_DQ_B63 ; D3_DQS_B0~D3_DQS_B17 ; D3_DQS_B#0~D3_DQS_B#17
P8P67 Deluxe KB/MS
Repair Process & Analysis:
1. Visually inspect:
2. BIOS :
(1)UPDATE BIOS
(2) COMS
3. Voltage:
Check PS/2 Working voltage +O_KBMS_5V_F
4. Signal:
5. Reset signal:
O_KB_RST# (Form SIO)
P8P67 Deluxe Serial ATA
Repair Process & Analysis:
1. Visually inspect:
2. BIOS :
(1)UPDATE BIOS
(2) COMS
3. CLK:
Check SX2，T2X1 25MHZ
4. Signal:
Check SATA Capacitors which connecting with
T2U1/PCH is short or not (TXP,TXN,RXN,RXP )
5. T2U1
Check Power and CLK with PEX8608 BUS and
check PEX8608 working condition and
S_PLTRST# are normal
6.
PCH
Check VCCSATA_PLL_PCH, S_SATA3_RCOMP, SATA_RBIAS, SATA3_RBIAS
P8P67 Deluxe LAN (1)
P8P67 Deluxe LAN (2)
Repair Process & Analysis:
1. Visually inspect:
2. BIOS :
(1)UPDATE BIOS
(2) COMS
3. Voltage:
(1.)Check PQ885 PIN2 3V_DUAL_LAN;
(2.)Check L2R16 PIN2 +L2_EVDD(1.05V)
4. CLK:
(1.)Network card frequency 25MHz(L2X1); (2)PCI-EX1 main line frequency C_PCIE_L2#,
C_PCIE_L2 (PIN20,19)
5. reset
signal network card PIN25 S_PLTRST# is the 3V
6. Other signals
(1) If can’t recognize the network card, check the PCIEX1 BUS signal (the figure above blue
color); (2) 10/100/1000M pay attention to check the MDI signal (the figure above brown)
P8P67 Deluxe USB (1)
Repair Process & Analysis:
1. Visually inspect:
2. BIOS :
(1)UPDATE BIOS
(2) COMS
3. Voltage:
Check USB power supply fuse both sides
whether voltage is 5V (U3QF2, U3QF1)
4. Signal:
U3RXDN, U3RXDP, U3TXDN, U3TXDP,
U2DN2, the U2DP2
P8P67 Deluxe USB (2)
Repair Process & Analysis:
5. UPD720200
(1)voltages:
+3VSB_ADV,+U3_+1.05V_DVDD
(2)frequency:
24MHz crystal oscillator, C_PCIE_U3#, C_PCIE_U3
(3)PCI-EX1 main BUS:
X_U3X1_RXN, X_U3X1_RXP, X_U3X1_TXN,
X_U3X1_TXP and S_PLTRST#
Other signals:
FLASH ROM power is normal
If the starting prompt over current protects 15second to shut down, check the
USB overflow protection circuit
Agenda
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•
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P67 Platform Introduce
New Feature
P8P67, H67 and H61 Architecture
Clock Distribution
Power Flow & Critical Power P67 platform
Power Sequence
Cougar Point & EC Introduce
Repair Notice & Trouble Shooting Guide
Experience Sharing
P8P67 Deluxe
~Q &A~
~THANK YOU~