Razor: Dynamic Voltage Scaling Based on
Circuit-Level Timing Speculation
Dan Ernst, Nam Sung Kim,
Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham,
and Conrad Ziesler
Faculty Members: David Blaauw, Todd Austin, and Trevor Mudge,
The University of Michigan
Krisztián Flautner, ARM Ltd.
36th International Symposium on Microarchitecture (MICRO-36’03)
Outline






Introduction
What is Razor?
Razor error detection/correction
Experimental Evaluation
Previous Work
Conclusion
Introduction (1/2)
 The need for DVS (Dynamic Voltage
Scaling)
 Critical supply voltage
 Traditional DVS adds many margins
 Worst-case may be data-dependent and
very rare
 Process variations and other variabilities
worsen the required margins
Introduction (2/2)
 Idea
 Instead of trying to avoid ALL errors, ALLOW
some errors to happen and correct them!
 Cost of fixing errors is minimal when the
error percentage is kept under control
 Tune processor voltage based on monitoring
error rate
What is Razor?
Razor Timing Error
4
9
3
clk
MEM
Shadow Latch
clk
5
Main FF
Main FF
Razor Timing Error Detection
9
clk_del
 Second sample of logic value used
to validate earlier sample
Key design issues:
 Maintaining pipeline forward progress
 Short path impact on shadow-latch
 Meta-stable results in main flip-flop
 Recovering pipeline state after errors
 Power overhead of error detection and
correction
Hold Constraint
(~1/2 cycle)
4
2
9
8
clk
MEM
Shadow Latch
clk
5
3
Main FF
Main FF
Razor Short Path Constraint
8
clk_del
 Min. path delay > Tdelay + Thold
Meta-stability in main FF
Key design issues:
 Maintaining pipeline forward progress
 Short path impact on shadow-latch
 Meta-stable results in main flip-flop
 Recovering pipeline state after errors
 Power overhead of error detection and
correction
Centralized Razor Pipeline Error Recovery
Cycle: 1
0
6
5
4
3
2
clock
recover
recover
error
recover
MEM
error
Razor FF
error
EX
Razor FF
ID
Razor FF
PC
IF
Razor FF
inst2
inst5
inst4
inst3
inst1
inst6
WB
(reg/mem)
error
recover
 Once cycle penalty for timing failure
 Global synchronization may be
difficult for fast, complex designs
Distributed Razor Pipeline Error Recovery
Cycle: 7891234560
bubble
recover
Flush
Control
flushID
error
recover
flushID
bubble
MEM
(read-only)
error
bubble
recover
flushID
error
Stabilizer FF
error
EX
Razor FF
ID
Razor FF
PC
IF
Razor FF
inst2
Razor FF
inst5
inst2
inst1
inst6
inst8
inst7
inst4
inst3
bubble
recover
flushID
 Multiple cycle penalty for timing failure
 Scalable design since all recovery
communication is local
 Builds on existing branch / data speculation
recovery framework
WB
(reg/mem)
Error Rate Studies – Empirical Results
100.0000000%
10.0000000%
1.0000000%
0.1000000%
0.0100000%
35% energy savings with 1.3% error
22% saving
random
0.0010000%
0.0001000%
0.0000100%
0.0000010%
0.0000001%
0.0000000%
1.78 1.74 1.70 1.66 1.62 1.58 1.54 1.50 1.46 1.42 1.38 1.34 1.30 1.26 1.22 1.18 1.14
Environmental-margin
@ 1.69 V
Zero-margin
@ 1.54 V
Supply Voltage (V)
once every 20 seconds!
Error rate
18x18-bit Multiplier Block at 90 MHz and 27 C
Error Rate Studies – SPICE-Level Simulations
 Based on a SPICE-level simulations of a
Kogge-Stone adder
Kogge-Stone Adder at 870 MHz and 27 C
100.00%
1.00%
0.10%
random
bzip
200 mV
0.01%
ammp
0.00%
2
1.8
1.6
1.4
1.2
Supply Voltage
1
0.8
0.6
Error rate
10.00%
EX-Stage Analysis – Optimal Voltage Sweep
Recovery cost includes energy to
recover entire pipeline (18x an add)
BZIP
1.4
Rel Energy
Rel Performance
1
0.8
0.6
0.31% Error Rate,
58% Energy Savings
0.4
Voltage
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.65
1.7
1.75
0.2
1.8
Relative IPC and Energy
1.2
EX-Stage Analysis – Optimal Voltage Sweep
GCC
1.4
Rel Energy
Rel Performance
1
0.8
0.6
1.62% Error Rate,
24% Energy Savings
0.4
Voltage
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.65
1.7
1.75
0.2
1.8
Relative IPC and Energy
1.2
Simulation Analysis – Energy-Optimal Voltage
120
Percentage of Baseline (zero-margin)
100
80
Total Energy
IPC
60
40
20
0
bzip
crafty
eon
gap
gcc
gzip
mcf
parser
twolf
vortex
vpr
Average
Supply Voltage Control System
Simulation Analysis – Razor DVS Execution
GCC
2
40.00%
Voltage
Error Rate
1.8
35.00%
1.6
30.00%
25.00%
1.2
1
20.00%
0.8
15.00%
0.6
10.00%
0.4
5.00%
0.2
0
0.00%
Time
Error Rate
Supply Voltage
1.4
Simulation Analysis – Razor DVS Performance
120
Percentage of Baseline (zero-margin)
100
Total Energy
DVS Energy
IPC
DVS IPC
80
60
40
20
0
bzip
crafty
eon
gap
gcc
gzip
mcf
parser
twolf
vortex
vpr
Average
Previous Work
Conclusion
 Razor advantages
 Eliminate safety margins
 Operate at sub-critical voltage for
optimal trade-off
 Tune voltage for average instruction data
 Paper writing
 Very detailed experiment steps
 Good survey about previous DVS work