EEEE 381 – Electronics I Lab #4: MOSFET Differential Pair with Active Load Overview The differential amplifier is a fundamental building block in electronic design. The objective of this lab is to examine the voltage transfer characteristic and performance of a MOSFET differential amplifier with an active load — i.e., with a PMOS current mirror attached between the drain terminals of the amplifying MOSFETs and the positive power supply. Theory Introduction: The actively-loaded differential amplifier is typically a two-input/single-output circuit, as shown in Figure 1. In this circuit, the output is shown at the drains of M2 and M4 as vo. The two inputs of the differential amplifier are at the gates of M1 and M2. When these inputs are grounded, the bias current available from the current source, Io, splits evenly between the two transistors, assuming that the transistors are identical. The corresponding voltage between the gate and source of the two transistors is known as the Q-point voltage (VGSQ). +5 V CD4007 M3 M4 VDD 5V (DC) vo IREF vg1 VSS 5V (DC) M1 M2 vg2 Io M5 M6 CD4007 –5V Figure 1. Differential amplifier with active load Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 1 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 DC Voltage Transfer Characteristics of a Differential Amplifier: When a differential-mode input signal vdiff is connected to the differential amplifier — that is, v diff v and the other is set at diff — the current in one transistor when one input is set at 2 2 increases while the current in the other decreases. The drain voltage vo of M2 will increase (or decrease) from its Q-point value depending on whether vdiff is positive (or negative). If the input signal is sufficiently positive, then vo will reach a maximum value and saturate at that value. If the input signal is sufficiently negative, then vo will reach a minimum value and saturate at that value. If the input signal to M1 is started at a sufficiently negative value of vdiff and gradually increased toward a sufficiently positive value of vdiff, the voltage vo starts initially at a maximum value, then goes through a segment where vo is proportional to vdiff, and finally saturates at a minimum value. The region where vo is proportional to vdiff is used in analog amplification. Differential-Mode Operation: Figure 2 shows the differential amplifier with inputs applied in differential mode. Assuming matched transistors, the following equations describe the gain of the amplifier. +5 V CD4007 M3 M4 VDD 5V (DC) vo IREF M1 vg1 vdiff 1 kz VSS 5V (DC) M2 vg2 ~ CD4007 M5 Io VCOM (DC) M6 –5V Figure 2. Differential amplifier in differential mode Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 2 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 With v g1 v diff 2 and v g 2 v , the differential-mode gain o v 2 diff vdiff is given by Equation (1): v Ad o g m ro 2 || ro 4 || RL . v diff of a differential amplifier (1) The transconductance gm is given by I W W g m n Cox VGSQ Vt k n VGSQ Vt 2k n I D 2k n o (2) L L 2 where ID is the DC current in M1 or M2, and where a load resistance RL may be attached to the output node (not shown in figure). If RL is not present, we would let RL → ∞ in Equation (1). Note that a common-mode DC supply (VCOM) might need to be provided in addition to the differential signal to bias the amplifier in the correct operating region (all transistors in saturation). This ensures that we get undistorted, or linear, amplification. Since the lower power supply is at 5 V, a value of VCOM = 0 V may be sufficient, but this should be checked as part of the pre-lab preparation. Common-Mode Operation: Figure 3 shows the differential amplifier with inputs applied in. With vg1 = vg2 = vcm, the v common-mode gain o is given by vcm v ro 4 1 1 ACM o (3) 2Ro 1 g m3 ro3 2 g m3 Ro vcm where Ro is the output resistance of the current source. For a simple current source, 1 . (4) Ro ro 6 I o Common-Mode Rejection Ratio: A CMRR (dB) 20 * log d . Acm (5) Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 3 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 +5 V CD4007 M3 M4 VDD 5V (DC) vo IREF M1 vg1 VSS 5V (DC) CD4007 M5 M2 Io M6 –5V vg2 ~ vcm 1 kz VCOM (DC) Figure 3. Differential amplifier in common mode Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 4 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 Pre-Lab For hand calculations use the most basic equations and parameters that match the SPICE model for the CD4007. The results should be similar to the results obtained from SPICE and the build. For example: NMOS SPICE model shows: VT=1.4, KP=UO Cox’=112uA/V2, and NMOS Parameters shown as: L=10u, W=170u, NRD=0.1, NRS=0.1. For PMOS SPICE model shows: VT=1.65, KP=UO Cox’ = 27.6uA/V2, and PMOS parameters as: L=10u, W=360u, NRD=0.54 NRS=0.54. (1) Assuming a 4 mA drain current through M6, calculate the theoretical Q-point values by grounding both inputs of the amplifier in Figure 1 and finding VGSQ1 and VGSQ2. (2) A DC common-mode voltage (VCOM) will be required to allow bias current to flow in the complete differential amplifier circuit. Calculate the minimum value of VCOM that can be applied and still ensure proper operation (i.e., all transistors in saturation) of the differential pair. Note: The threshold voltages of M1 and M2 will be significantly altered by body effect. (3) Using the Q-point values calculated in part (1) and assuming matched transistors, calculate the theoretical differential-mode gain, common-mode gain, and common-mode rejection ratio (CMRR) at vo. (4) Use PSPICE to obtain simulation values for the Q-point voltages. See the Appendix A SPICE Instructions below. (5) Simulate the circuit in Figure 2 with three different input values of vdiff to find the differential-mode gain at vo. Use an input voltage range of 40 mV to 60 mV peak-to-peak amplitude at a frequency of 1 kHz for vdiff. Note that the V_sin voltage source takes true amplitude as one of its inputs, not peak-to-peak amplitude. (6) Simulate the circuit in Figure 3 with three different input values of vcm to find the commonmode gain at vo. Use an input range of 1 V(p–p) to 3 V(p–p) for vcm at a frequency of 1 kHz. Calculate the common-mode rejection ratio of the amplifier. (7) Calculate the common-mode rejection ratio (CMRR) of the amplifier. Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 5 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 Lab Exercise Objectives: (1) Obtain the voltage transfer characteristics of a MOSFET differential pair. (2) Measure the differential-mode and common-mode gains, and determine the CMRR. Hardware Procedure: ** The NMOS substrate (pin 7) must be connected to the most negative voltage supply (–5 V here). The PMOS substrate (pin 14) must be connected to the most positive voltage supply (+5 V here). VDD and VSS need to be connected to provide a path for the Electrostatic discharge ESD circuitry. So do that before connecting anything to the gates of the MOSFETs and remove the gate connections before disconnecting the power supply. Refer to the pin-out diagram in the data sheet given as Figure 4. (or large size pin-out on last page) ** Make sure the signal generator is in High Z mode. (1) Using the simple current source designed in Lab #3, build the differential amplifier circuit shown in Figure 1. Two CD4007 packages will be needed — use one for the differential pair and current mirror (M1 – M4) and a second one for M5 and M6. (2) Ground both inputs of the amplifier. Measure the bias current through the current source and verify that it is approximately 4 mA by temporarily detaching the M6 drain from the differential amplifier and connecting it (the M6 drain) to +5 V through a 1 k resistor (measure the voltage across the 1 k resistor). Then remove the 1 k resistor and reattach the current source to the differential stage. Measure the DC voltages for VGSQ1 and VGSQ2, the Q-point values. (3) Set up the amplifier in differential mode as shown in Figure 2. Make sure that the NMOS substrates (pin 7) are connected to –5 V and that the PMOS substrates (pin 14) are connected to +5 V. Determine the differential-mode gain for three different input values of vdiff. (Make sure that you reset the oscilloscope to its normal mode if you had it running in XY mode previously.) Use the same vdiff values that you used in part (6) of the pre-lab. Use screen capture to store results for each value of vdiff to include in your lab write up. Caution: You must get the common-mode DC supply VCOM up to a point where the differential transistors are operating properly — i.e., in saturation. It is not sufficient to merely get a response at the output node. (You will get a response for VCOM in excess of ~1.5 V above the lower supply because current will be flowing, but this doesn’t mean that all transistors are operating in saturation. You will also see some amplification of the differential input signal.) You must get VCOM at least up the point where your current source is operating properly — i.e., at the designed 4 mA level — and all transistors are in saturation. All your results will be invalid if this is not done properly. (Continues on next page) Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 6 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 (4) Set up the amplifier in common mode as shown in Figure 3. Determine the common-mode gain for three different input voltage values of vcm. Use the same vcm values that you used in part (6) of the pre-lab. Use screen capture to store results to include in your lab notebook. (If the output signal is noisy, try changing the oscilloscope from a normal display mode to an average display mode.) (5) Calculate the CMRR of the amplifier. N.B.: The differential amplifier of Figures 1–3 will be used in subsequent labs (Labs #5–#6), so you may wish to keep it assembled once you have it working properly. Summary and Discussion Compare theoretical, simulation, and hardware values of differential-mode and commonmode gains, and explain any discrepancies. Explain why the differential input signal amplitude should be limited. What would you expect to happen to the output signal for larger input signals? Attach PSPICE simulations: (a) confirming current source design; (b) showing the Voltage Transfer Characteristic (VTC); (c) showing the differential gain of the amplifier (include curves for several different input signal amplitudes); (d) showing the common-mode gain of the amplifier (include curves for several different input signal amplitudes). Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 7 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 Figure 4. CD4007 pin-out and specification Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 8 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 *SPICE MODELS FOR RIT DEVICES AND LABS - DR. LYNN FULLER 8-17-2015 *LOCATION DR.FULLER'S COMPUTER *and also at: http://people.rit.edu/lffeee * *----------------------------------------------------------------------*Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1 .MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54 .MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) *----------------------------------------------------------------------- Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 9 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 Appendix A — PSPICE Instructions Please refer to the following for assistance in modifying the MbreakN MOSFET model. You also need to modify the MbreakP model similarly see the spice model above for values for W, L, NRD, and NRS. We want to place the MbreakN Schematic symbol on our schematic then edit and display the properties to represent the CD4007 transistors. We also want to change the name of the spice Model from MbreakN to RIT4007N7. Right Click on the transistor and select “Edit Properties”, Pivot, Display, Apply Finally, we want to let PSPICE know where to find the text file that has the SPICE MODEL in it. That is done by editing the PSPICE simulation profile. Under the Configuration Files Tab, select Include, and then Browse to the Location of the file where the SPICE model is. (Note: you should have already placed the text file that has the RIT4007N7 SPICE model in it on your computer in some location) Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 10 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 Check-Off Sheet A. Pre-Lab Calculation of theoretical Q-point, VCOM, differential-mode gain, common-mode gain, and common-mode rejection ratio (CMRR) values for the differential amplifier. PSPICE simulation of the Q-point. PSPICE simulation with three different input values of vdiff to find the differential-mode gain at vo. PSPICE simulation with three different input values of vcm to find the common-mode gain at vo. B. Experimental Differential amplifier of Figure 1 built and proper operation verified. Differential amplifier set up as in Figure 2; experimental differential-mode gain obtained for three different input values of vdiff. Differential amplifier set up as in Figure 3; experimental common-mode gain obtained for three different input values of vcm. Experimental value of CMRR calculated. TA Signature: ____________________________ Date: ___________________________ Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 11 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248 Electronics I – EEEE 381 — Lab #4: MOSFET Differential Pair, Active Load — Rev 5.1 (8/22/15) Page 12 of 12 Rochester Institute of Technology Teaching Assistants — Office: 09-3248