ECE 442
Solid-State Devices & Circuits
4. CMOS Logic Circuits
Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
jschutt@emlab.uiuc.edu
ECE 342 – Jose Schutt-Aine
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Digital Logic - Generalization
De Morgan’s Law
A  B  C  ...  A  B  C  ...
A  B  C  ...  A  B  C  ...
Distributive Law
AB  AC  BC  BD  A( B  C )  B(C  D)
•
General Procedure
1.
2.
3.
Design PDN to satisfy logic function
Construct PUN to be complementary of PDN in every way
Optimize using distributive rule
ECE 342 – Jose Schutt-Aine
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CMOS Logic Gate Circuits
•
Two Networks
– Pull-down network (PDN) with NMOS
– Pull-up network (PUN) with PMOS
PUN conducts when inputs are low
and consists of PMOS transistors
PDN consists of NMOS transistors
and is active when inputs are high
•
PDN and PUN utilize devices
– In parallel to form OR functions
– In series to form AND functions
ECE 342 – Jose Schutt-Aine
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Pull-Down Networks
Y  AB
Y  A B
ECE 342 – Jose Schutt-Aine
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Pull-Up Networks
Y  AB
Y  A B
ECE 342 – Jose Schutt-Aine
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Basic Logic Function
Basic
Function
INVERTER
NOR
NAND
Symbol
# Devices
PUN
# Devices
PDN
1
PMOS
2
PMOS-Series
2
PMOS-Parallel
1
NMOS
2
NMOS-Parallel
2
NMOS-Series
Truth
Table
ECE 342 – Jose Schutt-Aine
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Pull-Down and Pull-Up Functions
Pull-up network (PUN)
Pull-down network (PDN)
• Key features
– When PDN switch is on, PUN switch is off
and vice versa
– Conditions for being on and off are
complementary
ECE 342 – Jose Schutt-Aine
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Pull-Down and Pull-Up
PDN-parallel
NMOS
PUN-series
PMOS
YDP  A  B
Truth Tables
ECE 342 – Jose Schutt-Aine
YUS  AB
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Pull-Down and Pull-Up
When YDP in PDN-parallel is low, this means that either A or B (or both) is
high. When either A or B (or both) is high, either transistor (or both) in PUNseries are offYUS=low
When YDP in PDN-parallel is high, both A and B are low. Both transistors in
PUN-Series are on creating a path to VDD. YUS=highYUS=YDP.
PDN-Parallel and PUN-series are complementary
ECE 342 – Jose Schutt-Aine
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Pull-Down and Pull-Up
PDN-Series
NMOS
PUN-Parallel
PMOS
YDS  AB
Truth Tables
ECE 342 – Jose Schutt-Aine
YUP  A  B
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Pull-Down and Pull-Up
If YDS is low, both A and B must be high in which case both transistors in
PUN-Parallel are off providing no path to VDDYUP=lowYUP=YDS.
If YDS is high, then either A or B (or both) are off (low) in which case either
QPA or QPB in PUN-Parallel will be on and present a path to VDD; thus
YUP=high  YUP=YDS
PDN-Series and PUN-Parallel are complementary
ECE 342 – Jose Schutt-Aine
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Two-Input NOR Gate
Y  A  B  AB
ECE 342 – Jose Schutt-Aine
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Two-Input NOR Gate
Ideal
Actual
ECE 342 – Jose Schutt-Aine
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Two-Input NAND Gate
Y  AB  A  B
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Example
Y  AB  CD
Using De Morgan’s Law
Y  AB  CD  AB  CD  ( A  B )  (C  D)
Pull-down network
Pull-up network
ECE 342 – Jose Schutt-Aine
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Example 1
Evaluate Logic Function
Y  ( A  B )C
Y  AB  C
from pull down
from pull up
AB  C  AB  C  ( A  B )C
ECE 342 – Jose Schutt-Aine
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Example 2
Implement the function
Y  AB  C
pull down
pull up
Y  AB  C  AB  C  ( A  B)  C
ECE 342 – Jose Schutt-Aine
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Exclusive-OR (XOR) Function
Y  ( A  B)( A  B )
Y  AB  AB
XOR
pull down
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
ECE 342 – Jose Schutt-Aine
pull up
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