CS612
Algorithms for Electronic Design Automation
Background and Introduction
Mustafa Ozdal
CS 612 – Lecture 2
Mustafa Ozdal
Computer Engineering Department, Bilkent University
1
© KLMH
SOME SLIDES ARE FROM THE BOOK:
VLSI Physical Design: From Graph Partitioning to Timing Closure
MODIFICATIONS WERE MADE ON THE ORIGINAL SLIDES
Chapter 1 – Introduction
Original Authors:
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
2
Lienig
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Electronic Design Automation (EDA)
© KLMH
1.1
In 1965, Gordon Moore (Fairchild)
stated that the number of
transistors on an IC would double
every year. 10 years later, he
revised his statement, asserting
that they double every 18 months.
Since then, this “rule” has been
famously known as Moore’s Law.
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
3
Lienig
Moore: „Cramming more components onto integrated circuits"
Electronics, Vol. 38, No. 8, 1965
Moore’s Law
Electronic Design Automation (EDA)
© KLMH
1.1
Without the design technology
innovations between 1993 and
2007, the design cost of a chip
would have been $1800M
ITRS 2009 Cost Chart
(in2009
Millions
of Chart
Dollars)
ITRS
Cost
(in Millions of Dollars)
120.0
120.0
120.0
100.0
100.0
100.080.0
80.0
80.060.0
60.0
79.0
79.0
56.479.0
56.4
46.7
46.7
33.646.7
33.6
55.7
55.7
42.5
42.5
31.142.5
31.1
35.2
35.2
46.6
46.6
55.7
40.5
40.5
34.046.6
34.0
40.7
27.2
40.7
29.440.5
27.2
29.4
35.2
29.6
33.6
56.4
29.6
21.4
31.1
34.0
21.4
43.5
40.7
40.020.0
44.9
43.5
20.0
44.9
29.4
39.827.2
36.9
39.8
32.9
32.6
36.9
31.7
29.5
29.6
27.0
26.3 32.9
25.2 32.6 27.0
29.5
23.1 31.7
25.2
20.3 19.4
21.416.9
19.4 26.3
16.9 23.1
15.7 20.3
43.5
15.7
44.9
20.0 0.0
39.8
36.9
0.0
32.9
32.6
31.7
29.5
27.0
25.2
20.3 19.4 26.3
16.9202123.12022 2023 2024
15.7
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
0.0 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
60.040.0
40.0
2010 HW
2011
2012 2013
2014
2015
2016 2017
2019 2020Costs
2021+ ESDA
2022 Tool
2023
2024
Total
Engineering
Costs
+ EDA
EDA
Tool Costs
Costs
Total2018
SW Engineering
Engineering
Costs
Total
HW Engineering
Costs
+
Tool
Total
SW
Costs +
ESDA Tool
Costs
Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
4
Lienig
2009
Electronic Design Automation (EDA)
Circuit and Physical Design Process Advancements
1950 -1965
Manual design only.
1965 -1975
Layout editors, e.g., place and route tools, first developed for
printed circuit boards.
1975 -1985
More advanced tools for ICs and PCBs, with more sophisticated
algorithms.
1985 -1990
First performance-driven tools and parallel optimization algorithms
for layout; better understanding of underlying theory (graph theory,
solution complexity, etc.).
1990 -2000
First over-the-cell routing, first 3D and multilayer placement and
routing techniques developed. Automated circuit synthesis and
routability-oriented design become dominant. Start of parallelizing
workloads. Emergence of physical synthesis.
2000 - now
Design for Manufacturability (DFM), optical proximity correction
(OPC), and other techniques emerge at the design-manufacturing
interface. Increased reusability of blocks, including intellectual
property (IP) blocks.
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
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Lienig
Time Period
© 2011 Springer Verlag
© KLMH
1.1
VLSI Design Flow
© KLMH
1.2
System Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural Design
Goals and requirements:
Functionality, performance,
dimensions, etc.
Functional Design
and Logic Design
Circuit Design
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Packaging and
Testing
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
6
Lienig
© 2011 Springer Verlag
Fabrication
VLSI Design Flow
© KLMH
1.2
System Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural Design
Functional Design
and Logic Design
e.g. Instruction set, memory
system, number of cores,
communication protocols, …
Circuit Design
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Packaging and
Testing
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
7
Lienig
© 2011 Springer Verlag
Fabrication
VLSI Design Flow
© KLMH
1.2
System Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural Design
Functional Design
and Logic Design
Circuit Design
Hardware description using
RTL. Logic synthesis tools to
generate netlists.
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Packaging and
Testing
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
8
Lienig
© 2011 Springer Verlag
Fabrication
VLSI Design Flow
© KLMH
1.2
System Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural Design
Functional Design
and Logic Design
Circuit Design
Physical Design
DRC
LVS
ERC
Transistor-level design of
low level elements, e.g.
SRAMs, IO, critical blocks,…
Physical Verification
and Signoff
Packaging and
Testing
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
9
Lienig
© 2011 Springer Verlag
Fabrication
VLSI Design Flow
© KLMH
1.2
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design
Chip Planning
Circuit Design
Placement
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Clock Tree Synthesis
Signal Routing
Fabrication
Packaging and Testing
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
10
Lienig
© 2011 Springer Verlag
Timing Closure
Physical Design
E
A
C
Logic gates & connections
D
B
F
Netlist
Shapes on chip layers
Metal layers
Device layers
Chip Layers
- 11 -
VLSI Design Flow
© KLMH
1.2
System Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural Design
Functional Design
and Logic Design
Circuit Design
Physical Design
Physical Verification
and Signoff
Design rule checking (DRC)
Layout vs. schematic (LVS)
Fabrication
Electrical rule checking (ERC)
Packaging and
Testing
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
12
Lienig
© 2011 Springer Verlag
DRC
LVS
ERC
VLSI Design Flow
© KLMH
1.2
System Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural Design
Functional Design
and Logic Design
Circuit Design
Physical Design
Physical Verification
and Signoff
Packaging and
Testing
Layout sent to a fab (tapeout).
Photomasks used to print the
layout patterns onto layers.
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
13
Lienig
Fabrication
© 2011 Springer Verlag
DRC
LVS
ERC
VLSI Design Flow
© KLMH
1.2
System Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural Design
Functional Design
and Logic Design
Circuit Design
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure
Die is positioned in a package.
Pins connected to the package
pins. Multiple chips can be
integrated.
Chapter 1: Introduction
14
Lienig
Packaging and
Testing
© 2011 Springer Verlag
Fabrication
VLSI Design Styles

Full-custom design
Direct transistor-level design
Max flexibility, few constraints
Potential to highly optimize, but high design cost
Critical and high-volume parts that will be replicated

Semi-custom design
Cell-based: Standard and macro cells
Many pre-designed elements in the libraries
 Array-based: Configure the pre-fabricated elements
e.g. FPGA

CS 612 – Lecture 2
Mustafa Ozdal
Computer Engineering Department, Bilkent University
15
© KLMH
Cell Based Design
Common digital cells
IN1 IN2
OR
OUT
IN1 IN2
INV
NAND
OUT
IN
OUT
IN1 IN2
NOR
OUT
IN1 IN2
OUT
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
16
Lienig
AND
VLSI Design Styles
Vdd
Contact
Metal layer
Vdd
IN2
OUT
IN1
IN2
Poly layer
OUT
Diffusion layer
IN1
p-type
transistor
n-type
transistor
GND
GND
OUT
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
17
Lienig
IN1
IN2
© KLMH
1.3
VLSI Design Styles
Vdd
Contact
Metal layer
Vdd
IN2
OUT
IN1
IN2
Poly layer
OUT
Diffusion layer
IN1
p-type
transistor
n-type
transistor
GND
GND
OUT
Power (Vdd)-Rail
Ground (GND)-Rail
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
18
Lienig
IN1
IN2
© KLMH
1.3
Cell Placement
E
A
C
D
B
F
Implementation on
device layers
available in cell library
(e.g. AND, OR,
NAND, NOR, INV,
etc.)
Metal 1
Cells arranged in
rows on metal1
Device layers
- 19 -
VLSI Design Styles
© KLMH
1.3
Standard cell layout with
a feedthrough cell
Power
Pad
Pad
Standard cell layout using
over-the-cell (OTC routing
Standard
Cells
Ground
Pad
Power
Pad
A
Pad
Standard
Cells
Ground
Pad
A
VDD
VDD
GND
A’
GND
Routing
Channel
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
20
Lienig
Feedthrough
Cell
© 2011 Springer Verlag
A’
Over-the-cell routing
a
a A o
C
o
o
F
o
b
a
aB
E
o
b
a D o
a
b
Metal5
All terminals on
metal1
Connect terminals
using metal layers
Metal4
Metal3
Metal2
Each layer is either
horizontal or vertical
Metal1
- 21 -
Routing Between Two Pins
a
Metal3
C o
a D o
b
Route from C/o to
D/a
Metal2
Metal3: vertical
Metal2: horizontal
o
Metal1
a
Metal1: escape-only
D
o
a
C
b
Interlayer
connection: “via”
- 22 -
© KLMH
Cell Based Design
Layout with macro cells
RAM
PLA
VDD
RAM
PLA
Routing Regions
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
23
Lienig
Pad
GND
© 2011 Springer Verlag
Standard Cell
Block
Why Cell Based Design?

Easier to design, optimize and verify
Reuse of components
 Performance of each cell pre-characterized
 Transistor-level design constraints already handled
 Complexities abstracted in the cell definition
 Optimization easier


Disadvantage: Less room for optimization

Cannot have a cell for every single complex logic function
CS 612 – Lecture 2
Mustafa Ozdal
Computer Engineering Department, Bilkent University
24
© KLMH
Field Programmable Gate Array (FPGA)
After fabrication:
Each logic element can be configured to implement different functions
Each switchbox can be configured to change the connectivity
LB
LB
Switchbox
LB
SB
LB
SB
LB
LB
SB
LB
LB
VLSI Physical Design: From Graph Partitioning to Timing Closure
LB
Chapter 1: Introduction
25
Lienig
SB
Connection
© 2011 Springer Verlag
LB
Logic Element
© KLMH
1.4. Design Rules
Categories of design rules
 Size rules, such as minimum width: The dimensions of any component (shape),
e.g., length of a boundary edge or area of the shape, cannot be smaller than given
minimum values. These values vary across different metal layers.
 Separation rules, such as minimum separation: Two shapes, either on the
same layer or on adjacent layers, must be a minimum (rectilinear or Euclidean
diagonal) distance apart.
 Overlap rules, such as minimum overlap: Two connected shapes on adjacent
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
26
Lienig
layers must have a certain amount of overlap due to inaccuracy of mask alignment
to previously-made patterns on the wafer.
© KLMH
1.4. Design Rules
Categories of design rules
: smallest meaningful technologydependent unit of length

a
c
Minimum Width: a
Minimum Separation: b, c, d
e
Minimum Overlap: e
d
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
27
Lienig
© 2011 Springer Verlag
b
Physical Design Optimizations
© KLMH
1.5
Types of constraints
 Technology constraints enable fabrication for a specific technology node
and are derived from technology restrictions. Examples include minimum layout
widths and spacing values between layout shapes.
 Electrical constraints ensure the desired electrical behavior of the design.
Examples include meeting maximum timing constraints for signal delay and staying
below maximum coupling capacitances.
 Geometry (design methodology) constraints are introduced to
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
28
Lienig
reduce the overall complexity of the design process. Examples include the use of
preferred wiring directions during routing, and the placement of standard cells in
rows.
Algorithms and Complexity
© KLMH
1.6
Runtime complexity
 Runtime complexity: the time required by the algorithm to
complete as a function of some natural measure of the problem size,
allows comparing the scalability of various algorithms
 Complexity is represented in an asymptotic sense, with respect to the
input size n, using big-Oh notation or O(…)
 Runtime t(n) is order f (n), written as t(n) = O(f (n))
t(n)
lim
=k
n®¥ f (n)
where k is a real number
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
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 Example: t(n) = 7n! + n2 + 100, then t(n) = O(n!)
because n! is the fastest growing term as n  .
Algorithms and Complexity
© KLMH
1.6
Runtime complexity
 Example: Exhaustively Enumerating All Placement Possibilities

Given: n cells

Task: find a single-row placement of n cells with minimum total wirelength by using
exhaustive enumeration.

Solution: The solution space consists of n! placement options. If generating and
evaluating the wirelength of each possible placement solution takes 1 s and
n = 20, the total time needed to find an optimal solution would be 77,147 years!

A number of physical design problems have best-known algorithm complexities that
grow exponentially with n, e.g., O(n!), O(nn), and O(2n).

Many of these problems are NP-hard (NP: non-deterministic polynomial time)

No known algorithms can ensure, in a time-efficient manner, globally optimal solution
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
30
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 Heuristic algorithms are used to find near-optimal solutions
Algorithms and Complexity
© KLMH
1.6
Heuristic algorithms
 Deterministic: All decisions made by the algorithm are repeatable, i.e., not
random. One example of a deterministic heuristic is A* shortest path algorithm.
 Stochastic: Some decisions made by the algorithm are made randomly, e.g.,
using a pseudo-random number generator. Thus, two independent runs of the
algorithm will produce two different solutions with high probability. One example of a
stochastic algorithm is simulated annealing.

In terms of structure, a heuristic algorithm can be
 Constructive: The heuristic starts with an initial, incomplete (partial) solution and
adds components until a complete solution is obtained.
 Iterative: The heuristic starts with a complete solution and repeatedly improves
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
31
Lienig
the current solution until a preset termination criterion is reached.
Algorithms and Complexity
© KLMH
1.6
Heuristic algorithms
Problem Instance
Constructive Algorithm
Initial Solution
Iterative Improvement
Termination
Criterion Met?
no
yes
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
32
Lienig
Return Best-Seen Solution
Graph Theory Terminology
© KLMH
1.7
Graph
Hypergraph
b
Multigraph
b
b
a
e
f
c
a
a
d
f
g
c
c
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
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© 2011 Springer Verlag
d
e
Graph Theory Terminology
© KLMH
1.7
Directed graphs with cycles
c
Directed acyclic graph
c
f
f
a
a
b
d
g
a
b
d
g
e
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
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© 2011 Springer Verlag
e
b
Graph Theory Terminology
© KLMH
1.7
Undirected graph with maximum node degree 3
Directed tree
a
b
a
f
c
b
d
c
e
g
e
f
g
h
i
j
k
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
35
Lienig
© 2011 Springer Verlag
d
Graph Theory Terminology
© KLMH
1.7
Rectilinear minimum spanning
tree (RMST)
b (2,6)
Rectilinear Steiner minimum
tree (RSMT)
b (2,6)
Steiner point
VLSI Physical Design: From Graph Partitioning to Timing Closure
a (2,1)
Chapter 1: Introduction
36
Lienig
a (2,1)
c (6,4)
© 2011 Springer Verlag
c (6,4)
Common EDA Terminology
© KLMH
1.8
Netlist
a
N1
b
x
N3
N2
N4
y
z
N5
c
(a: N1)
(b: N2)
(c: N5)
(x: IN1 N1, IN2 N2, OUT N3)
(y: IN1 N1, IN2 N2, OUT N4)
(z: IN1 N3, IN2 N4, OUT N5)
Net-Oriented Netlist
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
37
Lienig
© 2011 Springer
Pin-Oriented Netlist
(N1: a, x.IN1, y.IN1)
(N2: b, x.IN2, y.IN2)
(N3: x.OUT, z.IN1)
(N4: y.OUT, z.IN2)
(N5: z.OUT, c)
Common EDA Terminology
© KLMH
1.8
Connectivity graph
a
N1
N3
N2
N4
z
N5
x
c
z
y
b
c
y
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
38
Lienig
© 2011 Springer Verlag
b
a
x
Common EDA Terminology
© KLMH
1.8
Connectivity matrix
a
N1
N3
N2
N4
z
N5
c
y
b
x
y
z
c
a
0
0
1
1
0
0
b
0
0
1
1
0
0
x
1
1
0
2
1
0
y
1
1
2
0
1
0
z
0
0
1
1
0
1
c
0
0
0
0
1
0
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
39
Lienig
© 2011 Springer Verlag
b
x
a
Common EDA Terminology
© KLMH
1.8
Distance metric between two points P1 (x1,y1) and P2 (x2,y2)
d  n x2  x1  y2  y1
n
n
d E ( P1 , P2 )  ( x2  x1 ) 2  ( y2  y1 ) 2
with n = 2: Euclidean distance
d M ( P1 , P2 )  x2  x1  y2  y1
n = 1: Manhattan distance
P1 (2,4)
dM = 7
dE = 5
P2 (6,1)
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 1: Introduction
40
Lienig
dM = 7
© KLMH
Next Lecture: Netlist and System Partitioning
2.1
Introduction
2.2
Terminology
2.3
Optimization Goals
2.4
Partitioning Algorithms
2.4.1 Kernighan-Lin (KL) Algorithm
2.4.2 Extensions of the Kernighan-Lin Algorithm
2.4.3 Fiduccia-Mattheyses (FM) Algorithm
2.5
Framework for Multilevel Partitioning
2.5.1 Clustering
2.5.2 Multilevel Partitioning
System Partitioning onto Multiple FPGAs
VLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 2: Netlist and System Partitioning
41
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2.6