In the Face of Integration, Abstraction Empowers Complexity by Tom Williams, Editor-in-Chief There is a common wisdom that goes something like, “with the scale of integration these days, so many things that were once implemented on a board module are now integrated on a single piece of silicon.” There is, of course, truth to that as far as it goes, but what are the practical implications? Yes, processors are certainly more highly integrated with multiple CPU cores, high-performance on-chip graphics, a variety of integrated peripherals and more. This has most certainly and almost universally reduced the component count for small form factor systems, making them smaller and reducing power consumption and costs. The picture changes rapidly when we start talking about custom silicon. Whenever we contemplate a custom silicon design, even when it only involves putting together predefined blocks of silicon IP, that means at some point firing up a fab. And that means many dollars that can only be justified by sufficient volume. Back when Motorola was in the business of making the 68000 microcontroller line, they had a large selection of designs with a wide choice of mixes of different peripherals. That came about partly because the company would do a custom design to a customer’s order, but that design would also become part of the 68000 product line. A similar variety grew up around the 8-bit Intel 8051 microcontroller family, resulting in vast catalogs of variants. Partially as an alternative to this, Cypress came up with a configurable Programmable System on Chip, or PSoC, and its PSoC 3 line is based around an 8-bit 8051 core. The family has since grown to include PSoCs based on 32-bit ARM cores as well, but has in common an area of programmable PLD-based logic that a developer can use to define a selection of peripheral devices. A tool called PSoC Creator offers a high-level graphical environment that lets the user define this peripheral set at a high level of abstraction. More recently, we have seen the advent of what we have here called application service platforms (ASPs), which combine a single or dual ARM core with a set of commonly used hardwired peripherals along with a full-blown FPGA fabric. These are offered by Xilinx (Zync-7000), Microsemi (SmartFusion) and Altera (Cyclone V). More about these a bit later. The cost barrier with a full-blown ASIC or SoC is that it involves IC design and most often the use of electronic design automation (EDA) tools, which remain the domain of specialists and are not generally used by embedded system developers, who mostly use the silicon products developed with these tools. However, that may be changing somewhat. High levels of integration involve high levels of complexity, and the best or only way to deal with high complexity is with high levels of abstraction. We are starting to see the emergence of some tools that will let developers specify their designs at higher levels of functionality, most often defined by the desired function of the software that the tool will then automate at the lower hardware levels. See the articles in this issue from Mentor Graphics and Cadence for a closer look at this trend. There is even a cooperative effort underway between Associated Compiler Experts and Synopsis to integrate compiler with processor design technology in such a way that would result in an application-specific instruction set processor (ASISP). This would allow the design of custom instructions that would in turn be able to generate a C compiler along with the hardware design. While it is not clear what the level of abstraction is for the processor and instruction set design, it nonetheless brings in the software developer to the early stages of hardware definition. This means that the application concepts drive the silicon design from the start. Again, any of these breakthroughs will still involve a fab and the corresponding volume demands. They will, however, greatly limit the risk of a redesign after the first fabrication run. By allowing the software requirements to define the hardware design and then run on the virtual hardware, both can be better verified prior to actually throwing the switch at the fab. The greatest promise for really custom designs at relatively low volumes and hence costs seems to us to lie with the above-mentioned ASPs. I have heard objections that they are still pretty pricey, but we all know that will go away if they come into ever wider use. What appears to be lacking is a common high-level development environment. Now each of these companies has created a suite of tools that seem to work very well with their products. What is needed is a tool metaphor that can unite the worlds of programmer and FPGA developer at a high level of abstraction and that could be applied to any of these products the way the C language can be used with a vast number of CPUs. That would allow choices among a unified number of applications, and drive up the acceptance while driving down the costs of these truly advanced devices. I know that’s asking a lot, but you should see what I expected of Santa as a kid.