VFET – A Transistor Structure for
Amorphous semiconductors
Michael Greenman, Ariel Ben-Sasson, Nir Tessler
Sara and Moshe Zisapel Nano-Electronic Center, EE Dept., Technion Israel
Institute of Technology, Haifa, Israel
III
Vertical Transistors
Vacuum tube triode
Vertical-junction fieldeffect transistor
Solid state triode
(AKA SCLT)
Vertical Organic FET
Patent US841387 from 10/25/1906
D. C. Mayer, N. A. Masnari, and R. J. Lomax, Ieee
Transactions on Electron Devices 27, 956-961 (1980).
Yang, Y.; Heeger, A. J. Nature 1994, 372, (6504), 344346.
L. P. Ma and Y. Yang, Appl. Phys. Lett. 85 (21),
5084 (2004).
Lateral Goes Vertical
Source
L
Drain
Drain
Semiconductor
Source
SiO2
Si++
SiO2
Gate
Si++
Lateral
FET:
Gate
Vertical
FET:
Channel Length
Direction
Location
Ma, L. & Yang, Y. Applied Physics APL 85, 5084 (2004).
III
VOFET Architecture
Patterned source electrode
Source electrode characteristics
A. J. Ben-Sasson et al., Applied Physics
Letters 95, 213301 (2009).
L
Conductive; Transparent
Perforated conductive layer
Virtual electrode
Processes:
Block-copolymers
Di-block copolymer self-assembly
fPMMA
fPS
Processes - Blockcopolymers
Annealing
Disordered to molecularly
organized
Thermal annealing
[T↑, TG const.]
Solvent annealing
[T const., TG↓]
3µm
Block-copolymers
as photolithography
masks
Processes:
Block-copolymers
Design tools:
• Chemistry
• Dimensions
• Process
95
Transmittance [%]
IV
90
85
80
75
70
65
60
1
2
3
4
10
10
10
10
Sheet resistance [ohm/sq]
Creating patterned source electrode using block
co-polymers (BCP) lithography.
PS
PMMA
PMMA
Au
PS
PS
R  100   , T  90%
 
Au
Ben-Sasson, A. J. et al. Patterned electrode vertical field effect
transistor fabricated using block copolymer nanotemplates.
Applied Physics Letters 95, 213301 (2009).
Works on cm scale
samples
Device architecture
3D Illustration
Macro scale top view
100μm
500μm
100μm
Fundamental parameters
Gate – Al
L - Channel length - active layer thickness
D - Perforations’ diameter (~80nm)
FF - perforations area ratio
td & ts
Drain – Al
Dielectric – td
Active layer
Patterned source – ts 100Å Au
O. Globerman, M.Sc. Thesis, Electrical Engineering, Technion, Israel, 2006
A. J. Ben-Sasson and N. Tessler, Nano Letters, vol. 12, pp. 4729-4733, 2012/09/12 2012.
How VOFET works?
Our approach – patterned source electrode:
L
L
L  0.2  0.05  m
Sze, S. & Ng, K. Physics of
semiconductor devices. (2006).
How VOFET works?
Charge density in the
Semiconductor layer for VDS  3V 
x
y
Unbiased gate
VGS  0 V 
x
y
Virtual contact
Formation
VGS  3V 
Drain
OFF
ON
OFF
V 0
Off state – Contact Limited
due to Schottky barrier
y
Patterned
source
Gate dielectric
Gate
On state – Virtual
contact, Space Charged
Limited Current
x
Saturated virtual
contact
VGS  9 V 
The effect of the perforations’ aspect ratio
Measurements
-3
10
Simulations
-9
4 10
(a) VDS=1V
(b) VDS=1V
-3
-9
10
1 10
10
0
ON
V 0
-4
10
S
-5
10
-10
0
10
20
30
40
Au
-6
0
10
V [V]
G
Patterned
source
Gate dielectric
Gate
e-
SC
Φb0
10
-7
10
-2
-9
-6
Drain
-9
2 10
D
-5
J [Acm ]
7
9
13
D
-2
J [Acm ]
hS[nm]
IG[A]
-4
10
10
3 10
“Thick” source  Tunnel effect
20
V [V]
G
D
h+
C60
30
Al
40
The Electrode Barrier
Φb
• High barrier  High On/Off
• High barrier  High VTO
100
10-2
VOn
10-4
10-6
0.4eV
0.6eV
0.8eV
1eV
DS
2
J [A/cm ]
On and Off channel
spatial origin is different
10-8
10-10
10-12
-2
0
2
4
V [V]
G
A. J. Ben-Sasson, N. Tessler, Journal of Applied Physics 110, 044501 (2011).
6
8
V.B
Stractured electrode
Non-uniform structure
JOff
JOn
-3
10
-5
10
-7
10
-9
10
-11
-2
0.4-0.4eV
0.4-0.6eV
0.4-0.8eV
0.4-1eV
JOff
0
2
V [V]
G
4
10-2
VOn
10-4
10-6
0.4eV
0.6eV
0.8eV
1eV
DS
10
VOn
2
-1
100
J [A/cm ]
J
1
10
DS
2
[A/cm ]
10
10-8
10-10
10-12
-2
0
2
4
V [V]
G
6
8
DC characteristics
Reducing Vg:
Gate
Source
Active
Drain
A. Ben-Sasson, G. Ankonina, M. Greenman , M. T. Grimes and N. Tessler ,
Low-temperature molecular vapor deposition of ultra-thin metal oxide dielectric
for low-voltage vertical organic field effect transistors, ACS Appl Mater
Interfaces (2013)
Solution processed active layer:
Drain (Al)
4.08 eV
N2200
Source(Au)
4.0 eV
5.1 eV
5.6 eV
Ben-Sasson, A. J., Chen, Z., Facchetti, A. & Tessler, N. Solution-processed ambipolar vertical
organic field effect transistor. Applied Physics Letters 100, 263306 (2012).
Silver Nanowire Based Electrode
Silver Nanowire Based Electrode
Time resolved measurement
Assembling time-resolved setup
reducing source resistance
VDS  20V
RD , Load  1.2 K 
ton  2  s
Vgs  10 V   10 V 
9
VFET
Source
2
Current [A/cm ]
6
Scope
ch1
RS ,amplifier  100
3
Drain
Voltage
Amplifier
0
-3
-5
0
5
10
15
20
25
30
Time [sec]
Greenman, M., Ben-Sasson, A. J., Chen, Z., Facchetti, A. & Tessler, N. Fast
switching characteristics in vertical organic field effect transistors. Appl. Phys. Lett.
103, 073502 (2013).
Scope
ch2
Time resolved measurement
Time-resolved simulation
TOF : 16ns  32ns
=10-3cm2V-1s-1
=10+1cm2V-1s-1
ns turns into ps
Greenman, M., Ben-Sasson, A. J., Chen, Z., Facchetti, A. & Tessler, N. Fast switching characteristics in
vertical organic field effect transistors. Appl. Phys. Lett. 103, 073502 (2013).
Silver Nanowire Based Electrode
Silver Nanowire Based Electrode
A. J. Ben-Sasson et al., Self-Assembled Metallic Nanowire-Based Vertical
Organic Field-Effect Transistor. ACS Appl. Mater. Interfaces 7, 2149-2152 (2015)
Standard photo-lithography
Replacing BCP technic with basic lithography:
10 m
2.5 m
Fits for metric scale substrates.
(matches for standard FAB lines)
Enables more complex lift-off or
etching process.
Holes diameter:
~ 60nm
0.5 m  1.1 m
Standard photo-lithography
Unit cell
Holes diameter effect
D
Fill Factor
2 m

PTCDI VOFET Vds=20V
100
1600
2
16
20 m
Drain Current (A/cm )
Diameter
Perimeter per
unit cell
Perimeter per
device area
20
2000
2D
200
200
Perimeter Area = Injection Area
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
-5
2m
20m
0
5
10 15 20 25
Gate Sorce Voltage (V)
30
Conventional photo-lithography
Connecting VOFET’s to invertor:
PTCDI and Poly TPD VOFET invertor
•
The first VOFET invertor!
Not good but still invert the
signal.
Low performance due to PVOFET strong off current.
Output Voltage [V]
•
•
15
Vdd=10
Vdd=12.5
Vdd=15
10
5
0
0
5
10
15
20
Gate Bias [V]
25
30
Thank You
The fabrication was performed at the MicroNano Fabrication Unit (MNFU), Technion.