NEWSDR 2015
2015 New England Workshop
for Software Defined Radio
Implementation of a Full Duplex Transceiver using Xilinx Zynq SoC and ADI RFCOMMS3 Board
Benjamin Drozdenko (bdrozdenko@coe.neu.edu), Rahman Doost (doost@ece.neu.edu), Kaushik Chowdhury (krc@ece.neu.edu), Miriam Leeser (mel@coe.neu.edu)
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• Software-defined radio (SDR) transitions the communication signal processing chain from a
rigid HW platform to a user-controlled paradigm, allowing flexibility in parameter settings.
Performing the most common SDR operations in software is usually less efficient than a HW implementation.
Gigabit
Modern real-time bi-directional communications systems may be difficult to model using only a typical CPU.
Ethernet
Some components of the communication system would be more advantageously implemented using FPGA.
We design a full duplex 802.11a transceiver with split functionality between a processor and logic fabric.
We implement our design using the Xilinx Zynq ZC706 SoC and the AD-FMCOMMS3-EBZ RF transceiver.
We experiment using GNU radio and MathWorks products for building functions to interface with the radio.
Abstract
Tools Option 1
Background
Hardware Setup
• IEEE 802.11a Physical (PHY) and Medium Access Control (MAC)
layer frame structure with some modifications
• Orthogonal Frequency Division Multiplexing (OFDM) used to carry data on multiple channels
• Binary/Quadrature Phase Shift Keying (B/QPSK) modulation used to encode bits as symbols
• Cyclic Prefix: prefix a symbol with a repetition of the end, eliminates intersymbol interference
from previous symbol; allows linear convolution to be modeled as circular, enabling DFT
MathWorks Products: Simulink + HDL Coder
• Communications System Toolbox Support Package for
Xilinx Zynq-Based Radio: allows access to RFCOMMS board
on Zynq using MATLAB System objects or Simulink blocks
• HDL Coder Support Package for Xilinx Zynq-7000 Platform:
allows generation of HDL from Simulink blocks and
placement on the Zynq PL.
• Embedded Coder Support Package for Xilinx Zynq-7000
Platform: allows generation of C code from MATLAB code
or Simulink blocks to be built on the Zynq PS ARM.
• Benefits:
PS
User
PS
• Many blocks for DSP (e.g. FFT & IFFT) and communications (e.g. B/
QPSK modulation) support automatic generation of HDL & C code
• Easy generation of HDL and PL image using HDL Workflow Advisor
PL
Receive Path
GNU Radio + Vivado
Tools Option 2
PL
Receive Path
• Disadvantage:
• As of R2015a, no way to model comms between PS & PL via AXI
• To be added in a future release
• In the meantime, must target system for either PS or PL
• A PL-only Tx-Rx chain is shown at right
• Original HDL core only handles basic data read
and write from/to ADC/DAC to/from DMA
interface.
• The ADC core operates at interface speed and
data width and hence might cause overrun to
the downstream modules.
• Computationally expensive blocks, such as
frame detection, can be implemented using the
Vivado tools for major speed up and offloading
of downstream modules.
• A new interface with a different clock speed
and bus width and enable/disable signals is
designed.
• Appropriate changes to the LIBIIO modules are
applied to accommodate the low level changes.
• Not all blocks supported for HDL generation (e.g. correlation)
• Data received in fixed-length packets, buffer allows
accumulation of samples
• Enabled subsystems allow for presence of states
Transmit Path
RFCOMMS LPC
GigE
• In Active Search state, receiver correlates signal with preamble to
find synchronization delay
• In Recover Decode state, receiver performs OFDM & B/QPSK
demodulation, cyclic prefix removal
• OFDM blocks not supported for HDL generation, but can
build using FFT/IFFT
Xilinx® ZYNQ™ ZC706 SoC
– Processing System (PS)
– Dual-Core ARM Cortex-A9 processor
– Fixed architecture supports SW
routines & operating systems
– Equivalent to logic of an FPGA
– A completely flexible canvas
– Ideal for high-speed logic, arithmetic,
& data flow subsystems
– Advanced Extensible Interface makes
links between PL & PS
– Connects peripherals in PL, incl.:
Active Search
Recover Decode
Challenges
• How to partition transceiver subsystem
blocks between the Zynq PL & PS?
• Which tools to use to generate HDL and
build an image file for the Zynq SD card?
• Which tools to use to generate and build
C code targeted for the PS ARM?
Future Work
• Tools Opt 1: Model OFDM & Correlation
using blocks that support HDL generation
• Tools Opt 2: Parametrized FPGA Blocks with
proper control in the user space
RFCOMMS LPC
– Programmable Logic (PL)
– AXI Interconnect
Designated Receiver (DRx)
Transmit Path
References
[1] IEEE Std 802.11a-1999. Part 11: Wireless LAN Medium Access. Control (MAC) and Physical Layer (PHY)
specifications. URL: http://standards.ieee.org/getieee802/download/802.11a-1999.pdf.
[2] Analog Devices, Inc. Various (online).
– Coprocessors
1.“AD-FMCOMMS3-EBZ User Guide.” URL: http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms3-ebz.
– Cores for interacting with external
interfaces (LEDs, switches, codecs)
2.“What is libiio?” URL: http://wiki.analog.com/resources/tools-software/linux-software/libiio.
– Additional memory elements
3.ADI Reference Designs HDL User Guide, URL: http://wiki.analog.com/resources/fpga/docs/hdl.
Analog Devices, Inc.
4.EVAL-AD-FMCOMMS3-EBZ. URL: http://www.analog.com/en/design-center/evaluation-hardware-andsoftware/evaluation-boards-kits/eval-ad-fmcomms3-ebz.html.
AD-FMCOMMS3-EBZ
[3] University of Strathclyde Glasgow. The Zynq Book. Embedded Processing with the ARM Cortex-A9 on the Xilinx
• An RF platform to software
Zynq-7000 All Programmable SoC. URL: http://www.zynqbook.com/.
developers & system architects [4] MathWorks, Inc. Various (online).
1.“Guided Code Generation.” URL: http://www.mathworks.com/help/hdlcoder/hdl-workflow-advisor.html.
• Operates over a much wider
2.“Targeting HDL Optimized QPSK Transmitter with Analog Devices FMCOMMS2/3/4.” URL:
tuning range, 70 MHz – 6 GHz
http://www.mathworks.com/help/releases/R2015a/supportpkg/xilinxzynqbasedradio/examples/targeting-hdloptimized-qpsk-transmitter-with-analog-devices-fmcomms2-3-4.html.
• Works much better than the
3.“Targeting HDL Optimized QPSK Receiver with Analog Devices FMCOMMS2/3/4.” URL:
AD-FMCOMMS2-EBZ over the
http://www.mathworks.com/help/releases/R2015a/supportpkg/xilinxzynqbasedradio/examples/targeting-hdlcomplete RF frequency
optimized-qpsk-receiver-with-analog-devices-fmcomms2-3-4.html.
[5] B. Bloessl, M. Segata, C. Sommer, and F. Dressler. An IEEE 802.11 a/g/p OFDM Receiver for GNU Radio.
– RX/TX RF differential-to-singlend workshop on Software radio implementation forum, pp. 9-16. ACM, New York, NY, 2013.
Proceedings
of
the
2
ended transformer is targeted for
[6] Xilinx, Inc. “Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit.” URL:
wider tuning range applications
http://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html#hardware.