EECS 362
Computer Architecture
Projects
Lecture 1
Instructor: Alok Choudhary
Co-instructor: Avery Ching
Outline
Course Overview
 Administrative Matters
 Course Structure
 Recap of Pipeline Processor
 First Week’s Assignment
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Course Overview
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Course involves the design and evaluation of a
pipelined processor:
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ISA design
Design and test of components
Design and test of datapath/control
Evaluating for correctness and performance using benchmark
programs
The target instruction set is a subset of the DLX ISA
If you haven’t taken EECS 361 - Drop the class!
Course Information
Instructor: Professor Alok Choudhary
Room: L469 Tech
Phone: (847) 467-4129
E-mail: choudhar@ece.northwestern.edu
Office Hours: TBD
Co-instructor: Avery Ching
Room: L460 Tech
Phone: (847) 467-2299
E-mail: aching@ece.northwestern.edu
Office Hours: TBD
Teaching Assistant: Kenin Coloma
Room: L460 Tech
Phone: (847) 467-2299
E-mail: kcoloma@ece.northwestern.edu
Office Hours: TBD
Class web page: http://www.ece.northwestern.edu/~aching/EECS362/
Textbooks:
The DLX Instruction Set Architecture Handbook (provided by instructors)
Philip M. Sailer and David R. Kaeli
Morgan Kauffman Publishers, 1996.
Computer Organization and Design: The Hardware/Software Interface
David A. Patterson and John L. Hennessy
Morgan Kaufmann Publisher, 2002 or 2005
Course Philosophy
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The entire class will be a project class.
One of the two classes (Thursdays), each group will meet me individually.
Each group will meet for 25 minutes.
The other class (Tuesdays) requires each group to make a 25 minute
presentation to rest of the class. The presentation should be professional and
put on the web.
Each group will do the following:
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Describe goals for the current week (and if they were accomplished)
Goals for the next week
Problems and difficulties encountered and how they were solved
Put all the material including the talk and summary of progress on their group
web page (latest by one day after it was presented to get credit for it).
Grading
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30% weekly progress
70% final project and results (due on last day of class with the report)
What is available?
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dlxcc - a C compiler for DLX
dlxasm – an assembler for DLX
dlxsim and dlxview – a command-line and graphical DLX
simulator. Used to determine correct program behavior for
debugging.
Description of these tools are available in the book and on the
course web page.
Both executables and original sources are available –
benchmarking and testing programs will be provided as the
course progresses.
Also, see the web site given in the book and at MKP
(www.mkp.com).
DLX ISA
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Most similar to MIPS
Load/Store
32 GP registers
32 Single precision FP registers
MIPS R3000 Instruction Set Architecture
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Instruction Categories
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Load/Store
Computational
Jump and Branch
Floating Point
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F0 - F31
R0 - R31
coprocessor
PC
HI
LO
Memory Management
Special
Instruction Format
OP
rs
rt
rd
OP
OP
sa
immediate
target
funct
A Pipelined Datapath
Clk
Ifetch
Reg/Dec
Exec
ExtOp
RegWr
Mem
ALUOp
Wr
Branch
1
0
Rt
RFile
Rw Di
Exec
Unit
0
Rd
Data
Mem
RA Do
WA
Di
1
RegDst
ALUSrc
MemWr
MemtoReg
1
Mux
IUnit
Rt
Rb
Zero
Mem/Wr Register
Ra
Ex/Mem Register
Rs
Imm16
busA
busB
ID/Ex Register
A
I
PC+4
Imm16
IF/ID Register
PC
PC+4
PC+4
0
What to Do Next
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Form groups of 3-4 (work in a team)
First week
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Go through the software and documentation (will be helpful to you in understanding how
you would develop your design)
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Understand instruction set for DLX
Give thought to how you would design a pipelined processor
Present your thoughts during the second class (Tuesday – 1/9/2007) of second week
Toolset tutorial for those who need it this upcoming Thursday 1/11/2007 in L460
Each of the n groups should then present 1/nth of the DLX ISA.
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The simulator does not tell you how to design the processor
Register Ops
Branch/Jump
Load/Store
Floating Point and Others
Each week document each group member’s contributions on group website