# 순차 회로 - University of Engineering and Technology, Taxila

```순차 회로
논리 설계
3. 순차 회로 (6-10장)
Soonhoi Ha
Seoul National University
School of Computer Science and Engineering
Soonhoi Ha Transparency No. 3-1
순차 회로
Chapter Overview
[ Chapter 6 ] Sequential Logic Design
 Sequential Logic Elements
 Timing Methodologies
 Registers
 Hardware Description Languages
[ Chapter 7 ] Finite State Machines
 Counters
 Concept of Finite State Machines
 Basic FSM Design Approach
Soonhoi Ha Transparency No. 3-2
순차 회로
Sequential circuits
 Circuits with feedback
 outputs = f(inputs, past inputs, past outputs)
 basis for building &quot;memory&quot; into logic circuits
 door combination lock is an example of a sequential circuit
state is memory
 state is an &quot;output&quot; and an &quot;input&quot; to combinational logic
 combination storage elements are also memory

New equal Reset
value
C1
C2
C3
Multiplexer
Comparator
MUX
control
Comb. logic
state
clock
equal
Soonhoi Ha Transparency No. 3-3
순차 회로
Sequential Logic
 Sequential logic
- system has “states”
- new component in sequential logic networks:
storage elements to remember the current state
- outputs depend on inputs and the states.
- new state is a function of the inputs and the old
state i.e., the fed back inputs are the state!
 Synchronous systems
period reference signal, the clock, causes the storage
elements to accept new values and to change state
 Asynchronous systems
no single indication of when to change state
Soonhoi Ha Transparency No. 3-4
순차 회로
Simple Circuits with Feedback
 Simple Circuits with Feedback
Basis for commercial static RAM designs
Cross-coupled NOR gates and NAND gates also possible
&quot;1&quot;
&quot;0&quot;
LD
\LD
\LD
A
Selectively break feedback path to
Z
LD
&quot;remember&quot;
&quot;data&quot;
&quot;stored value&quot;
Soonhoi Ha Transparency No. 3-5
순차 회로
Simple Circuits with Feedback
 Cross-Coupled NOR Gates
Just like cascaded inverters, with capability to force
output to 0 (reset) or 1 (set)
R
Q
R
S
S
\Q
Timing Waveform
Reset
Hold
Set
Reset
Set
100
R
S
Q
\Q
Forbidden
State
Forbidden
State
Soonhoi Ha Transparency No. 3-6
Race
순차 회로
R-S Latch
 State Behavior of R-S Latch
SR = 00, 10
SR = 00, 01
S R
Q
0 0
hold
0 1
0
1 0
1
1 1 unst able
SR = 1 0
QQ
01
QQ
10
SR = 0 1
SR = 0 1
SR = 1 0
SR = 11
SR = 1 1
SR = 1 1
QQ
00
SR = 0 1
SR = 1 0
SR = 0 0
SR = 0 0, 11
QQ
11
Soonhoi Ha Transparency No. 3-7
순차 회로
R-S Latch
Observed R-S Latch Behavior
SR = 00, 10
SR = 00, 01
SR = 1 0
QQ
01
QQ
10
SR = 0 1
SR = 0 1
SR = 1 0
SR = 11
SR = 1 1
SR = 1 1
QQ
00
SR = 0 0
SR = 0 0
Very difficult to observe R-S Latch in the 1-1 state
Ambiguously returns to state 0-1 or 1-0
A so-called &quot;race condition&quot;
Soonhoi Ha Transparency No. 3-8
순차 회로
R-S latch analysis
 Breaking feedback path
R
Q
Q'
S
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
Q(t)
0
1
0
1
0
1
0
1
Q(t)
Q(t+)
S
R
Q(t+)
0 hold
1
0 reset
0
1 set
1
X not allowed
X
S
0
0
X
1
Q(t) 1
0
X
1
R
characteristic equation
Q(t+) = S + R’ Q(t)
Soonhoi Ha Transparency No. 3-9
순차 회로
Level-Sensitive Latch
Level-Sensitive Latch aka Gated R-S Latch
Schematic:
\S
\Q
\R
Q
\Enable
Timing Diagram:
Set
Reset
\S
\R
\Enable
Q
\Q
Soonhoi Ha Transparency No. 3-10
순차 회로
Clocks
 Used to keep time
 wait long enough for inputs (R' and S') to settle
 then allow to have effect on value stored
 Clocks are regular periodic signals
 period (time between ticks)
 duty-cycle (time clock is high between ticks - expressed as %
of period)
duty cycle (in this case, 50%)
period
Soonhoi Ha Transparency No. 3-11
순차 회로
Clocks
 Controlling an R-S latch with a clock
 can't let R and S change while clock is active (allowing R and
S to pass)
 only have half of clock period for signal changes to propagate
 signals must be stable for the other half of clock period
R’
R
Q
clock’
S’
Q’
S
R’ and S’
changing
changing
clock’
Soonhoi Ha Transparency No. 3-12
Gated D-latch
Gated D Latch
순차 회로
D
\Q
\C
Q
Gated RS latch
Soonhoi Ha Transparency No. 3-13
순차 회로
J-K Latch
How to eliminate the forbidden state?
Idea: use output feedback to
guarantee that R and S are
never both one
J, K both one yields toggle
JK
Q(t) 00
0 0
01
11
10
0
1
1
1
0
0
1
1
K
R
J
S
\Q
\Q
Q
Q
R-S
latch
Characteristic Equation:
Q+ = Q K + Q J
hold reset toggle set
Soonhoi Ha Transparency No. 3-14
순차 회로
 Connect output of one latch to input of another
 How to stop changes from racing through chain?
 need to be able to control flow of data from one latch to the
next
 move one latch per clock period
 have to worry about logic between latches (arrows) that is too
fast
R
R
Q’
R
Q’
S
S
Q
S
Q
clock
Soonhoi Ha Transparency No. 3-15
순차 회로
Master-Slave Structure
 Break flow by alternating clocks (like an air-lock)
 use positive clock to latch inputs into one R-S latch
 use negative clock to change outputs with another R-S latch
 View pair as one basic unit
 master-slave flip-flop
 twice as much logic
 output changes a few gate delays after the falling edge of
clock but does not affect any cascaded flip-flops
slave stage
master stage
R
R
Q’
S
S
Q
P’
P
R
Q’
S
Q
CLK
Soonhoi Ha Transparency No. 3-16
순차 회로
1’s Catching Problem
 In first R-S stage of master-slave FF
 0-1-0 glitch on R or S while clock is high is &quot;caught&quot; by master
stage
 leads to constraints on logic to be hazard-free
Set
S
R
CLK
P
P’
Q
Q’
R
master stage
R Q’ P’
slave stage
R Q’
S
S
S
CLK
1s
Reset catch
QP
Master
Outputs
Slave
Outputs
Soonhoi Ha Transparency No. 3-17
Q
순차 회로
D Flip Flop
 Make S and R complements of each other
 eliminates 1s catching problem
 can't just hold previous value
(must have new value ready every clock period)
 value of D just before clock goes low is what is stored in flipflop
 can make R-S flip-flop by adding logic to make D = S + R’ Q
master-slave flip-flop
slave stage
master stage
D
R
Q’
S
Q
P’
P
R
Q’
Q’
S
Q
Q
CLK
Soonhoi Ha Transparency No. 3-18
Edge-Triggered D Flip Flop
순차 회로
 More efficient solution: only 6 gates
 sensitive to inputs only near edge of clock signal (not while
high)
D’
D
0
R
holds D’ when
clock goes low
Q
Clk=1
Q’
S
0
D
D’
negative edge-triggered D
flip-flop (D-FF)
4-5 gate delays
characteristic equation
Q(t+1) = D
holds D when
clock goes low
Soonhoi Ha Transparency No. 3-19
순차 회로
Edge-triggered Flipflops
0
D
D
Clk=0
D
R
D
S
3
Q Clk=0
Q
D
D
D
4
D
D
R
S
2
D
1
0
6
Q
5
Q
D -&gt; D’
D
Negative edge-triggered FF
when clock goes high-to-low
data is latched
Negative edge-triggered FF
when clock is low
data is held
Soonhoi Ha Transparency No. 3-20
순차 회로
Latches vs Flipflops
Latches vs. Flipflops
Edge triggered device sample inputs on
the event edge
7474
D
Q
Transparent latches sample inputs
as long as the clock is asserted
Timing Diagram:
Clk
flip-flop
D
Clk
7476
D
Q
Q7474
C
Clk
Level-sensitive
latch
Q7476
Behavior the same unless input changes
while the clock is high
Soonhoi Ha Transparency No. 3-21
순차 회로
Setup Time / Hold Time
 Definition of Terms
Input
Tsu Th
Clock
There is a timing
&quot;window&quot; around the
clocking event
during which the input
must remain stable
and unchanged
in order
to be recognized
Clock:
Periodic Event, causes state of
memory element to change
rising edge, falling edge, high level, low level
Setup Time (Tsu)
Minimum time before the clocking event
by which the input must be stable
Hold Time (Th)
Minimum time after the clocking event
during which the input must remain
stable
Soonhoi Ha Transparency No. 3-22
순차 회로
Setup Time / Hold Time
Typical Timing Specifications
374 Positive Edge Triggered D Flipflop
D
Clk
Q
T
T
su h
1.8 0.5
ns ns
T
w
3.3
ns
T
pd
3.6 ns
1.1 ns
T
T
su h
1.8 0.5
ns ns
T
w
3.3
ns
T
pd
3.6 ns
1.1 ns
all measurements are made from the clocking event
(the rising edge of the clock)
Soonhoi Ha Transparency No. 3-23
순차 회로
Setup Time / Hold Time
Typical Timing Specifications
373 Transparent Latch
D
- Setup time
- Hold time
- Minimum Clock Width
- Propagation Delays:
high to low, low to high,
maximum, typical
data to output
clock to output
Clk
Q
Tsu Th
0.5 1.2
Tw
Tsu Th
0.5 1.2ns
3.3
Tplh
Tphl
3.3
1.0 ns C-&gt;Q
3.3
1.0ns
Tplh
3.6 ns
1.0 ns
Tphl
3.6 ns
1.0 ns
Measurements from falling clock edge
or rising or falling data edge
Soonhoi Ha Transparency No. 3-24
D-&gt;Q
Latches vs Flipflops
Type
unclocked
latch
level
sensitive
latch
When Inputs are Sampled
always
clock high
(Tsu, Th around
falling clock edge)
순차 회로
When Outputs are Valid
propagation delay from
input change
propagation delay from
input change
positive edge
flipflop
clock lo-to-hi transition
(Tsu, Th around
rising clock edge)
propagation delay from
rising edge of clock
negative edge
flipflop
clock hi-to-lo transition
(Tsu, Th around
falling clock edge)
propagation delay from
falling edge of clock
master/slave
flipflop
clock hi-to-lo transition
(Tsu, Th around
falling clock edge)
propagation delay from
falling edge of clock
Soonhoi Ha Transparency No. 3-25
Toggle Flipflop (T-FF)
순차 회로
Toggle Flipflop (T-FF)
Formed from J-K with both inputs wired together
Soonhoi Ha Transparency No. 3-26
Summary of latches and flip-flops
순차 회로
 Development of D-FF
 level-sensitive used in custom integrated circuits
 can be made with 4 switches
 edge-triggered used in programmable logic devices
 good choice for data storage register
 Historically J-K FF was popular but now never used
 similar to R-S but with 1-1 being used to toggle output
(complement state)
 good in days of TTL/SSI (more complex input function: D = J
Q’ + K’ Q
 not a good choice for PALs/PLAs as it requires 2 inputs
 can always be implemented using D-FF
 Preset and clear inputs are highly desirable on flipflops
 used at start-up or to reset system to a known state
Soonhoi Ha Transparency No. 3-27
순차 회로
Flip-flop features
 Reset (set state to 0) – R
 synchronous: Dnew = R' • Dold (when next clock edge arrives)
 asynchronous: doesn't wait for clock, quick but dangerous
 Preset or set (set state to 1) – S (or sometimes P)
 synchronous: Dnew = Dold + S (when next clock edge arrives)
 asynchronous: doesn't wait for clock, quick but dangerous
 Both reset and preset
 Dnew = R' • Dold + S
 Dnew = R' • Dold + R'S
(set-dominant)
(reset-dominant)
 Selective input capability (input enable or load) – LD or
EN
 multiplexor at input: Dnew = LD' • Q + LD • Dold
 load may or may not override reset/set (usually R/S have priority)
 Complementary outputs – Q and Q'
Soonhoi Ha Transparency No. 3-28
순차 회로
Realizing Circuits with Different Kinds of Flipflops
Characteristic Equations
Derived from the K-maps
R-S: Q+ = S + R Q
for Q+ = F(Inputs, Q)
D:
Q+ = D
J-K: Q+ = J Q + K Q
T:
Q+ = T Q + T Q
Implementing One FF in Terms of Another
D
J Q
C
K Q
Q
K
D Q
J
D implemented with J-K
C Q
J-K implemented with D
Soonhoi Ha Transparency No. 3-29
순차 회로
Realizing Circuits with Different Kinds of Flipflops
Design Procedure
Excitation Tables: What are the necessary inputs to cause a
particular kind of change in state?
Q Q+
0 0
0 1
1 0
1 1
R S
X 0
0 1
1 0
0 X
J K
0 X
1 X
X 1
X 0
T
0
1
1
0
D
0
1
0
1
Implementing D FF with a J-K FF:
DQ
0 0
0 1
1 0
1 1
JK
0X
X1
1X
X0
D
?
J Q
C
K Q
Q
Combinational logic design problem
Input: D, Q
Output: J, K
Soonhoi Ha Transparency No. 3-30
순차 회로
Realizing Circuits with Different Kinds of Flipflops
Design Procedure
Implementing D FF with a J-K FF:
2) Create K-maps for J and K with same inputs (D, Q)
3) Fill in K-maps with appropriate values for J and K
to cause the same state changes as in the original K-map
Q
D
0
0 0
1
1
Q
J =D
1 X
X
D
D
0
0 X
1 1
J Q
C
K Q
1
X
K =D
0
Q
Soonhoi Ha Transparency No. 3-31
순차 회로
Activity
 What is “state” in a logic circuit?
 Show how an RS latch can be used as a storage
element using a state diagram.
 Show the differences between a level-sensitive latch and
an edge-triggering flip-flop. When do they behave
identically?
 Design a JK-Flip-flop with a D-flipflop
K
D Q
J
C Q
Soonhoi Ha Transparency No. 3-32
순차 회로
Realizing Circuits with Different Kinds of Flipflops
Implementing J-K FF with a D FF:
1) K-Map of Q+ = F(J, K, Q)
2,3) Revised K-map using D's excitation table
J
JK
Q
0
00 01 11
10
0
1
0
1
K
D Q
1
1
0
0
1
J
C Q
K
Q+ = D = JQ + KQ
Soonhoi Ha Transparency No. 3-33
순차 회로
Chapter Overview
[ Chapter 6 ] Sequential Logic Design
 Sequential Logic Elements
 Timing Methodologies
 Registers
 Hardware Description Languages
[ Chapter 7 ] Finite State Machines
 Counters
 Concept of Finite State Machines
 Basic FSM Design Approach
Soonhoi Ha Transparency No. 3-34
Timing Methodology
순차 회로
 Correct Timing:
(1) correct inputs, with respect to time, are provided to the FFs
- no setup time and hold time violation
(2) no FF changes more than once per clocking event
Soonhoi Ha Transparency No. 3-35
순차 회로
What is the intuitively “correct” behavior of this circuit?
IN
D Q
CQ
Q0
D Q Q1
CQ
CLK
Correct Operation assuming positive edge triggered FF
100
In
Q0
Q1
Clk
Soonhoi Ha Transparency No. 3-36
순차 회로
Why this works:
Propagation delays far exceed hold times;
Clock width constraint exceeds setup time
Assumes infinitely fast distribution of the clock
In
Q0
Q1
Tsu
1.8ns
Tsu
1.8ns
Tp
1.1-3.6ns
Tp
1.1-3.6ns
timing constraints
guarantee proper
operation of
assumes infinitely fast
distribution of the clock
CLK
Th
0.5ns
Th
0.5ns
Soonhoi Ha Transparency No. 3-37
순차 회로
Clock Skew
Effect of Skew on Cascaded Flipflops:
FF0 samples IN
In
FF1 samples Q0
100
CLK2 is a delayed
version of CLK1
Q0
Q1
Clk1
Clk2
Why occurs?
- logical clock driven from more than one physical circuit
with timing behavior
- different wire delay to different points in the circuit
Soonhoi Ha Transparency No. 3-38
순차 회로
Narror Width Clocking
Narrow Width Clocking for Systems with Latches for State
Two-sided Constraints
must be careful of very
fast signals as well as very
slow signals!
Combinational
logic
S
t
a
t
e
Clock
Clock Width &lt; fastest propagation through comb. logic
plus latch prop delay
Clock Period &gt; slowest propagation through comb. Logic
(rising edge to rising edge)
Soonhoi Ha Transparency No. 3-39
Clocking
Clocking for Systems with Flip-flops
순차 회로
State time (period)
Combinational
logic
S
t
a
t
e
CLK
Clock
Clock Period &gt; slowest propagation through comb. Logic
(rising edge to rising edge)
Clock Period &gt; FF propagation delay + Comb. Logic delay
+ FF setup time = T_p + T_delay + T_su
Soonhoi Ha Transparency No. 3-40
순차 회로
Metastability and Asynchronous Inputs
Terms and Definitions
 Clocked synchronous circuits
- common reference signal called the clock
- state of the circuit changes in relation to this clock signal
 Asynchronous circuits
- inputs, state, and outputs sampled or changed independent
of a common reference signal
R-S latch is asynchronous, J-K master/slave FF is synchronous
 Synchronous inputs
- active only when the clock edge or level is active
 Asynchronous inputs
- take effect immediately, without consideration of the clock
Soonhoi Ha Transparency No. 3-41
순차 회로
Metastability and Asynchronous Outputs
Handling Asynchronous Inputs
Clocked
Synchronous
System
Q0
Async
D
Q
Input
Synchronizer
Async
Input D Q
Clock
Clock
D Q
Q1
Clock
Q0
D Q
Q1
D Q
Clock
Never allow asynchronous inputs to be fanned out to more than
one FF within the synchronous system
Soonhoi Ha Transparency No. 3-42
순차 회로
Metastability and Asynchronous Inputs
What Can Go Wrong
Setup time violation!
In
Q0
Q1
Clk
Asynchronous input
Fans out to D0 and D1
One FF catches the
signal, one does not
impossible state might
be reached!
Single FF that receives the asynchronous signal is a
synchronizer
- shortest possible setup and hold time are desired.
Soonhoi Ha Transparency No. 3-43
순차 회로
Metastability and Asynchronous Inputs
Synchronizer Failure
In
D Q
?
When FF input changes close to clock edge,
the FF may enter the metastable state: neither
a logic 0 nor a logic 1
Logic 1
Logic 0
Time
Small, but non-zero probability
that the FF output will get stuck
in an in-between state
Oscilloscope Traces Demonstrating
Synchronizer Failure and Eventual
Soonhoi Ha Transparency No. 3-44
순차 회로
Metastability and Asynchronous Inputs
Solutions to Synchronizer Failure
- slow down the system clock
gives the synchronizer more time to decay into a steady state
synchronizer failure becomes a big problem for very high
speed systems
- use fastest possible logic in the synchronizer
Asynchronous
Input
D Q
Synchronized
Input
D Q
Clk
Synchronous System
Soonhoi Ha Transparency No. 3-45
순차 회로
Self-Timed and Speed Independent Circuits
Limits of Synchronous Systems
- Fully synchronous not possible for very large systems
because of problems of clock skew
- Partition system into components that are locally clocked
- These communicate using &quot;speed independent&quot; protocols
Communications
Signals
Clocked
Clocked
Subsystem
Subsystem
Request/Acknowledgement Signaling
Request
S2
S1
requester
client
master
Data Flow
Acknowledgement
provider
server
slave
Soonhoi Ha Transparency No. 3-46
순차 회로
Self-Timed and Speed Independent Circuits
Synchronous Signaling
Req
Data
Ack
Clk
Master issues read request; Slave produces data and acks back
Req
Data
Wait
Clk
Alternative Synchronous Scheme:
Slave issues WAIT signal if it cannot satisfy request in one
clock cycle
Soonhoi Ha Transparency No. 3-47
순차 회로
Self-Timed and Speed Independent Circuits
Asynchronous/Speed Independent Signaling
Communicate information by signal levels rather than edges!
No clock signal
Req
Data
Ack
(1) master raises request
slave performs request
(3) master latches data
acks by lowering request
(2) slave &quot;done&quot; by raising
acknowledge
(4) slave resets self by lowing
acknowledge signal
Soonhoi Ha Transparency No. 3-48
순차 회로
Self-Timed and Speed Independent Circuits
Alternative: 2 cycle signaling
Non-Return-to-Zero
Req
Data
Ac k
(1) master raises request, slave services request
(2) slave indicates that it is done by raising acknowledge
Next request indicated by low level of request
Requires additional state in master and slave
to remember previous setting or request/acknowledge
4 Cycle Signaling is more foolproof
Soonhoi Ha Transparency No. 3-49
순차 회로
Chapter Overview
[ Chapter 6 ] Sequential Logic Design
 Sequential Logic Elements
 Timing Methodologies
 Registers
 Hardware Description Languages
[ Chapter 7 ] Finite State Machines
 Counters
 Concept of Finite State Machines
 Basic FSM Design Approach
Soonhoi Ha Transparency No. 3-50
순차 회로
Register
 Register: collections of flip-flops with similar controls and
logic
 stored values somehow related (for example, form binary value)
 share clock, reset, and set lines
 similar logic at each stage
OUT1
OUT2
OUT3
OUT4
&quot;0&quot;
RS
DQ
RS
DQ
RS
DQ
RS
DQ
CLK
IN1
IN2
IN3
IN4
Soonhoi Ha Transparency No. 3-51
순차 회로
Register
Input/Output Variations
Tri-state or Open Collector Outputs
377
11 CLK
1 EN
18 D7
17 D6
14 D5
13 D4
8 D3
7 D2
4 D1
3 D0
Q7 19
Q6 16
Q5 15
Q4 12
Q3 9
Q2 6
Q1 5
Q0 2
74377 Octal D-type FFs
with input enable
374
11 CLK
18H QH 19
17G QG 16
14 F QF 15
13E QE 12
8 D QD 9
7 C QC 6
4 B QB 5
3 A QA 2
OE
1
74374 Octal D-type FFs
with output enable
Soonhoi Ha Transparency No. 3-52
순차 회로
Shift Register
Shift Registers
Storage + ability to circulate data among storage elements
OUT1
IN
DQ
OUT2
DQ
OUT3
DQ
OUT4
DQ
CLK
Shift from left storage
element to right neighbor
on every lo-to-hi transition
on shift signal
Shift
Shift
Shift
Q
1
1
Q
2
0
Q
3
0
Q
4
0
0
1
0
0
0
0
1
0
0
0
0
1
Soonhoi Ha Transparency No. 3-53
순차 회로
Universal Shift Register
 Holds 4 values
 serial or parallel inputs
 serial or parallel outputs
 permits shift left or right
 shift in new values from left or right
output
left_in
left_out
clear
s0
s1
right_out
right_in
clock
s0
0
0
1
1
s1
0
1
0
1
function
hold state
shift right
shift left
input
Soonhoi Ha Transparency No. 3-54
순차 회로
Design of Universal Shift Register
 Consider one of the four flip-flops
 new value at next clock cycle:
clear
1
0
0
0
0
s0
–
0
0
1
1
s1
–
0
1
0
1
new value
0
output
output value of FF to left (shift right)
output value of FF to right (shift left)
input
Nth cell
to N-1th
cell
to N+1th
cell
Q
D
CLK
CLEAR
0 1 2 3 s0 and s1
control mux
Q[N-1]
(left)
Input[N]
Q[N+1]
(right)
Soonhoi Ha Transparency No. 3-55
순차 회로
Shift register application
 Parallel-to-serial conversion for serial transmission
parallel outputs
parallel inputs
serial transmission
Soonhoi Ha Transparency No. 3-56
순차 회로
Pattern recognizer
 Combinational function of input samples
 in this case, recognizing the pattern 1001 on the single input signal
OUT
OUT1
IN
CLK
DQ
DQ
OUT2
DQ
OUT3
OUT4
DQ
Soonhoi Ha Transparency No. 3-57
순차 회로
Parallel To Serial Conversion
Parallel
Inputs
Sender
S1194
S0
LSI
D7
D QD
D6
C QC
D5
B QB
D4
A QA
ClockRSI
CLK
CLR
D3
D2
D1
D0
S1194
S0
LSI
D QD
C QC
B QB
A QA
RSI
CLK
CLR
S1
S0 194
LSI
D QD D7
C QC D6
B QB D5
A QA D4
RSI
CLK
CLR
S1
S0194
LSI
D QD
C QC
B QB
A QA
RSI
CLK
CLR
Parallel
Outputs
D3
D2
D1
D0
Serial transmission
Soonhoi Ha Transparency No. 3-58
순차 회로
Review
 Design a 3 bit shift register with the following
capabilities.
(2) shift left and shift right capability
 Name some applications of shift register.
 What is the difference between synchronous clear and
asynchronous clear?
Soonhoi Ha Transparency No. 3-59
순차 회로
Chapter Overview
[ Chapter 6 ] Sequential Logic Design
 Sequential Logic Elements
 Timing Methodologies
 Registers
 Hardware Description Languages
[ Chapter 7 ] Finite State Machines
 Counters
 Concept of Finite State Machines
 Basic FSM Design Approach
Soonhoi Ha Transparency No. 3-60
순차 회로
R-S Latch
module rs_latch(r, s, q);
input r, s;
output q;
wire
qbar;
R
Q
nor_gate nor1(s, q, qbar);
S
Q'
nor_gate nor2(r, qbar, q);
endmodule
Soonhoi Ha Transparency No. 3-61
D Flip-Flop
순차 회로
module dff (clk, d, q);
input clk, d;
output q;
reg
q;
always @(posedge clk)
q = d;
endmodule
Positive edge-triggering
Compare with @(clk)
Soonhoi Ha Transparency No. 3-62
순차 회로
D Flip-Flop with Set/Reset input
Synchronous: module dff_sync_rs (clk, r, s, d, q);
input clk, r, s, d;
output q;
reg q;
always @(posedge clk)
if ( r )
q = 1’b0;
else if (s)
q = 1’b1;
else
q = d;
endmodule
Asynchronous: module dff_async_rs (clk, r, s, d, q);
input clk, r, s, d;
output q;
reg q;
always @(posedge r)
q = 1’b0;
always @(posedge s)
q = 1’b1;
always @(posedge clk)
q = d;
endmodule
Soonhoi Ha Transparency No. 3-63
순차 회로
Shift Register
Sequential
or blocking
assignment
module shift4bit (clk,in,out1,out2,out3,out4);
input clk, in;
output out1, out2, out3, out4;
reg out1, out2, out3, out4;
always @(posedge clk)begin
out4 = out3;
out3 = out2;
out2 = out1;
out1 = in;
end
endmodule
module shift4bit (clk,in,out1,out2,out3,out4);
Delayed or
Nonblocking
assignment
input clk, in;
output out1, out2, out3, out4;
reg out1, out2, out3, out4;
always @(posedge clk)begin
out1 &lt;= in;
out2
&lt;= out1;
{out1,out2,out3,out4}
out3
out2;
&lt;=
{in1,&lt;=out1,
out2, out3}
out4 &lt;= out3;
end
Takes effects at the end of the
endmodule
always block
Soonhoi Ha Transparency No. 3-64
순차 회로
Register File (Fig. 6.50)
module register_file_32_by_8 (we, re, abus, dbus, obus)
parameter mem_size = 32;
parameter data_bus_width = 8;
input we, re;
input [data_bus_width-1 : 0] dbus;
output [data_bus_width-1 : 0] obus;
reg [data_bus_width-1 : 0] obus;
reg [data_bus_width-1 : 0] out;
reg [data_bus_width-1 : 0] regfile [mem_size-1:0];
always @(posedge we) begin
regfile[abus] = dbus;
always @(posedge re) begin
out = regfile[abus];
assign obus = (re) ? Out : 8’bZZZZZZZZ;
endmodule
Soonhoi Ha Transparency No. 3-65
Summary
순차 회로
 Fundamental building block of circuits with state
 latch and flip-flop
 R-S latch, R-S master/slave, D master/slave, edge-triggered D flipflop
 Timing methodologies
 use of clocks
 cascaded FFs work because propagation delays exceed hold times
 beware of clock skew
Asynchronous inputs and their dangers
 synchronizer failure: what it is and how to minimize its impact
 Handshaking protocol
Basic registers
 shift registers
 Hardware description languages and sequential logic
Soonhoi Ha Transparency No. 3-66
Homework
순차 회로
 Exercises (Chapter 6)
- 1, 10, 11, 15, 19
 Due Date: one week after
Soonhoi Ha Transparency No. 3-67
순차 회로
Chapter Overview
[ Chapter 6 ] Sequential Logic Design
 Sequential Logic Elements
 Timing Methodologies
 Registers
 Hardware Description Languages
[ Chapter 7 ] Finite State Machines
 Counters
 Concept of Finite State Machines
 Basic FSM Design Approach
Soonhoi Ha Transparency No. 3-68
순차 회로
Counters
Proceed through a well-defined sequence of states in
response to count signal
3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
Binary vs. BCD vs. Gray Code Counters
A counter is a &quot;degenerate&quot; finite state machine /
sequential circuit where the state is the only output
Soonhoi Ha Transparency No. 3-69
순차 회로
Ring Counter
Counting patterns: 1000, 0100, 0010, 0001
if one of the patterns is its initial state (by loading or set/reset)
OUT1
IN
DQ
DQ
OUT2
DQ
OUT3
OUT4
DQ
CLK
Soonhoi Ha Transparency No. 3-70
순차 회로
Johnson Counter
What is the counting pattern?
OUT1
IN
D Q
DQ
OUT2
D Q
OUT3
OUT4
DQ
CLK
Soonhoi Ha Transparency No. 3-71
순차 회로
Counter Design Procedure
Introduction
Can be generalized to implement ANY finite state machine
Counters are a very simple way to start: no decisions on
what state to advance to next
current state is the output
Example: 3-bit Binary Upcounter
&lt; State transition diagram &gt;
000
111
001
110
010
101
011
100
present state
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
next state
001 1
010 2
011 3
100 4
101 5
110 6
111 7
000 0
Soonhoi Ha Transparency No. 3-72
순차 회로
Implementation
D flip-flop for each state bit
Combinational logic based on encoding
C3
0
0
0
0
1
1
1
1
C2
0
0
1
1
0
0
1
1
N3
C1
0
1
0
1
0
1
0
1
C3
N3
0
0
0
1
1
1
1
0
N2
0
1
1
0
0
1
1
0
N1
1
0
1
0
1
0
1
0
N1 &lt;=
N2 &lt;=
&lt;=
N3 &lt;=
&lt;=
&lt;=
&lt;=
N2
C3
C1’
C1C2’ + C1’C2
C1 xor C2
C1C2C3’ + C1’C3 + C2’C3
(C1C2)C3’ + (C1’ + C2’)C3
(C1C2)C3’ + (C1C2)’C3
(C1C2) xor C3
N1
C3
0
0
1
1
0
1
1
0
1
1
1
1
C1 0
1
0
1
C1 1
0
0
1
C1 0
0
0
0
C2
C2
C2
Soonhoi Ha Transparency No. 3-73
순차 회로
Implementation
OUT1
D Q
OUT2
D Q
OUT3
D Q
CLK
&quot;1&quot;
Soonhoi Ha Transparency No. 3-74
Implementation
&lt; State transition diagram &gt;
000
111
001
110
010
101
011
100
순차 회로
&lt; State transition table &gt;
Present Next Flip-flop
state
state
input
000 001 001
001 010 011
010 011 001
011 100 111
100 101 001
101 110 011
110 111 001
111 000 111
T-FF
사용
Soonhoi Ha Transparency No. 3-75
순차 회로
Implementation
Example Continued
K-maps for Toggle
Inputs:
CB
A 00 01 11 10
0 1 1 1 1
1 1 1 1 1
Resulting Logic Circuit:
+
TA = 1
CB
A 00 01 11 10
0 0 0 0 0
1 1 1 1 1
TB = A
\Reset
TSQ QA T SQ QB
/Q
/Q
R
R
T SQ QC
/Q
R
Count
CB
A 00 01 11 10
0 0 0 0 0
1 0 1 1 0
TC = AB
Soonhoi Ha Transparency No. 3-76
Counter Design Procedure
More Complex Count Sequence
순차 회로
 Step 1: Derive the State Transition Diagram
Count sequence: 000, 010, 011, 101, 110
Present
state
000
001
010
011
100
101
110
111
Next
state
010
XXX
011
101
XXX
110
000
XXX
000
110
010
101
011
 Step 2: State Transition Table
Note: don’t care condition
Soonhoi Ha Transparency No. 3-77
순차 회로
Counter Design Procedure
More Complex Count Sequence
 Step 3: K-Maps for Next State Functions
CB
A 00 01 11 10
0 0 0 0 X
1 X 1 X 1
CB
A 00 01 11 10
0 1 1 0 X
1 X 0 X 1
C+ = A
B+ = B’ + A’C’
CB
A 00 01 11 10
0 0 1 0 X
1 X 1 X 0
A+ = C’B
Soonhoi Ha Transparency No. 3-78
순차 회로
Implementation with D-FF
DC = A
DB = A C + B
DA = B C
A
D Q C DB D Q B
Q \C
Q \B
Count
\C
\A
DB
\B
B
\C
DA
D Q A
Q \A
DA
Resulting Logic Level Implementation:
3 Gates, 8 Input Literals + Flipflop connections
Soonhoi Ha Transparency No. 3-79
순차 회로
Self-Starting Counters
Re-deriving state transition table from don't care assignment
C+
A
C
B+
0
0
0
0
1
1
1
1
A
B
Present
C B A
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A+
C
1
1
0
1
1
0
0
1
A
C
0
1
0
0
0
1
0
0
B
Next State
C+ B+ A+
0 1 0
1 1 0
0 1 1
1 0 1
0 1 0
1 1 0
0 0 0
1 0 0
B
001
111
000
110
100
010
101
011
Soonhoi Ha Transparency No. 3-80
순차 회로
Self-Starting Counters
 Start-up states
 at power-up, counter may be in an unused or invalid state
 designer must guarantee that it (eventually) enters a valid
state
 Self-starting solution
 design counter so that invalid states eventually transition to
a valid state
 may limit exploitation of don't cares
111
111
001
100
000
110
010
100
101
011
implementation
on previous slide
000
110
010
101
011
Soonhoi Ha Transparency No. 3-81
001
Catalog Counter
7 P
10 T 163
2 CLKRCO 15
6 D
QD 11
5 C
QC 12
4 B
QB 13
3 A
QA 14
1 CLR
74163 Synchronous
4-Bit Upcounter
순차 회로
Positive Edge Triggered FFs
Parallel Load Data from D, C, B, A
P, T Enable Inputs: both must be
asserted to enable counting
RCO: asserted when counter enters its
highest state 1111, used for
&quot;Ripple Carry Output&quot;
74161: similar in function, asynchronous load and reset
Soonhoi Ha Transparency No. 3-82
순차 회로
Catalog Counter
74163 Detailed Timing Diagram
CLR
A
B
C
D
CLK
P
T
QA
QB
QC
QD
RCO
12 13 14 15 0
Count
1
2
Inhibit
Soonhoi Ha Transparency No. 3-83
순차 회로
Cascaded Synchronous Counters with Ripple Carry Outputs
P
T
RCO
D
C
B
A
QD
QC
QB
QA
D
C
163
B
A
CLK
H
G
F
E
P
T
RCO
RCO
D
C
B
A
QD
QC
QB
QA
E
ABCD = 1111
163
Soonhoi Ha Transparency No. 3-84
순차 회로
Synchronous Counters
The Power of Synchronous Clear and Load
Starting Offset Counters:
e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...
100
Clock
D
C
B
A
Use RCO signal to trigger Load
RCO
LD
DCBA
0110
state changes only on the next
rising clock edge
Soonhoi Ha Transparency No. 3-85
순차 회로
Synchronous Counters
Offset Counters Continued
Ending Offset Counter:
e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000
D
C
QD QC QB QA
B
A
CLR
CLR
Decode state to
determine when to
reset to 0000
Asynchronous case
Soonhoi Ha Transparency No. 3-86
순차 회로
Asynchronous vs. Synchronous Counters
Ripple Counters
Deceptively attractive alternative to synchronous design style
State transitions are not sharp!
Can lead to &quot;spiked outputs&quot; from combinational logic
decoding the counter's state
Soonhoi Ha Transparency No. 3-87
Counter Design
순차 회로
 Design a counter repeating the following sequence:
000, 001, 011, 101, 110
 Is the counter design above self-starting?
Soonhoi Ha Transparency No. 3-88
순차 회로
Chapter Overview
[ Chapter 6 ] Sequential Logic Design
 Sequential Logic Elements
 Timing Methodologies
 Registers
 Hardware Description Languages
[ Chapter 7 ] Finite State Machines
 Counters
 Concept of Finite State Machines
 Basic FSM Design Approach
Soonhoi Ha Transparency No. 3-89
순차 회로
Concept of the State Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Present State
Even
Even
Odd
0
Odd
Res et
Even
[0]
Input
0
1
0
1
Next State Output
Even
0
Odd
0
Odd
1
Even
1
Symbolic State Transition Table
1
0
1
Odd
[1]
State
Diagram
Present State Input Next State Output
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
1
Encoded State Transition Table
Soonhoi Ha Transparency No. 3-90
순차 회로
Concept of the State Machine
Example: Odd Parity Checker
Next State/Output Functions: NS = PS xor PI; OUT = PS
Inp ut
NS
Input
CLK
D Q
PS/Output
RQ
\Reset
D FF Implementation
T
Q
Outpu t
CLK
R
Q
\Rese t
T FF Implementation
State Diagram -&gt; State Transition Table -&gt;
Next-State and Output Functions -&gt; Implementation
Soonhoi Ha Transparency No. 3-91
순차 회로
Back to Shift Register
In
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
N1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
N2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
N3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
100
1
0
000
0
1
0
010
1
001
1
0
110
1
101
0
0
1
111 1
0
1
011
0
N1 &lt;= In
N2 &lt;= C1
N3 &lt;= C2
OUT1
IN
DQ
DQ
OUT2
OUT3
DQ
CLK
Soonhoi Ha Transparency No. 3-92
순차 회로
Basic Design Approach
Five Step Process
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state mininimization
4. Perform state assignment
5. Implement the FSM
Soonhoi Ha Transparency No. 3-93
순차 회로
Vending Machine Example
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes (10 cents), nickels (cents)
no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram
N
Coin
Sensor
D
Reset
Vending
Machine
FSM
Open
Gum
Release
Mechanism
Clk
Soonhoi Ha Transparency No. 3-94
순차 회로
Vending Machine Example
Step 2. Map into more suitable abstract representation
Draw state diagram:
Reset
Inputs: N, D, reset
Output: open
S0
N
S1
N
S4
[open]
S3
N
S7
[open]
D
D
S2
N
S5
[open]
D
S6
[open]
D
S8
[open]
Soonhoi Ha Transparency No. 3-95
순차 회로
Vending Machine Example
Step 3: State Minimization
Reset
Present
State
0&cent;
0&cent;
N
5&cent;
D
5&cent;
N
10&cent;
10&cent;
D
N, D
15&cent;
[open]
reuse states
whenever
possible
15&cent;
Inputs
D N
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
X X
Next
State
0&cent;
5&cent;
10&cent;
X
5&cent;
10&cent;
15&cent;
X
10&cent;
15&cent;
15&cent;
X
15&cent;
Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1
Symbolic State Table
Soonhoi Ha Transparency No. 3-96
순차 회로
Vending Machine Example
Step 4: State Encoding
Present State Inputs
Q Q
D N
1 0
0 0
0
0
0
1
1
0
1
1
0 1
0
0
0
1
1
0
1
1
0
0
1 0
0
1
1
0
1
1
0
0
1 1
0
1
1
0
1
1
Next State
D D
1
0
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
Soonhoi Ha Transparency No. 3-97
순차 회로
Vending Machine Example
Step 5. Implementation
D FF easiest to use
Q1Q0
Q1Q0
00 01 11 10 DN
00 01 11 10
DN
1
1 1
X X X
1 1 1
1
1
X
1
D1
0
1
X
0
1
0
X
1
1
1
X
1
0
1
X
1
Q1Q0
00 01 11 10
DN
1
1
X X X X
1
D0
Output
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates
Soonhoi Ha Transparency No. 3-98
Moore Machine vs Mealy Machine
순차 회로
 Moore Machine
- Outputs are function
solely of the current
state
- Outputs change
synchronously with
state changes
Inputs
output
logic
next state
logic
Outputs
Next State
Current State
State
Register
Xi
Inputs
Output
Logic
Next State
Logic
Zk
Outputs
Clock
Soonhoi Ha Transparency No. 3-99
Moore Machine vs Mealy Machine
 Mealy Machine
Inputs
- Outputs depend on
state AND inputs
- Input change causes
an immediate output
change
- Asynchronous signals
Xi
Inputs
Output
and
Next state
Logic
State RegisterClock
output
logic
next state
logic
순차 회로
Outputs
Next State
Current State
Zk
Outputs
State
Feedback
Soonhoi Ha Transparency No. 3-100
순차 회로
Moore and Mealy Machines
State Diagram Equivalents
N D + Reset
Moore
Machine Reset
ND
[0]
N
5&cent;
[0]
N
10&cent;
[0]
N+D
15&cent;
[1]
0&cent;
Reset/0
0&cent;
Reset
D
(N D + Reset)/0
Reset/0
D
N/0
5&cent;
N D/0
Mealy
Machine
D/0
N/0
10&cent;
ND
D/1
N+D/1
15&cent;
Reset
Outputs are associated
with State
N D/0
Reset/1
Outputs are associated
with Transitions
Soonhoi Ha Transparency No. 3-101
순차 회로
Moore and Mealy Machines
Converting between Moore and Mealy Machines
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
0
0
0
[0]
1
1
[0]
0
0
1/0
0/0
1
1/1
1
2
[1]
0/0
1
0
0
[0]
1
1
[0]
0
1
2
[1]
1
Soonhoi Ha Transparency No. 3-102
Comparison of Two Machine Types
순차 회로
 Mealy machines tend to have less states
 different outputs on arcs (n2) rather than states (n)
 Moore machines are safer to use
 outputs change at clock edge (always one cycle later)
 in Mealy machines, input change can cause output change as
soon as logic is done – a big problem when two machines are
interconnected – asynchronous feedback may occur if one isn’t
careful
 Mealy machines react faster to inputs
 react in same cycle – don't need to wait for clock
 in Moore machines, more logic may be necessary to decode
state into outputs – more gate delays after clock edge
Soonhoi Ha Transparency No. 3-103
순차 회로
Complexity Comparison of Two Machine Types
 Assumption
 M inputs, N outputs, L FFs
 Minimum/maximum number of state transitions from a
given state
 They are the same: 2^M transitions
Minimum/maximum number of state transitions to a given
state
 Minimum = 0;
 Maximum = 2^M * 2^L
 Min./Max. number of output patterns
 Min. = 1
 Max. (Mealy) = min {2^M * 2^L, 2^N}
(Moore) = min {2^L, 2^N}
Soonhoi Ha Transparency No. 3-104
순차 회로
Moore and Mealy Machines
Reverse engineer the following:
X
X
\B
J Q
C
KR Q
FFa \Reset
A
\A
Input X
Output Z
State A, B = Z
Clk
X
X
\A
J Q
C
KR Q
FFb \Reset
Z
\B
Soonhoi Ha Transparency No. 3-105
순차 회로
Moore and Mealy Machines
Formal Reverse Engineering
Derive transition table from next state and output combinational
functions presented to the flipflops!
Ja = X
Jb = X
Z=B
Ka = XB
Kb = X xor A
FF excitation equations for J-K flipflop:
A+ = Ja  A + Ka  A = X  A + (X + B)  A
B+ = Jb  B + Kb  B = X  B + (X  A + X  A)  B
Soonhoi Ha Transparency No. 3-106
순차 회로
Moore and Mealy Machines
Synchronous Mealy Machine
Clock
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
State Register
latched state AND outputs
avoids glitchy outputs!
Clock
state
feedback
Moore Machine
Soonhoi Ha Transparency No. 3-107
순차 회로
Moore Implementation of Vending Machine
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
Soonhoi Ha Transparency No. 3-108
순차 회로
Mealy Implementation of Vending Machine
Reset/0
Reset/0
0&cent;
N’ D’/0
N/0
D/0
5&cent;
N’ D’/0
N/0
10&cent;
D/1
N+D/1
15&cent;
N’ D’/0
Reset’/1
present state inputs
Q1 Q0
D N
0 0
0 0
0 1
1 0
1 1
0 1
0 0
0 1
1 0
1 1
1 0
0 0
0 1
1 0
1 1
1 1
– –
next
D1
0
0
1
–
0
1
1
–
1
1
1
–
1
state
D0
0
1
0
–
1
0
1
–
0
1
1
–
1
output
open
0
0
0
–
0
0
1
–
0
1
1
–
1
D0
= Q0’N + Q0N’ + Q1N + Q1D
D1
= Q1 + D + Q0N
OPEN = Q1Q0 + Q1N + Q1D + Q0D
Soonhoi Ha Transparency No. 3-109
순차 회로
Mealy Implementation of Vending Machine
make sure OPEN is 0 when reset
D0
= Q0’N + Q0N’ + Q1N + Q1D
D1
= Q1 + D + Q0N
OPEN = Q1Q0 + Q1N + Q1D + Q0D
Soonhoi Ha Transparency No. 3-110
Retimed Moore Machine
순차 회로
OPEN = Q1Q0 creates a
combinational delay after Q1 and
Q0 change in Moore
implementation.
Retiming moves flip-flops and
logic through each other to
improve delay
Soonhoi Ha Transparency No. 3-111
Synchronous Mealy Machine
순차 회로
DQ
C
Soonhoi Ha Transparency No. 3-112
순차 회로
Activity
 Draw the state diagram of a FSM asserting output = 1
when two consecutive inputs have the same value (0 or 1).
 What is the key difference between Moore and Mealy
FSMs?
 Draw the state diagram of the following logic. What kind
of FSM is it? Convert it to another type of FSM.
X
X
\B
J Q
C
KR Q
FFa \Reset
A
\A
Clk
X
X
\A
J Q
C
KR Q
FFb \Reset
Z
\B
Soonhoi Ha Transparency No. 3-113
순차 회로
Motivation for Optimization
State Reduction
0
0
S0
[0]
S0
[0]
1
0
1
S1
[1]
1
S1
[1]
1
1
S2
[0]
0
0
Odd Parity Checker: two alternative state diagrams
- Identical output behavior on all input strings
- FSMs are equivalent, but require different implementations
- Design state diagram without concern for # of states,
Reduce later
Soonhoi Ha Transparency No. 3-114
Traffic Light Controller Example
순차 회로
A busy highway is intersected by a little used farmroad.
With no car on farm road, light remain green in highway
direction.
If vehicle on farmroad, highway lights go from Green to
Yellow to Red, allowing the farmroad lights to become
green. These stay green only as long as a farmroad car is
detected but never longer than a set interval.
Even if farmroad vehicles are waiting, highway gets at least
a set interval as green.
Assume you have an interval timer that generates a short
time pulse (TS) and a long time pulse (TL) in response to
a set (ST) signal. TS is to be used for timing yellow lights
and TL for green lights.
Soonhoi Ha Transparency No. 3-115
순차 회로
Traffic Light Controller Example
C
HL
FL
Highway
Highway
HL
FL
C
Soonhoi Ha Transparency No. 3-116
Traffic Light Controller Example
순차 회로
 Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL
Description
place FSM in initial state
short time interval expired
long time interval expired
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
assert green/yellow/red highway lights
start timing a short or long interval
 Tabulation of Unique States: Some light configuration
imply others
State
S0
S1
S2
S3
Description
Soonhoi Ha Transparency No. 3-117
순차 회로
Traffic Light Controller
TL + C
Reset
S0: HG
S0
TL•C/ST
S1: HY
TS/ST
TS
S1
S2: FG
S3
TS
TS/ST
S2
S3: FY
TL + C/ST
TL • C
Soonhoi Ha Transparency No. 3-118
Encoding Possibilities
순차 회로
State assignment: HG, HY, FY, FG
 Binary Encoding
 00, 01, 10, 11
 One-hot encoding
 1000, 0100, 0010, 0001
 Yet another possibility: identical to the output
 001100, 010100, 100010, 100001
Soonhoi Ha Transparency No. 3-119
순차 회로
Summary
 Models for representing sequential circuits
 abstraction of sequential elements
 finite state machines and their state diagrams
 inputs/outputs
 Mealy, Moore, and synchronous Mealy machines
 Finite state machine design procedure
 deriving state diagram
 deriving state transition table
 determining next state and output functions
 implementing combinational logic
Soonhoi Ha Transparency No. 3-120
Homework
순차 회로
 Exercises (Chapter 7)
- 2, 12, 15, 19, 21, 24
 Due Date: one week after
Soonhoi Ha Transparency No. 3-121
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