Multiple Valued Logic • Currently Studied for Logic Circuits with More Than 2 Logic States – Intel Flash Memory – Multiple Floating Gate Charge Levels – 2,3 bits per Transistor http://www.ee.pdx.edu/~mperkows/ISMVL/flash.html • Techniques for Manipulation Applied to Multioutput Functions – Characteristic Equation – Positional Cube Notation (PCN) Extensions MVI Functions • Each Input can have Value in Set {0, 1, 2, ..., pi-1} F :{0,1,..., pi 1} {0,1, X } • MVI Functions • X is p-valued variable • literal over X corresponds to subset of values of S {0, 1, ... , p-1} denoted by XS MVL Literals • Each Variable can have Value in Set {0, 1, 2, ..., pi-1} • X is a p-valued variable • MVL Literal is Denoted as X{j} Where j is the Logic Value • Empty Literal: X{} • Full Literal has Values S={0, 1, 2, …, p-1} X{0,1,…,p-1} Equivalent to Don’t Care MVL Example • MVI Function with 2 Inputs X, Y – X is binary valued {0, 1} – Y is ternary valued {0, 1, 2} – n=2 pX=2 pY=3 • Function is TRUE if: – – – – X=1 and Y= 0 or 1 Y=2 SOP form is: F = X{1}Y{0,1} + X{0,1}Y{2} • Literal X{0,1} F is Full, So it is Don’t Care – implicant is – minterm is X {1}Y{0} – prime implicants are X{1} and Y{2} X{1} Y{0,1} Y X 0 1 0 1 1 1 2 1 1 Multi-output Binary Function • Consider f 0 ( x, y , z ) x z x y x z x y z f1 ( x, y, z) z x y x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 f0 1 1 1 0 0 1 0 1 f1 0 1 1 1 0 1 0 1 f0 f1 Multi-output Binary Function • Consider f 0 ( x, y, z ) x z x y x z f1 ( x, y, z) z x y x y z f0 f1 x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 f0 1 1 1 0 0 1 0 1 f1 0 1 1 1 0 1 0 1 Characteristic Equation W x y z F x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 1 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 Characteristic Equation Sum of Minterms F x{0} y{0} z{0}W {0} x{0} y{0} z{1}W {0} x{0} y{0} z{1}W {1} x{0} y{1} z{0}W {0} x{0} y{1} z{0}W {1} x{0} y{1} z{1}W {1} x{1} y{0} z{1}W {0} x{1} y{0} z{1}W {1} x{1} y{1} z{1}W {0} x{1} y{1} z{1}W {1} x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 1 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 PCN for MVL Functions • Binary Variables, {0,1}, Represented by 2-bit Fields 00 0 10 1 01 * 11 • MV Variables, {0,1,…,p-1}, Represented by p-bit Fields • BV Don’t Care is 11 • MV Don’t Care is 111…1 • MV Literal or Cube is Denoted by C() PCN for MVL Example F X {1}Y {0,1} X {0,1}Y {2} X 01 11 Y 110 001 • Positional Cube Corresponding to X{1} is C(X{1}) C ( X ) 01 111 {1} • Since Y{0,1,2} is Don’t Care PCN for MVI-BO Example z f1 ab ab f 2 ab f 3 ab ab f (a, b); f ( f1 , f 2 , f 3 ) a b f1 f2 f3 a b 10 10 100 a b 10 01 001 a b 01 10 001 ab 01 01 110 • View This as a SOP of MVI Function: F f a{0}b{0} z{0} a{0}b{1} z{2} a{1}b{0} z{2} a{1}b{1} z{0,1} • F is the Characteristic Equation List Oriented Manipulation • Size of Literal = Cardinality of Logic Value Set x{0,2} size = 2 • Size of Implicant (Cube, Product Term) = Integer Product of Sizes of Literals in Cube • Size of Binary Minterm = 1 Implicant of Unit Size EXAMPLE f (x1,x2,x3,x4,x5,x6) implicant x1 x3 x4 x1{1} x3{1} x4{0} x2{0,1} x5{0,1} x6{0,1} size 111 2 2 2 01 01 10 11 11 11 8 # Don ' t Cares 3 ( x2 , x5 , x6 ) Logic Operations • Consider Implicants as Sets – Apply (, , , etc) • Apply Bitwise Product, Sum, Complement to PCN Representation • Bitwise Operations on Positional Cubes May Have Different Meaning than Corresponding Set Operations EXAMPLE Complement of Implicant Complement of Positional Cube MVL Logical Operations • AND Operation – MIN - Set Intersection • OR Operation – MAX - Set Union • NOT Operation – Set Complement EXAMPLE X {0,1,3}Y {1,2} X {1}Y {2} X {1}Y {2} X {0,1,3}Y {1,2} X {1}Y {2,3} X {0,1,3}Y {1,2,3} p 5; X {0,1,3} X {2,4} MVL Number of Functions of 1 Variable p 2 3 4 5 6 7 8 p p 4 27 256 3125 46656 823543 16777216 MVL Circuits MAX-gate MIN-gate Cube Merging • Basic Operation – OR of Two Cubes • MVL Operation – MAX is Union of Two Cubes EXAMPLE = 1 {0,1} 0 1 = 0 {0,1} 0 1 Merge and into = {0,1} {0,1}0 1 a c d ac d c d (a a )c d a{1}b{0,1}c{0}d {1} a{0}b{0,1}c{0}d {1} (b c d )(a a ) {0,1} {0} {1} {1} a{0,1}b{0,1}c{0}d {1} {0} Multi-Output Minimization Example X1 0 0 0 0 1 1 1 1 Input X2 0 0 1 1 0 0 1 1 X3 0 1 0 1 0 1 0 1 Output f0 f1 f2 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 X1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 X2 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 X3 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 X4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 F 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 Minimization Example (cont) Sum of Minterms (Fig. 10.7 PLA Implementation) F X1 X 2 X 3 X 4 X1 X 2 X 3 X 4 {0} {0} {0} {1} {0} {0} {0} {2} X1 X 2 X 3 X 4 {2} X1 X 2 X 3 X 4 X1 X 2 X 3 X 4 {0} X1 X 2 X 3 X 4 X1 X 2 X 3 X 4 X1 X 2 X 3 X 4 {0} {1} {1} {0} {0} {1} {1} {1} {0} {0} {0} {1} {1} {1} {0} {1} {2} {1} {1} {1} {1} {0} Merging • Merge 1st and 2nd • Merge 3rd and 4th • Merge 5th and 6th • Merge 7th and 8th F X1 X 2 X 3 X 4 {0} {0} {0} {1,2} X1 X 2 X 3 X 4 {1} {0} {1} {0,1} X1 X 2 {0} {0,1} {1} X1 X 2 X 3 {1} {1} {2} X3 X4 {0,1} {0} X4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 X1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 X2 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 X3 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 X4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 F 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 Minimization Example (cont) F X1 X 2 X 3 X 4 {0} {0} {0} {1,2} X1 X 2 X 3 X 4 {1} {0} {1} {0,1} X1 X 2 {0} {0,1} {1} X1 X 2 X 3 {1} {1} {2} X3 X4 {0,1} {0} X4 Multi-Output Function Using of Multi-Output Prime Implicants (Fig. 10.8 PLA Implementation) f0 X1 X 2 X 3 X1 X 2 f1 X 1 X 2 X 3 X 1 X 2 X 3 f2 X1 X 2 X 3 X1 X 2