Review Paper on wide frequency range CMOS Voltage Controlled Oscillator
for PLL
Prepared By
Mrs. Swati Umesh Gulhane
M.E. Second Year (Electronics & Telecommunication)
Ramrao Adik Institute of Technology, Nerul, Navi Mumbai, India
swatiugulhane@gmail.com
Guided By
Mrs. Sujata Kadam , Professor EXTC Dept.
Mr. M. M. Dongre , Professor & HOD EXTC Dept.
Ramrao Adik Institute of Technology, Nerul, Navi Mumbai, India
Abstract
Voltage Controlled Ring Oscillators is used
A voltage controlled oscillator (VCO) is one
of the most important basic building blocks
in analog and digital circuits. There are
many different implementations of VCOs.
One of them is a ring oscillator based VCO,
which is commonly used in the clock
generation subsystem. The main reason of
ring
oscillator
popularity
is
a
direct
consequence of its easy integration. Due to
their integrated nature, ring oscillators have
been
used
in
many
communication systems.
digital
and
in PLL circuit, used to generate the
oscillations and increase the speed of the
whole
system
for
RF
wireless
communication. This kind of Voltage
Controlled Ring Oscillators used in highresolution
oscillators
for
different
applications. The goal of this project is to
design a high speed and low power VoltageControlled Ring Oscillator in CMOS 0.18
micron technology that makes it suitable for
wireless application.
This paper deals with design and simulation
of Voltage-Controlled Ring Oscillator. The
design challenges are increasing with the
getting
compact,
increase in demand for low power, high-
became attractive for the realization of high
frequency wireless systems. The proposed
speed
differential ring oscillator is designed for
electronics
2GHz and greater than 2 GHz frequencies
phenomenal growth over the last two
by using 0.18μmCMOS technology. This is
decades, mainly due to the rapid advances in
done by exploring the ring oscillator both in
integration technologies, large-scale systems
theory and practice. Voltage Controlled
design in short, due to the advent of VLSI.
Ring Oscillators has been compared with
The number of applications of integrated
earlier reported LC VCO and the proposed
circuits in high-performance computing,
VCO shows better performance in terms of
telecommunications,
frequency and power consumption.
electronics has been rising steadily, and at a
and
high
CMOS
frequency
industry
has
and
technologies
ICs.
The
achieved
a
consumer
very fast pace. Typically, the required
Keywords: Voltage Controlled Oscillator,
computational power (or, in other words, the
Ring Oscillator, CMOS, PLL
intelligence) of these applications is the
driving force for the fast development of this
I.
field The role of oscillators is to create a
Introduction
periodic logic or analog signal with a stable
Voltage Controlled Oscillators (VCOs) are
and predictable frequency. Oscillators are
perhaps the most important element in all
required to generate the carrying signals for
communication systems, wired or wireless.
radio frequency transmission, but also for
They appear in many analog and RF signal
the main clocks of processors. The output is
processing systems. Wireless and optical
equal to the input, and the phase difference
communication systems have shown an
is equal to one fourth of the period
explosive growth during the last few years.
according to the phase detector principles
This exponential growth has driven the need
for more compact, more cost-effective, fully
integrated, low power voltage-controlled
oscillator
(VCO).
Apart
from
communication systems, VCOs are integral
part of biomedical applications. As the size
The Micro wind 3.1 software is used in
this project which allows us to design and
simulate an integrated circuit at physical
description level. The package contains a
library of common logic and analog ICs to
view edit and simulate. We can gain or
1
access to Circuit Simulation by pressing one
modern PLL is that it can be used for off-
single key. The electric extraction of the
shelf IC chips. It is generally used in clock
designed circuit is automatically performed
recovery of communication system and
and the analog simulator produces voltage
frequency
and current curves immediately.
communication system. Recently, power
This project deals with the analysis and
design of CMOS ring voltage controlled
oscillators (VCOs).The design challenges
are increasing with the increase in demand
for low power, high-frequency wireless
systems. The reasons are poor phase noise
performance of integrated VCO and large
area taken by the loop filter. Many recent
reports show that with careful design, onchip VCO can be made to produce
comparable phase noise performance with
synthesizer
of
wireless
consumption has become the main concern
in modern VLSI because of the popular use
of portable electronics. With the progress of
VLSI
technology,
PLL
is
necessarily
designed in system as a chip. Low power
designs often imply the use of low voltage
supplies, but voltage reduction is generally
limited by the required speed of operation.
Every PLL is usually composed of a phase
detector, a low pass filter, a VCO and a
frequency divider as shown in Fig.1.1
off-chip VCO.
Phase Locked Loop (PLL)
With the rapid development of integrated
circuit technology, the phase locked loop
has emerged as one of the fundamental
building block in electronics technology.
Fig. 1.1 Block Diagram of PLL
The phase locked loop has been used in the
application such as FM, stereo-decoders,
Ring Oscillator
FM demodulators, frequency shift keying
The role of oscillators is to create a
decoders, motor speed control, tracking
periodic logic or analog signal with a stable
filters, frequency, FM demodulator and a
and predictable frequency. Oscillators are
generation of local oscillators frequencies in
required to generate the carrying signals for
TV and in FM tuners. A major advantage of
radio frequency transmission, but also the
2
main clocks of processors. The ring
oscillator is a very simple oscillator circuit,
based on the switching delay existing
between the input and output of an inverter.
If we connect an odd chain of inverters, we
obtain a natural oscillation, with a period
which corresponds roughly to the number of
elementary delays per gate. The fastest
oscillation is obtained with 3 inverters (One
single inverter connected to itself does not
oscillate).
The
usual
implementation
consists in a series of five up to one hundred
Fig. 1.2 Differential Pair Delay Cell
chained inverters. Usually, one inverter in
II. Problem Definition
the chain is replaced by a NAND gate to
enable the oscillation.
The main difficulty for using submicron
For most applications, the differential ring
CMOS
oscillator is widely used, since it has a
communication systems is poor frequency
differential output to reject common-mode
range
noise, power supply noise and so on.
Precaution is required to achieve as low
Although the differential loop ring VCO has
power consumption as possible during
two input and output signals, it also has to
design
meet the Barkhausen Criteria and the
oscillators.
analysis for differential VCO is similar to a
All these specifications have trade-offs with
single-end signal ring VCO.
one another, and this makes a VCO design
Basically, the delay cell of the differential
challenging. Ring oscillator VCOs can be
ring VCO employs a differential pair as
highly compared to LC VCOs; as a result,
input and uses various types of load to get
they have far superior output frequency
enough gain. The most simple delay cell for
range, however, they have higher gain and
the differential ring VCO is shown as Fig.
phase noise, which are both undesirable. As
1.2
the number of the stages in a ring oscillator
.
oscillators
and
of
increases,
more
CMOS
the
in
power
wireless
consumption.
voltage
output
controlled
voltage
swing
3
increases. For a constant output frequency,
switching delay existing between the input
the transitions of the output waveform
and output of an inverter. VCOs are
become faster for larger number of stages.
generally of the form of a ring oscillator,
Since phase-noise is sensitive to the
relaxation oscillator or a resonant oscillator.
transitions,
phase-noise
The ring oscillator, common in monolithic
decreases with the increasing number of
topologies takes the form of an odd number
stages.
of inverters connected in a feedback loop.
The most challenging part of the PLL design
If we connect an odd chain of inverters, we
is the design of Voltage Controlled Ring
obtain a natural oscillation, with a period
Oscillator with most important parameters in
which corresponds roughly to number of
the
elementary delays per gate. Ring oscillator
hence
design
are
output
power
consumption,
structure also employs positive feedback to
frequency range, etc.
III. Proposed Design
achieve oscillation. Fig 4.1 depicts an Nstage
ring
oscillator
The proposed oscillator is fundamentally
differential
cells,
constructed by cascading series of delay
complementary outputs.
realized
using
which
have
cells to improve the power consumption and
oscillation frequency of the PLL, new
design of ring oscillator VCO using 0.18 μm
CMOS process is proposed. It will provide a
frequency of 2GHz and greater than 2GHz
which has advantage of low power and
increased frequency in comparison with
Fig. 4.1 Differential Ring Oscillator
early designed VCO.
The voltage controlled oscillator (VCO)
Design of VCO
generates a clock with a controllable
Oscillators are required to generate the
carrying
signals
for
radio
frequency
transmission, but also for the main clocks of
processors. The ring oscillator is a very
frequency. The VCO is commonly used for
clock generation in phase lock loop circuits.
The clock may vary typically by +/-50% of
its central frequency.
simple oscillator circuit, based on the
4
Proposed Voltage controlled oscillator is
shown
in
Fig.
4.2.The
current-started
inverter chain uses a voltage control Vctrl to
modify the current that flows in the N1, P1
branch. The current through N1 is mirrored
by N2, N3, N4, N5& N6. The some current
flows in P1. The current Through P1 is
mirrored by P2, P3 and P4. Consequent
change in the Vctrl induces a global change
in the inverter currents and it acts directly on
the delay.
The VCO circuit is the fundamental
part of Phase locked loop.It is designed by
Fig. 4.2. Voltage Controlled Ring
Oscillator with N stage inverter
using 0.18micrometer technology.The VCO
circuit is simulated with the help of
The Bias circuit
Advanced design system version 2008
software and layout is drawn with the help
of Microwind 3.1 software.The
frequency of VCO is 2GHz
target
which is
obtained using design of VCO with the help
of inverter that provide small circuitary low
complexity
and
there
is
problem
in
developing oscillations so to overcome this
problem we design VCO with help of
differential amplifier.In this design of VCO
circuit comparator is used as a output buffer.
The buffer circuit can drive a substantially
higher number of loads. It prevents the
circuit from overloading effect which helps
the voltage controlled oscillator circuit to
provide sustained oscillations.
In the design of VCO,the biasing circuit is
one of the important circuit.It is known as
the control circuit.The control voltage given
to the bias circuit controls the frequency of
the differential cell circuit.As the voltage
changes the number of oscillation varies and
thus the frequency also changes.Thus,we get
the stable oscillations with a predictable
frequency.The below figure 4.3 shows the
schematic diagram of the bias circuit.The
VCO design uses a self-biasing technique to
generate the necessary bias voltages of the
buffer stages. The key idea behind selfbiasing is that it allows circuits to choose the
operating bias levels in which they function
5
best. By referring all bias voltages and
respectively. Now consider the ideal ring
currents to other generated bias voltages and
oscillator. Thus by taking τ rise = τ fall = τ
currents, the operating bias levels are
the frequency of oscillation is defined as
essentially established by the operating
F osc = 1/ 2N τ
frequency.
This expression confirms that the ring
oscillator oscillation frequency depends on
number of stages (N). If the numbers of
stages are more the overall delay increases,
which
results
in
diminishing
of
the
frequency of overall system. In other words
this expression conveys a relation between
oscillator frequency and stages delay.
Actually, there is a trade-off between
number of stages and frequency of the
oscillator.
So
for
high
frequency
applications it is necessary to design such
Fig.4.3 Schematic diagram of Bias circuit
type of oscillator which has minimum
number of stages.
Power Consumption
Design Considerations
The average power dissipation in an N-stage
Oscillation Frequency
CMOS ring oscillator circuit is
For N- stage ring oscillator the oscillation
𝑃𝑎𝑣𝑔= 𝑛𝑉𝐷𝐷𝐼𝑎𝑣𝑔
= 𝑛𝑁𝑉𝐷𝐷𝑞𝑚𝑎𝑥𝑓𝑜𝑠𝑐
frequency is defined as
Fosc = 1/ N ( τ rise + τ fall )
Where 𝑞𝑚𝑎𝑥= 𝐶𝑡𝑜𝑡∗𝑉𝐷𝐷
𝐼𝑎𝑣𝑔= 𝑁𝐶𝑡𝑜𝑡𝑉𝐷𝐷𝑓𝑜𝑠𝑐
The above equation clearly gives the
Where, Fosc is the frequency of oscillation,
information that when circuit switches at
N is number of stages, and τ rise, τ fall are
high frequency the contribution of dynamic
the rise and fall time of each delay stage
power consumption is more due to output
load capacitance charging and discharging
mechanisms. Where Pavg is average power,
6
Cload is output load capacitance, VDD is
Voltage Controlled Ring Oscillator for PLL
supply voltage and Fosc is frequency of
to get wide range frequency. In TV
oscillation.
controlling system VCO is used to tune
Performance Results
different channels which have different
frequencies
as VCO provides different
values of frequencies according to change in
control voltage.
In
today’s
communication
system,
oscillators are one of the key building blocks
realizing a single-chip radio. Advanced RF
CMOS technology has been implemented to
solve various problems related to the
Fig. 4.4 Frequency Variation in 3 stage and
conductive substrate and operation speed of
5 stage Differential Ring VCO
active devices. The inherent 1/f noise is still
a bottleneck to the design of integrated low
phase noise oscillators. Fully integrated
VCOs is one of the major bottleneck in
RFIC design wireless transceivers. The
CMOS processes are attractive due to the
highest integration level achievement and
cost effective solution. Proposed design can
be an effective to improve the power
Fig. 4.5 Power Variation in 3 stage and 5
stage Differential Ring VCO
consumption and oscillation frequency of
the PLL. It will provide a frequency of
2GHz and greater than 2GHz which has
advantage
of
reduced
size,
increased
frequency and low power consumption in
Scope of Work
comparison with early designed VCO.
Hardware/Software specifications
The scope of this project is to design
7
Software tool used for this project work is
and starts associated with changing design
Microwind 3.1. It is a new era of creativity
tools mid-cycle.
in deep submicron CMOS VLSI and IC
IV. Conclusion
Design.Microwind3.1 is a complete solution
for deep sub-micron Transistor level CMOS
In
design and simulation. As fresh perspectives
architecture is demonstrated using 0.18 μm
drive competitive edge and embrace the
technology provided by TSMC. However,
explosion of technology, MICROWIND3.1
low power consumption is achieved by
has embraced the IC designs education using
using minimum number of transistors, rail to
CMOS VLSI in the same way.
rail swing and maintaining the minimum
this
W/L.
Advanced System Design is most popular
paper
This
differential
work
gives
ring
the
VCO
various
performance curves by which the relation
high-frequency circuit design software.
between frequency and power consumption
Advanced Design System (ADS) is the
is established. This paper also provides the
industry leader in high-frequency design. It
comparison between 3-stage and 5-stage
supports system and RF design engineers
ring oscillators.
developing all types of RF designs, from
simple
to
the
RF/microwave
most
from
The proposed VCO is designed for 2 GHz
integrated
and greater than 2 GHz frequency. For this
complex,
modules
to
and
two topologies has been used, one is by
a
using inverter and other is by using
complete set of simulation technologies
differential amplifier. Both these topologies
ranging from frequency and time-domain
are modularized. The inverter topology uses
circuit simulation to electromagnetic field
odd number of inverters and it provides
simulation,
small
MMICs
for
aerospace/defence
ADS
communications
applications.
lets
With
designers
fully
circuitary,
low
complexity
and
characterize and optimize designs. The
problems in developing oscillations. Hence,
single,
to overcome this problem we have used
integrated
design
environment
provides system and circuit simulators,
differential
amplifier
topology
which
along with schematic capture, layout, and
provides complex circuitry and it develops
verification capability eliminating the stops
fast oscillations.
8
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