Package with 4-valued
logic
Signal Attributes
Assertion
Data Flow description
Few more Examples of
Simulation
• Build a library of logic gates
– AND, OR, NAND, NOR, INV, etc.
• Include sequential elements
– DFF, Register, etc.
• Include tri-state devices
• Use 4-valued logic
Our goal is to
Explain 4-valued logic
– ‘X’, ‘0’, ‘1’, ‘Z’
– Encapsulate global declarations in a package
Global Package
• Build a library of logic gates
– AND, OR, NAND, NOR, INV, etc.
• Include sequential elements
– DFF, Register, etc.
• Include tri-state devices
• Use 4-valued logic
– ‘X’, ‘0’, ‘1’, ‘Z’
– Encapsulate global declarations in a package
PACKAGE resources IS
TYPE level IS ('X', '0', '1', 'Z'); -- enumerated type
TYPE level_vector IS ARRAY (NATURAL RANGE <>) OF level;
-- type for vectors (buses)
SUBTYPE delay IS TIME; -- subtype for gate delays
-- Function and procedure declarations go here
END resources;
Next we build gates
Two Input AND Gate Example
USE work.resources.all;
ENTITY and2 IS
ARCHITECTURE behav OF and2 IS
BEGIN
one : PROCESS (a,b)
GENERIC(trise : delay := 10 ns;
tfall : delay := 8 ns);
PORT(a, b : IN level;
c : OUT level);
END and2;
BEGIN
IF (a = '1' AND b = '1') THEN
c <= '1' AFTER trise;
ELSIF (a = '0' OR b = '0') THEN
c <= '0' AFTER tfall;
ELSE
c<= 'X' AFTER (trise+tfall)/2;
END IF;
END PROCESS one;
END behav;
a
b
c
1 and X = X
Observe that we use
here three-valued
algebra {0,1,X}
And Gate Simulation Results
Tri-State Buffer Example
USE work.resources.all;
ENTITY tri_state IS
ARCHITECTURE behav OF tri_state IS
GENERIC(trise : delay := 6 ns;
tfall : delay := 5 ns;
thiz : delay := 8 ns);
BEGIN
one : PROCESS (a,e)
PORT(a : IN level;
e : IN level;
b : OUT level);
END tri_state;
b
e
Observe that we use
here four-valued
algebra {0,1,X,Z}
BEGIN
IF (e = '1' AND a = '1') THEN
-- enabled and valid data
b <= '1' AFTER trise;
ELSIF (e = '1' AND a = '0') THEN
b <= '0' AFTER tfall;
ELSIF (e = '0') THEN -- disabled
b <= 'Z' AFTER thiz;
ELSE -- invalid data or enable
b <= 'X' AFTER (trise+tfall)/2;
END IF;
END PROCESS one;
END behav;
a
Tri-State Buffer Simulation Results
ARCHITECTURE behav OF tri_state IS
BEGIN
USE work.resources.all;
ENTITY tri_state IS
GENERIC(trise : delay := 6 ns;
tfall : delay := 5 ns;
thiz : delay := 8 ns);
PORT(a : IN level;
e : IN level;
b : OUT level);
END tri_state;
one : PROCESS (a,e)
BEGIN
IF (e = '1' AND a = '1') THEN
-- enabled and valid data
b <= '1' AFTER trise;
ELSIF (e = '1' AND a = '0') THEN
b <= '0' AFTER tfall;
ELSIF (e = '0') THEN -- disabled
b <= 'Z' AFTER thiz;
ELSE -- invalid data or enable
b <= 'X' AFTER (trise+tfall)/2;
END IF;
END PROCESS one;
END behav;
D Flip Flop Example
USE work.resources.all;
ENTITY dff IS
GENERIC(tprop : delay := 8 ns;
tsu
: delay := 2 ns);
PORT(d
clk
enable
q
qn
END dff;
:
:
:
:
:
IN level;
IN level;
IN level;
OUT level;
OUT level);
ARCHITECTURE behav OF dff IS
BEGIN
one : PROCESS (clk)
BEGIN
-- check for rising clock edge
IF ((clk = '1' AND clk'LAST_VALUE = '0')
AND enable = '1') THEN -- ff enabled
-- first, check setup time requirement
IF (d'STABLE(tsu)) THEN
-- check valid input data
IF (d = '0') THEN
q <= '0' AFTER tprop;
qn <= '1' AFTER tprop;
ELSIF (d = '1') THEN
q <= '1' AFTER tprop;
qn <= '0' AFTER tprop;
ELSE -- else invalid data
q <= 'X';
qn <= 'X';
END IF;
ELSE -- else violated setup time requirement
q <= 'X';
qn <= 'X';
END IF;
END IF;
END PROCESS one;
END behav;
USE work.resources.all;
ENTITY dff IS
GENERIC(tprop : delay := 8 ns;
tsu : delay := 2 ns);
PORT(d
: IN level;
clk : IN level;
enable : IN level;
q : OUT level;
qn : OUT level);
END dff;
D Flip Flop
Simulation
Results
ARCHITECTURE behav OF dff IS
BEGIN
one : PROCESS (clk)
BEGIN
-- check for rising clock edge
IF ((clk = '1' AND clk'LAST_VALUE = '0')
AND enable = '1') THEN -- ff enabled
-- first, check setup time requirement
IF (d'STABLE(tsu)) THEN
-- check valid input data
IF (d = '0') THEN
q <= '0' AFTER tprop;
qn <= '1' AFTER tprop;
ELSIF (d = '1') THEN
q <= '1' AFTER tprop;
qn <= '0' AFTER tprop;
ELSE -- else invalid data
q <= 'X';
qn <= 'X';
END IF;
ELSE -- else violated setup time requirement
q <= 'X';
qn <= 'X';
END IF;
END IF;
END PROCESS one;
END behav;
Assertion Statements
assert condition
report message
severity level;
• Ex.
assert not (S = '1' and R = '1')
report “S and R are equal to '1'”
severity Error;
• An assertion statement specifies a
boolean condition to check, an error
message and a severity indication.
Assertion Statements
When the condition is false, the error message is sent to the
system output with an indication of the severity and the name of
the design unit in which the assertion occurred.
– (Default message: “Assertion violation”).
• The severity is of the type Severity_Level which has the values
of:
–
–
–
–
Note,
Warning,
Error,
and Failure. (Default se-verity level: Error)
• In some VHDL system, unsatisfied conditions of severity Error
or Failure cause the simulation to terminate.
•
Using Assertions to Specify Timing
Requirements
Assertion
statements
can be used
to specify
timing
requirements
, such as setup time and
hold time.
• Example
If data is NOT stable and
clock=1 then check if
clock is stable in hold
time
If this condition is false report
is printed
When data changes during
clock=1 it cannot change
during hold time from
clock change, this is OK
because it changed after
hold_time
Signal
related
attributes
Pre-defined Signal Attributes
Signal Attributes event
and last_value
Short definitions of these and
others Signal Attributes
• SIGNAL’event - returns True if an event occurred on this signal during this
delta
• SIGNAL’active - returns True if a transaction occurred this delta
• SIGNAL’last_event - returns the elapsed time since previous event
• SIGNAL’last_value - returns previous value of signal before last event
• SIGNAL’last_active - returns time elapsed since previous transaction
Signal Attributes that return Signals
• Delayed(t), Stable, Quiet and transaction
Stable Attribute
Signal’stable(time) creates a signal that is True when the reference
signal has no events for time value
Derived signal attribute
• VHDL contains
a number of
predefined
attributes which
are related to
signals.
Signal -Related
Attributes
• They can be
divided into two
classes:
– attributes which
define signals
themselves
– attributes which
are functions to
provide
information
about signals.
These attributes are signals
themselves
Examples of Using Attributes:
Detecting Edges
We use attribute
event
Measuring Pulse Width
Measuring Pulse Width (cont)
Measuring Setup Time
Delay
Parameterization
• Entities can be
made
parameterized
by the use of
• GENERIC
CONSTANTS
• They are
passed to an
instantiated
component by
its
environment
• A generic
constant can
be used in
computation,
but remains
fixed during
simulation.
Delay Parameterization
Delay
Parameterization
- Structured
Example
Data Flow Descriptions
in VHDL
• A data flow description consists of a set
of concurrent signal assignment
statements.
• A signal assignment statement
executes in response to change on its
input signals.
Data Flow Descriptions in VHDL
Each value in the waveform will be scheduled to appear
on the target after the specified delay.
• If the assignment statement executes again, previously
scheduled values may be overridden.
• A delay of zero represents an infinitesimally small delay
-signal assignment never takes effect immediately.
• Data flow descriptions are similar to register-transfer
level expressions.
• They may imply hardware implementation structure.
Simple data-flow
example:
More examples of
Concurrent Signal
Assignment
Guarded will be discussed in a
separate lecture
More examples: Concurrent Signal Assignment
• This
describes a
decoder, or
translator
from binary
to one-hot
code
We discussed it
but now we add timing
Conditional Signal Assignment
Selected Signal Assignment
concatenation
For students to use and think about
• What is the basic timing model for simulation in
VHDL.
• Types of delay in VHDL:
– transport,
– inertial
– delay.
• Detailed explanation of delta model. Why previous
models were inconvenient? The student should be
able to assume delta delay draw the timing diagram
and next go with delta to zero and illustrate
graphically the results of simulation.
For students to use and think about
• General assignment statements with bit selections,
concatenations, timing delays and expressions.
• Variables versus signals in assignment statements.
• Some selected signal-related attributes.
• Conditional signal assignment with when.
• Concurrent signal assignment with when
• Explain simulation with four-valued simulator.
• Assertion statements.
• Detailed D FF with timing.
• Tri-state buffer and its simulation.
Questions for students
• Example: MUX
• This example highlights the difference between signals
and variables
ARCHITECTURE test1 OF mux IS
SIGNAL x : BIT := '1';
SIGNAL y : BIT := '0';
BEGIN
PROCESS (in_sig, x, y)
BEGIN
x <= in_sig XOR y;
y <= in_sig XOR x;
END PROCESS;
END test1;

ARCHITECTURE test2 OF mux IS
SIGNAL y : BIT := '0';
BEGIN
PROCESS (in_sig, y)
VARIABLE x : BIT := '1';
BEGIN
x := in_sig XOR y;
y <= in_sig XOR x;
END PROCESS;
END test2;
Assuming a 1 to 0 transition on in_sig, what are
the resulting values for y in the both cases?
Sources
• VLSI. Ohio University, Starzyk
• Krzysztof Kuchcinski
• Yingtao Jiang
• Hai Zhou
• Prof. K. J. Hintz