Chapter 4:
Central Processing Unit
CPU
Register File
CU
ALU
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General Register Organization
Input
R1
R2
R3
R4
R5
R6
R7
LD
SELA
MUX
A
3x8
Decoder
OPR
SELD
MUX
SELB
B
ALU
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General Register Organization
OPR
00000
00001
00010
00101
00110
01000
01010
01100
01110
10000
11000
Operation
Transfer A
Increment A
Add A + B
Subtract A − B
Decrement A
AND A and B
OR A and B
XOR A and B
Complement A
Shift right A
Shift left A
Examples:
Microoperation
R1 ← R2 − R3
R4 ← SHL R4
Input
R1
R2
R3
R4
R5
R6
R7
LD
SELA
MUX
A
3x8
Decoder
OPR
SELD
MUX
SELB
B
ALU
SELA SELB SELD OPR
010
011
001 00101
100
000
100 11000
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Stack Organization
 LIFO
Last In First Out
Current
Top of Stack
TOS
SP
FULL
EMPTY
Stack Bottom
0
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
1
0
0
0
0
2
5
0
2
1
3
5
8
5
5
Stack
4 / 44
Stack Organization
 PUSH
Current
Top of Stack
TOS
SP ← SP – 1
M[SP] ← DR
If (SP = 0) then (FULL ← 1)
EMPTY ← 0
SP
FULL
EMPTY
Stack Bottom
1 6 9 0
0
1
2
3
4
5
6
7
8
9
10
1
0
0
0
0
0
6
1
0
0
0
0
9
2
5
0
2
1
0
3
5
8
5
5
Stack
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Stack Organization
 POP
Current
Top of Stack
TOS
DR ← M[SP]
SP ← SP + 1
If (SP = 11) then (EMPTY ← 1)
FULL ← 0
SP
FULL
EMPTY
Stack Bottom
0
1
2
3
4
5
6
7
8
9
10
1
0
0
0
0
0
6
1
0
0
0
0
9
2
5
0
2
1
0
3
5
8
5
5
Stack
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Stack Organization
 Memory Stack
● PUSH
PC
0
1
2
AR
100
101
102
SP ← SP – 1
M[SP] ← DR
● POP
DR ← M[SP]
SP ← SP + 1
SP
200
201
202
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Reverse Polish Notation
 Infix Notation
A+B
 Prefix or Polish Notation
+AB
 Postfix or Reverse Polish Notation (RPN)
AB+
AB+CD
(2) (4)  (3) (3)  +
RPN
ABCD+
(8) (3) (3)  +
(8) (9) +
17
8 / 44
Reverse Polish Notation
 Example
(A + B)  [C  (D + E) + F]
(A B +) (D E +) C  F + 
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Reverse Polish Notation
 Stack Operation
(3) (4)  (5) (6)  +
PUSH
3
PUSH
4
MULT
6
PUSH
5
30
4
5
PUSH
6
3
42
12
MULT
ADD
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CPU Organization
 Single Accumulator
● Result usually goes to the Accumulator
● Accumulator has to be saved to memory quite often
General Register
● Registers hold operands thus reduce memory traffic
● Register bookkeeping
Stack
● Operands and result are always in the stack
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Instruction Formats
 Three-Address Instructions
● ADD
R1, R2, R3
R1 ← R2 + R3
 Two-Address Instructions
● ADD
R1, R2
R1 ← R1 + R2
One-Address Instructions
● ADD
AC ← AC + M[AR]
M
 Zero-Address Instructions
● ADD
TOS ← TOS + (TOS – 1)
 RISC Instructions
● Lots of registers. Memory is restricted to Load & Store
Opcode Operand(s) or Address(es)
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
 Three-Address
1. ADD
R1, A, B
; R1 ← M[A] + M[B]
2. ADD
R2, C, D
; R2 ← M[C] + M[D]
3. MUL
X, R1, R2
; M[X] ← R1  R2
13 / 44
Instruction Formats
Example: Evaluate (A+B)  (C+D)
 Two-Address
1. MOV
R1, A
; R1 ← M[A]
2. ADD
R1, B
; R1 ← R1 + M[B]
3. MOV
R2, C
; R2 ← M[C]
4. ADD
R2, D
; R2 ← R2 + M[D]
5. MUL
R1, R2
; R1 ← R1  R2
6. MOV
X, R1
; M[X] ← R1
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
 One-Address
1. LOAD A
; AC ← M[A]
2. ADD
; AC ← AC + M[B]
B
3. STORE T
; M[T] ← AC
4. LOAD C
; AC ← M[C]
5. ADD
D
; AC ← AC + M[D]
6. MUL
T
; AC ← AC  M[T]
7. STORE X
; M[X] ← AC
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
 Zero-Address
1. PUSH
A
; TOS ← A
2. PUSH
B
; TOS ← B
; TOS ← (A + B)
3. ADD
4. PUSH
C
; TOS ← C
5. PUSH
D
; TOS ← D
6. ADD
; TOS ← (C + D)
7. MUL
; TOS ← (C+D)(A+B)
8. POP
X
; M[X] ← TOS
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
 RISC
1. LOAD R1, A
; R1 ← M[A]
2. LOAD R2, B
; R2 ← M[B]
3. LOAD R3, C
; R3 ← M[C]
4. LOAD R4, D
; R4 ← M[D]
5. ADD
R1, R1, R2
; R1 ← R1 + R2
6. ADD
R3, R3, R4
; R3 ← R3 + R4
7. MUL
R1, R1, R3
; R1 ← R1  R3
8. STORE X, R1
; M[X] ← R1
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Addressing Modes
 Implied
Opcode Mode
...
● AC is implied in “ADD M[AR]” in “One-Address”
instr.
● TOS is implied in “ADD” in “Zero-Address” instr.
 Immediate
● The use of a constant in “MOV R1, 5”, i.e. R1 ← 5
 Register
● Indicate which register holds the operand
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Addressing Modes
 Register Indirect
● Indicate the register that holds the number of the
register that holds the operand
MOV R1, (R2)
 Autoincrement / Autodecrement
● Access & update in 1 instr.
R1
R2 = 3
R3 = 5
Direct Address
● Use the given address to access a memory location
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Addressing Modes
 Indirect Address
● Indicate the memory location that holds the address of
the memory location that holds the data
AR = 101
100
101
102
103
104
0 1 0 4
1 1 0 A
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Addressing Modes
 Relative Address
● EA = PC + Relative Addr
PC = 2
0
1
2
+
AR = 100
Could be Positive or
Negative
(2’s Complement)
100
101
102
103
104
1 1 0 A
21 / 44
Addressing Modes
 Indexed
● EA = Index Register + Relative Addr
Useful with
“Autoincrement” or
“Autodecrement”
XR = 2
+
AR = 100
Could be Positive or
Negative
(2’s Complement)
100
101
102
103
104
1 1 0 A
22 / 44
Addressing Modes
 Base Register
● EA = Base Register + Relative Addr
Could be Positive or
Negative
(2’s Complement)
AR = 2
+
BR = 100
Usually points to
the beginning of
an array
100
101
102
103
104
0
0
0
0
0
0
0
0
1
0
0
1
0
0
5
5
2
A
7
9
23 / 44
Types of Instructions
 Data Transfer Instructions
Name
Mnemonic
Load
LD
Store
ST
Move
MOV
Exchange
XCH
Input
IN
Output
OUT
Push
PUSH
Pop
POP
Data value is
not modified
 Data Manipulation Instructions
 Program Control Instructions
24 / 44
Data Transfer Instructions
Mode
Assembly
Register Transfer
Direct address
LD ADR
AC ← M[ADR]
Indirect address
LD @ADR
AC ← M[M[ADR]]
Relative address
LD $ADR
AC ← M[PC+ADR]
Immediate operand
LD #NBR
AC ← NBR
Index addressing
LD ADR(X)
AC ← M[ADR+XR]
Register
LD R1
AC ← R1
Register indirect
LD (R1)
AC ← M[R1]
Autoincrement
LD (R1)+
AC ← M[R1], R1 ← R1+1
25 / 44
Data Manipulation Instructions
 Arithmetic
 Logical & Bit Manipulation
 Shift
Name
Mnemonic
Clear
CLR
Complement
COM
AND
AND
OR
OR
Exclusive-OR
XOR
Clear carry
CLRC
Set carry
SETC
Complement carry COMC
Enable interrupt
EI
Disable interrupt
DI
Name
Mnemonic
Increment
INC
Decrement
DEC
Add
ADD
Subtract
SUB
Multiply
MUL
Divide
DIV
Add with carry
ADDC
Subtract with borrow
SUBB
Negate
NEG
Name
Logical shift right
Logical shift left
Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Rotate right through carry
Rotate left through carry
Mnemonic
SHR
SHL
SHRA
SHLA
ROR
ROL
RORC
ROLC
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Program Control Instructions
Name
Mnemonic
Branch
BR
Jump
JMP
Skip
SKP
Call
CALL
Return
RET
Compare (Subtract)
CMP
Test (AND)
TST
Subtract A – B but
don’t store the result
10110001
00001000
Mask
00000000
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Status Bits
Cn-1
A
B
ALU
Cn
F
V
Z
S
C
Fn-1
Zero Check
28 / 44
Conditional Branch Instructions
Mnemonic
Branch Condition
Tested Condition
BZ
Branch if zero
Z=1
BNZ
Branch if not zero
Z=0
BC
Branch if carry
C=1
BNC
Branch if no carry
C=0
BP
Branch if plus
S=0
BM
Branch if minus
S=1
BV
Branch if overflow
V=1
BNV
Branch if no overflow
V=0
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Conditional Branch Instructions
 Example:
● A: 1 1 1 1 0 0 0 0
A:
● B: 0 0 0 1 0 1 0 0
+(−B): 1 1 1 0 1 1 0 0
11110000
11011100
C=1
Z=0
S=1
V=0
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Program Interrupts
 Save:
● PC
● Registers
● Status Bits
Program
Status Word
PSW
Main Program
•
•
•
•
10 CMA
11
•
12 STA [201]
•
•
•
•
•
ISR
•
Load AC
•
•
RET
31 / 44
Types of Interrupts
 External Interrupts
● Keyboard, Mouse … etc
 Internal Interrupts
● Timers, Divide-By-Zero … etc
 Software Interrupts
Main Program
•
•
•
•
10 INT
11
•
•
•
ISR
•
•
•
•
RET
32 / 44
CISC
 Complex Instruction Set Computer
● Large number of instructions with a complicated ALU
● Some instructions perform specialized tasks and are
used infrequently
● Large variety of addressing modes
● Variable length instruction formats
● Instructions can manipulate operands in memory
33 / 44
RISC
 Reduced Instruction Set Computer
● Relatively few instructions, hence simple ALU
● Relatively few addressing modes
● Memory access limited to “load” and “store”
● All operations done within “registers” of the CPU
● Fixed-length and easily decoded instruction format
● Single-cycle instruction execution
● Hardwired control unit
34 / 44
Homework
Chapter 8
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
8-1
8-3
8-7
8-8
8-9
8-11
8-13
8-14
8-15
8-16
8-17
8-18
8-32
35 / 44
Homework
 Mano
8-1
A bus-organized CPU has 16 registers with 32 bits in
each, an ALU, and a destination decoder.
a. How many multiplexers are there in the A bus, and
what is the size of each multiplexer?
b. How many selection inputs are needed for MUX A
and MUX B?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are there in the ALU
for data, including input and output carries?
e. Formulate a control word for the system assuming
that the ALU has 35 operations.
36 / 44
Homework
8-3
Specify the control word that must be applied to the
processor of Fig. 8-2 to implement the following
microoperations.
a. R1 ← R2 + R3
b. R4 ← R4
c. R5 ← R5 – 1
d. R6 ← shl R1
e. R7 ← input
37 / 44
Homework
8-7
Convert the following arithmetic expressions from infix to
reverse Polish notation.
a. A  B + C  D + E  F
b. A  B + A  (B  D + C  E)
c. A + B  [C  D + E  (F + G)]
A * [B + C  (D + E)]
d. ─────────────
F  (G + H)
38 / 44
Homework
8-5
Convert the following arithmetic expressions from reverse
Polish notation to infix notation.
a. A B C D E +  − /
b. A B C D E  / − +
c. A B C  / D − E F / +
d. A B C D E F G +  +  + 
8-9
Convert the following numerical arithmetic expression
into reverse Polish notation and show the stack operations
for evaluating the numerical result.
(3 + 4) [10 (2 + 6) + 8]
39 / 44
Homework
8-11 A computer has 32-bit instructions and 12-bit addresses.
If there are 250 two-address instructions, how many oneaddress instructions can be formulated?
8-13 The memory unit of a computer has 256K words of 32
bits each. The computer has an instruction format with
four fields: an operation code field, a mode field to specify
one of seven addressing modes, a register address field to
specify one of 60 processor registers, and a memory
address. Specify the instruction format and the number of
bits in each field if the instruction is in one memory word.
40 / 44
Homework
8-14 A two-word instruction is stored in memory at an address
designated by the symbol W. The address field of the
instruction (stored at W + 1) is designated by the symbol
Y. The operand used during the execution of the
instruction is stored at an address symbolized by Z. An
index register contains the value X. State how Z is
calculated from the other addresses if the addressing
mode of the instruction is
a. direct
b. indirect
c. relative
d. indexed
41 / 44
Homework
8-15 A relative mode branch type of instruction is stored in
memory at an address equivalent to decimal 750. The
branch is made to an address equivalent to decimal 500.
a. What should be the value of the relative address field
of the instruction (in decimal)?
b. Determine the relative address value in binary using
12 bits. (Why must the number be in 2’s complement?)
c. Determine the binary value in PC after the fetch phase
and calculate the binary value of 500. Then show that
the binary value in PC plus the relative address
calculated in part (b) is equal to the binary value of
500.
42 / 44
Homework
8-16 How many times does the control unit refer to memory
when it fetches and executes an indirect addressing mode
instruction if the instruction is (a) a computational type
requiring an operand from memory; (b) a branch type.
8-17 What must the address field of an indexed addressing
mode instruction be to make it the same as a register
indirect mode instruction?
8-18 An instruction is stored at location 300 with its address
field at location 301. The address field has the value 400.
A processor register R1 contains the number 200.
Evaluate the effective address if the addressing mode of
the instruction is (a) direct; (b) immediate; (c) relative;
(d) register direct; (e) index with R1 as the index register.
43 / 44
Homework
8-32 The content of the top of a memory stack is 5320. The
content of the stack pointer SP is 3560. A two-word call
subroutine instruction is located in memory at address
1120 followed by the address field of 6720 at location
1121. What are the content of PC, SP, and the top of the
stack:
a. Before the call instruction is fetched from memory?
b. After the call instruction is executed?
c. After the return from subroutine?
44 / 44