Low Power And High Performance Double
Edge Triggered Flip-flop
B.Sreekanth Reddy, R.Mallikarjuna Reddy, Kuppam N Chandra Sekhat

Abstract— The power consumption of a system is a
crucial parameter in modern VLSI circuits especially for low
power applications. In this project, a low power and high
performance Double Edge Triggered D-Flip Flop (DETFF)
design is proposed in 45nm CMOS technology. The proposed
DETFF is having less number of transistors than earlier
designs. The novelty of the proposed flip flop lies in the
feedback strategy using common feedback inverter and pass
transistors in the place of transmission gates to make the
design in static with less number of transistors. This improves
the power efficiency of the proposed flip flop. Simulations are
carried out using HSPICE tool with different clock frequencies
ranging from 400MHz to 2GHz and with different supply
voltages ranging from 0.8V to 1.2V.
In general, a power delay product (PDP) based
comparison is appropriate for low power portable systems. At
nominal condition, the PDP of the proposed DETFF is
improved by 65.48% and 44.85% over earlier designs DETFF
1 and DETFF 2 respectively. Simulation results show lowest
power dissipation and least delay than existing designs, which
claims that the proposed DETFF is suitable for low power and
high speed applications.
Index Terms—CMOS, flip - flops, Double - edge triggered, power
dissipation, delay and PDP.
INTRODUCTION
Very Large Scale Integration (VLSI) is the
methodology of making coordinated circuits by joining a
huge number of transistors into a solitary chip. VLSI
started in the 1970s when complex semiconductor and
correspondence innovations were being produced. The
chip is a VLSI gadget.
The principal semiconductor chips held two
transistors each. Ensuing advances included more
transistors, and as an outcome, more individual capacities
or frameworks were incorporated about whether. The
initially coordinated circuits held just a couple of gadgets,
maybe upwards of ten diodes, transistors, resistors and
capacitors, making it conceivable to create one or more
rationale entryways on a solitary gadget. The little scale
joining (SSI), changes in system prompted gadgets with
many rationale doors, known as medium-scale mix (MSI).
R.Mallikarjuna Reddy, ECE Department, Jawaharlal Nehru
Technology University, GVIC College, Madanapalle, Andhra Pradhesh,
INDIA,Mobile:8096330172 email:mallikarjunareddy.r416@gmail.com
Second Author name,ECE Department Name, Jawaharlal Nehru
Technology University,GVIC College,Madanapalle,Andhra Pradhesh
,INDIA,Mobile:9949981046.,e-mail:sreekanthreddy52@gmail.com
Kuppam N Chandra Sekhar, ECE Department, Jawaharlal Nehru
Technology University,GVIC College,Madanapalle,Andhra Pradhesh
,INDIA,Mobile:9885229501, e-mail: chandrasekhar501@gmail.com.
Further changes prompted expansive scale
combination (LSI), i.e. frameworks with in any event a
thousand rationale entryways. Current engineering has
moved far past this imprint and today's chip have numerous
a huge number of entryways and billions of individual
transistors known as "Vast Scale Integration (VLSI). This is
the field which includes pressing more rationale gadgets
into littler and more diminutive ranges.
1.1.History and Evolution of VLSI:
The history and evolution of VLSI is given below.
At one time, there was an exertion to name and adjust
different levels of substantial scale reconciliation above
VLSI. Terms like Ultra-huge scale Integration (ULSI) were
utilized. At the same time the enormous number of
entryways and transistors accessible on regular gadgets has
rendered such fine qualifications debatable. Terms
recommending more noteworthy than VLSI levels of mix
are no more in boundless utilization. Indeed VLSI is
currently sort of curious, given the regular presumption that
all microchips are VLSI or better.
Starting early 2008, billion-transistor processors
are industrially accessible, a case of which is Intel's
Montecito Itanium chip. This is relied upon to wind up more
regular place as semiconductor manufacture moves from the
current era of 65 nm methods to the following 45 nm eras
(while encountering new difficulties, for example, expanded
variety crosswise over procedure corners).
1.2.Structured Design and difficulties
Organized VLSI configuration is a particular
technique began via Carver Mead and Lynn Conway for
sparing microchip region by minimizing the interconnect
fabrics zone. This is gotten by monotonous course of action
of rectangular macro pieces which can be interconnected
utilizing wiring by projection. Organized VLSI
configuration had been famous in the early 1980s, yet lost
its prevalence later due to the approach of arrangement and
steering instruments squandering a considerable measure of
territory by directing, which is endured in view of the
advancement of Moore's Law.
Moore's Law:
Moore's law depicts a long haul incline ever. The
quantity of transistors that can be put reasonably on an
incorporated circuit duplicates roughly at regular intervals
indicated in figure 1.1. This pattern has proceeded for more
1
than a large portion of a century and is relied upon to
proceed until 2015 or 2020 or later.
forcefully in every innovation era to accomplish higher
coordination thickness and execution
II LITERATURE SURVEY
2.1.Power Dissipation:
Fig 1.1.Moores Law
Challenges
As chip configuration get to be more mind
boggling because of innovation scaling, the planners have
experienced a few difficulties which compel them to think
past the outline plane, and look ahead to post-silicon:
Power utilization/Heat dissemination
It is more advantageous to discuss power scattering
of computerized circuits as of right now. Despite the fact
that power depends significantly on the circuit style, it can
be partitioned, when all is said in done, into static and
element power. The static force is created because of the DC
predisposition current, or because of spillage momentums.
In the majority of the rationale families aside from the pushforce sorts, for example, CMOS, the static power has a
tendency to rule. That is the motivation behind why CMOS
is the most suitable circuit style for substantial scale joining
(VLSI).
High pressing thickness
Despite the fact that CMOS has points of interest,
however when the CMOS circuit is utilized as a part of
cutting edge advanced coordinated circuits, power
utilization can be credited to four principle segments:
Pavg = Pdynamic + Pstatic + Psc + Pleakage
As limit voltages have stopped to scale with
propelling procedure engineering, element power
dissemination has not scaled relatively. Keeping up
rationale unpredictability when scaling the configuration
down just implies that the force dissemination for every
zone will go up. This has offered ascent to procedures, for
example, dynamic voltage and recurrence scaling (DVFS) to
minimize general force.
Process variety
As photolithography strategies tend closer to the
essential laws of optics, accomplishing high precision in
doping focuses and scratched wires is getting to be more
troublesome and inclined to lapses because of variety.
Fashioners now must mimic crosswise over different
creation methodology corners before a chip is affirmed
prepared for generation.
Stricter configuration tenets
due to lithography and engraving issues with
scaling, outline standards for format have gotten to be
progressively stringent. Planners must remember always of
these standards while laying out custom circuits. The
overhead for specially craft is currently arriving at a tipping
point, with numerous configuration houses picking to switch
to electronic outline mechanization (EDA) devices to
mechanize their outline process.
Timing/outline conclusion
As clock frequencies have a tendency to scale up,
planners are thinking that it more hard to disseminate and
keep up low clock skew between these high recurrence
tickers over the whole chip. This has prompted a climbing
enthusiasm toward multi center and multiprocessor
architectures, since a general speedup can be acquired by
bringing down the clock recurrence and circulating
transforming. CMOS gadgets have scaled descending
Fig 2.1: Sources of Power Dissipation in CMOS Circuits
The above mathematical statement comprises of
four terms and thus represents that there are four significant
wellsprings of force utilization in an advanced CMOS
circuits. The main term speaks to the exchanging part of
force, the second term speaks to the static force. The third
term speaks to the short out force is brought on by the
immediate way in the middle of VDD and ground, i.e.
impede Isc, The fourth term is spillage power. The figure
2.1 demonstrates the wellsprings of force dissemination in
CMOS circuits.
Static Power
Strictly talking, advanced CMOS circuits shouldn't
devour static force for steady static current stream. All nonspillage present in CMOS circuits ought to just happen in
homeless people when signs are exchanging. However there
are times when deviations from CMOS style circuit
configuration are essential, a sample of which is pseudo
NMOS rationale circuit. Static force dissemination relies on
upon a current stream from force to ground amid perfect
time dissimilar to short out force scattering, which happens
just amid exchanging movement. NMOS circuits indicate
high static force utilizations on the grounds that power is
associated straightforwardly to ground when entryways
2
yield is rationale zero. In decently outlined and low power
CMOS plans, static force ought to be zero.
The short out present ISC, which is emerges when
both the NMOS and PMOS transistor systems are at the
same time dynamic or on, directing present from the supply
voltage VDD to ground. The force dispersal because of
short out present Isc is known as short out force
dissemination, PSC given by
Psc = IscVdd
2.2 Power Reduction Techniques
The following are some of the techniques to reduce power
dissipation.
Reduction of Power Supply
The energy and power consumed by the CMOS
digital circuits are sensitive to the power supply voltage as
given by the following equations.
Energy, E = CVDD2
Power, P = CVDD2f
Reducing the power supply voltage is an efficient
approach to lower the energy and power. The power supply
voltage is actually the most crucial factor in reducing
energy/ power. This will, however, be at the expense of the
delay of the circuits. Using the Power Delay Product
(PDP) as a metric, one can derive the optimum supply
voltage that would yield minimum PDP.
The optimum supply voltage (for minimum PDP)
can be found from the below equation and is given by
3𝑉𝑇
𝑉𝐷𝐷 (𝑂𝑃𝑇) =
3−𝛼
The above expression is valid for long-channel and
deep sub micrometer devices. For long-channel transistors
(α = 2), the optimum supply voltage is equal to 3VT, For
deep sub micrometer devices with α closer to unity the
optimum voltage is expected to be less than 3VT. For
example, if α = 1.5, then VDD (OPT) = 2VT. At any rate,
the optimum value for VDD is proportional to the threshold
voltage. So, the conclusion is that the supply voltage must
be reduced to minimize the PDP. Scaling the supply
voltage below the point of minimum PDP will cause severe
degradation in the delay. The second point is that the
optimum supply voltage is related to the threshold voltage.
Reduction of Switching Activity
Another approach to low-power design is to reduce
the switching activity and the amount of the switched
capacitance to the minimum level required to perform a
given task. Switching activity in CMOS digital integrated
circuits can be reduced by algorithmic optimization and
architecture optimization. Each of these aspects will be
discussed briefly as below.
Algorithmic Optimization
Algorithmic optimization depends heavily on the
application and on the characteristics of the data, such as
the dynamic range, the correlation, and statistics of the data
transmission and so on. Some of the techniques apply only
to applications such as digital Signal Processing (DSP) and
cannot be used for general-purpose processing.
Several architectural techniques have been
proposed to reduce the switching activity, such as, ordering
of the input signals and delay path balancing to remove
glitching. In multi-level logic circuits, the propagation
delay from one logic block to the next can cause spurious
signal transitions or glitches, as a result of critical races or
dynamic hazards occurs.
Reduction of Switched Capacitance
The amount of switched capacitance plays a
significant role in the dynamic power dissipation of the
circuit. Hence, the reduction of this parasitic capacitance is
a major goal for low-power design of digital integrated
circuits. The switching capacitance can be broken down
into two categories, the first category is capacitance in
dense logic (which includes the transistor parasitic and
wire capacitances at the output of the gates) and the second
category is capacitances of the busses and a clock network
(which is mainly the wire capacitance). In some systems,
the capacitance of the busses and a clock network may
comprise close to 50% of the overall chip capacitance. An
example of such system is the Alpha chip.
At the system level, one of the approaches to
reduce the switched capacitance is to limit the use of
shared resources. A simple example is the use of a global
bus structure for the data transmission between a large
numbers of operational modules. The type of logic style
used to implement a digital circuit also affects the physical
capacitance of the circuit. The physical capacitance is a
function of the number of transistors that are required to
implement a given function. For example, one approach to
reduce the physical capacitance is to use transfer gates over
conventional CMOS logic gates to implement logic
functions.
3.2 INTRODUCTION TO FLIP-FLOPS
Latches and flip-flops are the basic elements for
storing information. One latch or flip-flop can store one bit
of information. The main difference between latches and
flip-flops is that for latches, often called level-sensitive
because their outputs are constantly affected by their inputs
as long as the enable signal is asserted. They are
transparent during the entire time when the enable signal is
asserted. Flip-flops, on the other hand, have their content
change only either at the rising or falling edge of the
enable signal. This enable signal is usually the controlling
clock signal. After the rising or falling edge of the clock,
the flip-flop content remains constant even if the input
changes.
D Latch with Enable
The D latch can also have an enable input as shown
in figure 2.2. When the E input is asserted (E = 1), the Q
output follows the D input. In this situation, the latch is
said to be “open” and the path from the input D to the
output Q is “transparent”. Hence the circuit is often
referred to as a transparent latch. When E is de-asserted (E
= 0), the latch is disabled or “closed”, and the Q output
retains its last value independent of the D input. A sample
timing diagram for the operation of the D latch with enable
is shown in figure 3.2(d). Between t0 and t1, the latch is
enabled with E = 1 so the output Q follows the input D.
3
Between t1 and t2, the latch is disabled, so Q remains
stable even when D changes.
Fig 3.2: D latch with enable (a) circuit using NAND gates (b)
truth table(c) logic symbol (d) timing diagram
3.2.1 Flip-Flop Types
There are basically four main types of flip-flops:
SR, D, JK, and T. The major differences in these flip-flop
types are in the number of inputs they have and how they
change state. The flip-flops can be described fully and
uniquely by its logic symbol, characteristic table,
characteristic equation, state diagram, or excitation table,
and are summarized in figure 3.3.
3.2.2 D Flip-Flop
The D flip-flop with positive-edge-triggered is
shown in figure 3.3. Here two D latches are connected in
series and a clock signal Clk is connected to the E input of
the latches, one directly, and one through an inverter. The
first latch is called the master latch. The master latch is
enabled when Clk = 0 and follows the primary input D.
When Clk is a 1, the master latch is disabled but the second
latch, called the slave latch, is enabled so that the output
from the master latch is transferred to the slave latch. The
slave latch is enabled all the while that Clk = 1, but its
content changes only at the beginning of the cycle, that is,
only at the rising edge of the signal because once Clk is 1,
the master latch is disabled and so the input to the slave
latch will not change.
The circuit of figure 3.4(a) is called a positive
edge-triggered flip-flop because the output Q on the slave
latch changes only at the rising edge of the clock. If the
slave latch is enabled when the clock is low, then it is
referred to as a negative edge-triggered flip-flop. The
circuit of figure 3.4(a) is also referred to as a master- slave
D flip-flop because of the two latches used in the circuit.
Figure 3.4(b) and figure 3.4(c) show the truth table and the
logic symbol respectively.
Fig 3.4: Master-slave positive-edge-triggered D flip-flop: (a)
circuit using D latches
(b) truth table (c) logic symbol
The edge triggered flip-flops can be classified into two
types. As given below


Single Edge Triggered Flip-Flop (SETFF)
Double
Edge
Triggered
Flip-Flop
(DETFF)
In SETFF the data is sampled at only one edge
either positive or negative edge, where as in DETFF the
data is sampled at both edges.
Fig 3.3: Flip-Flop types
3.3 SINGLE EDGE TRIGGERED FLIP-FLOP
The figure 3.5 compares the different operations
between a latch and a flip-flop. In figure 3.5(a) a gated D
latch, a positive-edge-triggered D flip-flop and a negativeedge-triggered D flip-flop, all having the same D input and
4
controlled by the same clock signal. Figure 3.5(b) shows
timing diagram of gated D latch, a positive-edge-triggered
D flip-flop and a negative-edge-triggered D flip-flop.
Notice that the gated D latch Qa follows the D
input as long as the clock is high. The positive-edgetriggered flip-flop Qb responds to the D input only at the
rising edge of the clock while the negative-edge-triggered
flip-flop Qc responds to the D input only at the falling edge
of the clock.
appropriate sample is selected for the Q output by a
clocked multiplexer (MUX). Today we need high
performance FFs. The most common approach for
improving the performance is to increase the clock
frequency. However, use of high clock frequency has a
number of disadvantages.
Power consumption of the clock system
dramatically increases and clock uncertainties take
significant part of the clock cycle. Other problems include
degradation of the clock waveform due to the non-ideal
clock distribution, power supply noise and cross-talk. An
alternative clocking strategy relies on the use of storage
elements capable of capturing data on both clock edges
(rising and falling edge). Such storage elements are
referred to as Double-Edge Triggered clocked Storage
Elements (DETSE). In this case, the same data throughput
can be achieved with half of the clock frequency. In other
words double edge clocking can be used to save half of the
power on the clock distribution network. Power dissipation
is directly proportional to the square of the supply voltage
and clock frequency as shown in below equation.
P = α CV2f
Fig 3.5: Comparison of a gated latch, positive-edge-triggered
flip-flop and
negative-edge-triggered flip- flop: (a) circuit
(b) timing diagram
The dynamic power consumption in the clock tree
depends on the frequency, the voltage swing, and the load
of clock tree. If the sampling of the input is performed in
both rising and falling edge of clock (double-edge
triggered), then for same applications and operational
speeds, the frequency of the clock can be half of the clock
frequency of the Single Edge Triggered Flip-Flop.
Double-Edge Triggered Feedback Flip-Flop
(DFFF) has less dynamic power consumption, static
power, and delay compared to the previous flip-flops.
3.4 DOUBLE-EDGE TRIGGERED FEEDBACK FLIPFLOP
In some of the designs DETFF approach is
preferred to reduce power dissipation. Unlike SETFF, data
is captured by both edges of the clock. Implementation of
DETFF is shown in the block diagram in figure 3.6.
Fig 3.6: Block diagram of DETFF
Both positive and negative edges are used to
sample the D input at alternate clock edges, and the
Therefore operating clock frequency is reduced to
half by using double edge clocking and low supply voltage
is applied to decrease power consumption. These are the
most effective ways to reduce power consumption. The
both techniques are applied here to reduce the power
consumption of the proposed DETFF.
There are several ways to implement a DETFF;
such ways can be categorized into two ways. The first idea
is to insert additional circuitry to generate internal pulse
signals on each clock edge. The second idea is to duplicate
the pathway to enable the flip-flop to sample data on every
clock edge.
3.4.1 Power Consumption of DETFF
The power consumption of DETFF is due to three main
components of power dissipation of a flip-flop:

Internal power dissipation of the flip-flop
represents the power consumed by the internal and
input nodes during latching operations, including
the power dissipated driving the output load.

Local clock power dissipation represents the
portion of the power dissipated in the clock buffer
that is driving the clock input of the flip-flop.

Local data power dissipation represents the portion
of the power dissipated in the logic gate that is
driving the data input of the flip-flop.
The clock power dissipation is determined solely
by the clock load of the flip-flop, whereas the distribution
of the internal and data power dissipation is affected by the
structure and operation of the latching element itself as
well as the input switching activity. The sum of these three
components is referred to as the total power (P TOT). All
three components of power require independent estimation
in any comparative analysis because, inherently, a tradeoff
exists between the three. If a comparison is made without
5
taking all three components into account, it may indicate
misleading results.
III.IMPLEMENTATION
TG5, and TG6 of figure 3.1 are replaced with pass
transistors P1, P2, P3 and P4 respectively. The two
inverters I2 and I4 of figure 3.1 are used for two feedback
paths, but here a single feedback inverter I3 is used as a
common feedback inverter for two feedback paths as
shown in figure 3.2.
3.1 EXISTING DETFF DESIGNS
3.1.1 DETFF proposed by M. Pedram et al
The DETFF proposed by M.Pedram, Q.Wu and
X.Wu [12] is shown in figure 4.1. This flip- flop is
basically a Master Slave flip-flop structure and has two
data paths. The upper data path consists of a Single Edge
Triggered flip-flop (SETFF) implemented using
transmission gates. This works on positive edge. The lower
data path consists of a negative edge triggered flip-flop
implemented using transmission gates. Note that two
inverters are inserted in the feedback path to restore the
level in two SETFFs. Besides, all three MUXs are simply
composed of a pair of MOS transistors for reducing
number of transistors. This flip flop has 22 transistors
excluding clock driver. In these 22 transistors, 12
transistors are clocked transistors.
Fig 3.2: Proposed DETFF circuit diagram
Fig 3.1: Circuit diagram of DETFF1
The input data is supplied to one end each of two
transmission gates (TG1, TG2)and the other end of the two
transmission gates (TG1, TG2) is separately connected to
the input of two inverters (I1, I2). The outputs of the two
inverters (I1, I2) are separately connected to the inputs of
another two inverters (I3, I4) via the pass transistors (P1,
P3). The output of inverter I3 goes through two pass
transistors (P2, P4) to connect to one end of the above
mentioned two transmission gates (TG1, TG2) separately,
and the output of the inverter I4 forms the output of the
present invention. The proposed DETFF design shows a
pair of parallel loops as shown in conventional and existing
methods. When the clock pulse changes from low to high,
the upper loop holds data and the down loop samples data.
But when the clock pulse changes from high to low, the
top loop switches to sample data and then the down loop
switches to hold data.
The figure 1 shows a pair of parallel loops. When
the clock pulse changes from low to high, the upper loop
holds data and the down loop samples data. But when the
clock pulse changes from high to low, the top loop
switches to sample data and then the down loop switches
to hold data.
The novelty of the proposed flip flop lies in the
feedback strategy using common feedback inverter and
pass transistors to make the design static. This improves
the power efficiency of our flip flop. This flip flop has 16
transistors excluding clock driver. In these 16 transistors, 8
transistors are clocked transistors.
3.2 PROPOSED DETFF DESIGN
The proposed DETFF design is shown in figure
3.3. This flip-flop is also basically Master Slave flip-flop
structure and it consists of two data paths. The proposed
design is composed of six switches (two transmission gates
and four NMOS pass transistors) and four inverters. The
upper data path consists of transmission gate TG1, pass
transistors (P1, P2) and inverter I1. The lower data path
consists of transmission gate TG2, pass transistors (P3, P4)
and inverter I2. These two data paths use same feedback
inverter I3 and same output inverter I4. The transmission
gate (TG) and pass transistor (P) in both the data paths are
clocked such that the upper data path works as positive
edge triggered flip flop and lower data path works as
negative edge triggered flip flop.
Comparison of number of transistors and number
clocked transistors required for the three FFs is
summarized in Table 3.1.
Specification
No. of
Transistors
(excluding clock
driver)
DETFF
1
DETFF
2
Proposed
DETFF
22
20
16
12
10
8
The proposed design is identical to figure 3.1
except feedback path. The transmission gates TG2, TG3,
6
Table 3.1: Comparison of number of transistors required for the
three FFs
From the Table 4.1 it is clear that the proposed
DETFF design have less number of transistors and also
less number of clocked transistors thus it provides low
power dissipation and increased performance with low
transistor count. Thus the proposed Double Edge Triggered
Flip-Flop (DETFF) has become more efficient in terms of
area, power and speed which claim for better performance
than conventional designs.
IV SIMULATION RESULTS
Fig 4.4: Waveform for average power and delay of
DETFF 2
Fig 4.1: Output waveform of DETFF1
Fig 4.5: Output waveform of proposed DETFF
Fig 4.2: Waveform for average power and delay of
DETFF 1
Fig 4.6: Waveform for average power and delay of
proposed DETFF
4.2 PERFORMANCE COMPARISON
Since D to Q delay depends on when the data
transition occurs, here we measured timing parameter
clock to Q delay. The clock-to-Q delay is the delay from
the active clock input to the new value of the output.
Fig 4.3: Output waveform of DETFF 2
4.2.2 On Variation of Supply Voltages
The nominal power supply voltage for 65nm
technology is 1V. However, for battery operated systems,
the power supply voltage is reduced drastically to lower
the power consumption.Therefore delay, power, and
energy of all the DETFFs are computed as a function of
supply voltage. We simulated the three DETFFs with
different supply voltages ranging from 0.8 volt to 1.2 volt.
7
Table 6.2 shows the comparison of simulation results of
average power dissipation for various flip flops with the
variation of supply voltages.
Table 4.3 shows the comparison of average power
dissipation, delay and PDP of scan registers developed by
DETFF1, DETFF2 and proposed DETFF.
VDD
(V)
DETFF
1 (µW)
DETFF
2 (µW)
Proposed
DETFF
(µW)
Improvement
% Over 1
Improvement
% Over 2
Specification
DE
TFF
1
DE
TFF
2
Prop
osed
DET
FF
Improve
ment %
over 1
Improve
ment %
over 2
0.8
0.954
0.65
0.522
45.28
19.69
0.9
1.168
0.836
0.685
41.35
18.06
Power (µW)
6.41
5
5.21
7
4.51
5
29.62
13.46
1.0
1.471
1.066
0.881
40.11
17.35
Delay (ns)
3.78
0.16
1.813
1.367
1.114
38.55
18.51
3.76
6
0.37
1.1
3.77
2
1.2
2.126
1.796
1.394
34.43
22.38
PDP (10-15J)
24.2
5
19.6
8
17
29.9
13.62
No. of transistors
(Excluding Clock
Driver)
106
98
82
22.64
16.33
Table 4.1: Average power dissipation on variation of supply
voltages
From the Table 4.1 it is clear that the proposed
DET flip-flop has an average improvement of 39.94% and
19.2% in terms of average power dissipation with the
variation of supply voltages when compared with DETFF 1
and DETFF 2 respectively.
Table 4.2 shows the comparison of power-delayproduct (PDP) for various flip flops with the variation of
supply voltages.
VDD
(V)
DETFF DETFF
Proposed
1 (10- 2 (10- DETFF (1018J)
18J)
18J)
Improve
ment %
Over 1
Improve
ment %
Over 2
0.8
37.84
20.81
11.06
70.77
46.85
0.9
36.8
22.09
12.04
67.28
45.5
1.0
38.94
24.37
13.44
65.48
44.85
1.1
41.3
27.85
15.25
63.07
45.24
1.2
43.54
33.32
17.51
59.78
47.45
Table 4.2: PDP on variation of supply voltages
From the Table 6.4 it is clear that the proposed DET flipflop has an average improvement of 65.28% and 45.98% in terms
of PDP with the variation of supply voltages when compared
with DETFF 1 and DETFF 2 respectively. Figure 6.9 shows the
statistical variations of PDP for various flip flops with the
variation of supply voltages.
4.2.3 Scan Registers
A 4-bit scan register is implemented using existing
and as well as proposed DETFFs. We simulated the three
scan registers developed by the three DETFFs. The
performance of the scan register developed by the
proposed DETFF is evaluated by comparing the average
power, delay and power delay product (PDP) with scan
registeres developed by DETFF 1 and DETFF 2.
Table 6.8: Performance comparison of scan registers
From the Table 4.3 it is clear that the proposed
DET flip-flop has an average improvement of 48.58% and
14.54% in terms of average power dissipation with the
variation of clock frequencies when compared with DETFF
1 and DETFF 2 respectively.
V.CONCLUSION AND FUTURE SCOPE
CONCLUSION
The proposed Double-edge-triggered D flip-flop is
a low power, low voltage, high speed and low transistor
count flip-flop designed in 45nm CMOS technology. The
proposed design eliminates one feedback loop by using
common feedback inverter logic thereby reducing the
number of transistors and also by using pass transistors the
number of clocked transistors is also reduced compared to
existing DETFFs. This improves the power efficiency of
the proposed DETFF. The three DET flip-flops are
simulated with different supply voltages ranging from
0.8V to 1.2V and with different clock frequencies ranging
from 400MHz to 2GHz. At nominal condition, the PDP of
the proposed DETFF is improved by 65.48% and 44.85%
over earlier designs DETFF1 and DETFF2 respectively.
Simulation results show that the proposed design has
lowest power dissipation and least delay thereby lowest
PDP than existing designs. Therefore the proposed design
is very well suited for low power and high speed
applications operating at low voltages.
FUTURE SCOPE
The future scope is to use latest CMOS
technologies like 40nm and 22nm to reduce some more
power consumption and dissipation. The transistor sizes
get vary for different technology files. By optimizing the
transistor sizes it is possible to achieve low power and high
performance DETFFs compared to the proposed DETFF.
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REFERENCES
[1]
M. Pedram, Q. Wu, and X. Wu, “A New Design
ofDouble Edge
Triggered Flip-Flops,” Proceeding of the Asia
and South Pacific Design Automation Conference (ASP-DAC), pp.
417–421, 1998.
[2]
Imran Ahmed Khan, Danish Shaikh and MirzaTariq
Beg,“ 2 GHz Low Power Double EdgeTriggered flip-flop in 65nm
CMOS Technology” IEEE Conference, pp 978-1-4673-1318-6/12,
2012.
[3]
Xiaowen Wang, and William H. Robinson, “A LowPower Double Edge-Triggered Flip-Flop with Transmission Gates
and Clock Gating” IEEE Conference , pp 205-208, 2010.
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Hossein Karimiyan Alidash, Sayed Masoud Sayedi and
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Peiyi Zhao, Jason McNeely, Pradeep Golconda and
Jianping Hu, ”Low Power Design of Double-Edge Triggered FlipFlop by Reducing the Number of Clocked Transistors,” IEEE
Conference, 2008.
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Yu Chien-Cheng ,“Design of Low-Power Double EdgeTriggered Flip- Flop Circuit", Second IEEE Conference on
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BIOGRAPHIES
R.Mallikarjuna Reddy ,received her Bachelor Degree in
Electronics & Communication Engineering from Jawaharlal
Nehru Technological University Hyderabad in the year
2004, Master’s Degree in VLSI System Design from
Jawaharlal Nehru Technological University Hyderabad in
the year 2008. Presently working as an Assistant Professor
in ECE Department In GVIC at Madanapalle. Her interested
areas of research are Nano Electronics, VLSI System Design
and Low Power VLSI Design.
Y.Yaswanth Kumar, received his Bachelor Degree in
Electronics and Commuication Engineering from Jawaharlal
Nehru Technological University Anantapur in the year
2011. Currently he is doing his Master’s Degree in VLSI
System Design in Jawaharlal Nehru Technological
University Anantapur. His interested areas are Low Power
VLSI Design, Digital Circuits Design and VLSI Technology
Kuppam N Chandra Sekhar, received her Bachelor
Degree in Electronics & Communication Engineering from
Jawaharlal Nehru Technological University Hyderabad in
the year 2006, Master’s Degree in VLSI System Design
from Jawaharlal Nehru Technological University Hyderabad
in the year 2013. Presently working as an Assistant
Professor in ECE Department In GVIC at Madanapalle. Her
interested areas of research are Communication,VLSI
System Design and Low Power VLSI Design.
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