CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
JAN2016
ASSESSMENT_CODE BCA2050_JAN2016
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
10922
QUESTION_TEXT
Explain multiprocessing in brief. Discuss its advantages and
disadvantages.
SCHEME OF
EVALUATION
Multiprocessing: multiprocessing is concerned with …. same
progress(page 272) (3 mark)
Advantages(page 273)
Three point- Each[1mark]=>(1*3)=[3 marks]
Disadvantages (page 274)
Four points –Each[1 mark}=>(1*4)=[4 marks]
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72890
QUESTION_TEXT
Discuss the read and write cycle of an 8086 processor.
SCHEME OF
EVALUATION
Read cycle is data transfer from memory or input/output to CPU. It
consists of several steps they are: (0.5x10) Marks
1. Processor starts a read bus cycle by floating the address of the
memory location on the address lines.
2. After the address lines are steady, the processor declares the
address strobe signal on the bus. The address strobe signals are
utilized to verify the validity of the address lines.
3. The processor thereafter positions the Read/Write signal to high
i.e. read.
4. Subsequently, the processor declares the data strobe signal. Data
strobe gives signal to the memory that the processor is all set to read
data.
5. The memory subsystem decodes the address and puts the data
on the data lines.
6. The memory subsystem thereafter declares the data acknowledge
signal. Data acknowledge is utilised to signal to the processor that
valid data at this point be latched in.
7. Processor latches in the data and cancels out the data strobe. This
gives signal to the memory that the data has been latched by the
processor.
8. Processor also cancels out the address strobe signal.
9. Memory subsystem now cancels out the data acknowledgement
signal.
10. This acts as a signal to the termination of the read bus cycle.
Write cycle is transfer of data from CPU to memory or Input/Output.
The various steps involved in this are: (0.5x10) Marks
1. Processor starts a write bus cycle by floating the floating the
address of the memory location on the address lines.
2. After the address lines are steady, the processor declares the
address strobe signal on the bus. The address strobe signals are
utilized to verify the validity of the address lines.
3. The processor thereafter positions the Read/Write signal to low
i.e. write.
4. After this the processor puts data on the data lines.
5. At this point, the processor declares the data strobe signal. This
provides signal to the memory that the processor contains valid data
needed for the memory write operation.
6. The memory subsystem decodes the address and wirtes the data
into the addressed memory location.
7. The memory subsystem thereafter declares the data acknowledge
signal. Thus gives signal to the processor that data has been written to
the memory.
8. Then the processor cancels out the data strobe, giving signal that
the data is not valid anymore.
9. Processor also cancels out the address strobe signal.
10. Memory subsystem at this point cancels out the data
acknowledgement signal, giving signal for termination of the write bus
cycle.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72893
QUESTION_TEXT
List the characters of CISC and RISC.
Major characteristics of CISC architecture are
SCHEME OF
EVALUATION

A large number of instructions - typically from 100 to 250
instructions

Some instructions that perform a specialised task and are
used infrequently.

A large variety of addressing modes – typically from 5 to 20
different modes.

Variable length instruction formats.

Instructions that manipulate, operands in memory.
Major Characteristics of RISC architecture are
o
Relatively few instructions.
o
Relatively few addressing modes.
o
Memory access limited to load and store instructions.
o
All operations done within the registers of the CPU.
o
Fixed length, easily decoded instruction format.
o
Single cycle instruction execution.
o
Hard wired rather than micro-programmed control.
Other characteristics attributed to RISC architecture
are:

The relatively large number of registers in the
processor unit.

Use of overlapped register windows to speedup procedure call and return.

Efficient instruction pipeline.

Compiler support for efficient translation of
high level language programs into machine
language programs.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125685
QUESTION_TEXT
Briefly explain the 8086 register set.
General purpose registers –(2mark)
Sagest Registers –(2 mark)
SCHEME OF EVALUATION Pointers & index registers (3 mark)
Flag registers( 1 mark)
Miscellaneous registers (2mark)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125686
QUESTION_TEXT
What is instruction cycle? Explain the various registers utilised in the
CPU cycle and the steps involved in the instruction cycle.
An instruction cycle means the time duration in which a single
instruction is obtained from memory and implemented as soon as a
computer is provided with an instruction in machine language. It is also
called fetch-and-execute cycle. (1 mark)
The various registers utilised in the CPU cycle are:
•
Program counter: This is a special purpose register which is
utilised by the processor to contain the address of the subsequent
instruction to be implemented. As each instruction is implemented, the
PC is automatically incremented. (1 mark)
•
Memory Address Register: The MAR saves the physical memory
address on which the subsequent instruction is placed or the subsequent
piece of data will be written. IT contains the address of a memory block
to be written to or read from. (1 mark)
•
Memory Data Register: MDR is a two way register which
contains data accessed from memory or data awaiting storage in
memory. Hence MDR can stack its data from:
SCHEME OF
EVALUATION
One of the CPU registers
The data bus (1 mark)
•
Instruction Register: IT stores the instruction presently being
executed. (0.5 mark)
•
Control Unit: After choosing machine resources like a specific
arithmetic operation and a data source register, The CU is utilised to
decode the program instruction in the IR. It synchronises the initiation of
those resources. (1 mark)
•
Arithmetic Logic Unit: Works on the logical operations (0.5
mark)
Steps involved in Instruction Cycle are:
•
Fetch the instruction: Fetching the instruction is in the first phase
of an instruction cycle. The subsequent instruction is extracted from the
memory address which is at present stored in the Program Counter as
well as in the Instruction Register. (1 mark)
•
Decode the Instruction: The decoder interprets the instruction
when the instruction has been obtained. In this phase, the instruction
present in the instruction register gets decoded. (1 mark)
•
Read Effective address: When the instruction contains an indirect
address, the actual address is read from the main memory and any
needed data is obtained from main memory and there after positioned in
data registers. (1 mark)
•
Execute the instruction: The control unit of CPU forwards the
decoded information in the form of a sequence of control signals to the
applicable functional units of the CPU to perform the actions needed by
the instruction like reading values from registers, forwarding them to the
ALU to conduct logical or mathematical functions on them as well as
writing the outcome back to a register. (1 mark)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125690
QUESTION_TEXT
Explain instruction execution procedure.
1.
Contents of PC are loaded into MAR and read request is sent to the
main memory. While waiting for the MFC signal PC is incremented by
setting one of the current values in the PC. Mean while carry–in to ALU
is set to 1 and an add operation is specified.
2.
The updated value from the register Z is sent back to PC. This step
can be started immediately after issuing the read request without having
to wait for the MFC signal.
SCHEME OF
EVALUATION
3.
Wait for the MFC signal. Here word fetched from the memory is
loaded into the IR. This completes fetch phase of the operation.
4.
The instruction decoding circuit interprets the contents of IR at the
beginning which enables the control circuitry to choose the appropriate
signals for the remainder of the control sequence. Here address field of
IR, which contains the address NUM, is gated to the MAR and memory
read operation is initiated.
5.
Transfer the content of R0 to register Y and wait for the MFC
signal.
6.
Now the memory operand is available on register MDR. The
addition operation is performed.
7.
The result is transferred to R0. This completes the execution phase
of the operation. The end signal indicates that this is the last step of
current instruction and causes a new fetch cycle to be started going back
to step1.
(Total 10 marks)