CompE 460
Real-Time and Embedded
Systems
Lecture 5 – Memory Technologies
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• Prayer/Thoughts
• The CPU-Memory Interface
• The Memory Subsystem and Technologies
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Volatile Memory
• DRAM
• SDRAM
SRAM
• DDR RAM
•
Non-Volatile Memory
• ROM
• EEPROM
• Flash
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Memory
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What are some different kinds of memory?
Volatile
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SRAM: Static Random Access Memory
DRAM: Dynamic Random Access Memory
SDRAM – Synchronous DRAM
DDR SDAM – Dual data rate ram
RDRAM – Rambus DRAM
VideoRAM – Dual Port RAM
Non-Volatile
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Read Only Memories
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ROM
PROM
EPROM
EEPROM
Flash
MRAM – Magnetic RAM
FRAM – FerroElectric RAM
Phase Change Memory – Based on electrically induced phase change of chalcogenide
materials (has both crystaline and non-crystaline states)
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Cont
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In a PC, what do you
normally use?
• Volatile main memory
• Memory Modules
• Non-Volatile BIOS
•EEPROM/Flash
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MasterComponents
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Memory
Subsystem
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Memory subsystems generally
consist of multiple chips
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Both volatile and non-volatile
And/or multiple chips for each
Depending on system, each chip
provides few bytes (e.g., 14) per
access (like in a PC system), or
each provides all bytes for an
access (like in most embedded
systems)
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•
Bytes from multiple chips are
accessed in parallel to fetch
words
Memory controller
decodes/translates address and
control signals
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Memory
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• Forgets memory when power is turned off
• Usually volatile is much faster than non-volatile memory
• Many types of volatile memory – Usually comes in 2 flavors
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Asynchronous
• SRAM: Static Random Access Memory
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upside: fast and no refresh required
downside: not so dense and not so cheap
often used for caches
• DRAM: Dynamic Random Access Memory
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upside: very dense (1 transistor per bit) and inexpensive
downside: requires refresh and often not the fastest access times
often used for main memories
Synchronous
• SDRAM – Synchronous DRAM – refers to the fact that this DRAM is tied to a
common clock with the uproc, so all data is read/write on a particular clock edge
(either rising or falling)
• DDRAM – Dual data rate ram – data is read/written on each clock edge (both rising
and falling)
Asynch Mem - Static versus
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Dynamic RAM
• What is a D flip-flop?
•
Static RAM uses Flipflops for each storage element
• What is a capacitor
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Dynamic Ram uses capacitors for each storage element
D
CLK
Q
Storage
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• RAM chips don't store whole
bytes, but rather they store
individual bits in a grid, which
you can address one bit at a
time
CPU Async Memory
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Interface
• CPU Asynch Memory Interface usually consists of:
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unidirectional address bus
bidirectional data bus
read control line
write control line
ready control line
size (byte, word) control line
address bus
data bus
CPU
• Memory access involves a memory bus transaction
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read:
(1) set address, read and size,
(2) copy data when ready is set by memory
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write:
(1) set address, data, write and size,
(2) done when ready is set
Read
Write
Ready
size
Memory
Basics title
Contstyle
ClickStorage
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address bus
• Row and Column
decoders are simple 1
of X decoders (from
CompE 224)
• Example:
•
contains 8 16x1bit
decoders
data bus
CPU
Read
Write
Ready
Size
Memory
16x8-bit memory array
0000
0001
1
1
0
0
1
0
1
0
0
0
0
0
1
0
0
1
address 1-of-16
decoder
1111
0 1 0 1 0 0 1 1
D7 D6 D5 D4 D3 D2 D1 D0
SRAM Organization and
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Operations
(a) Address lines/decoders
to select a row and a column
(b) Chip Select
(c) Read/Write enable
(d) Data in/out
SRAM
Memory
Timing
for Read
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to edit
Master
titleAccesses
style
• Address and chip select signals are provided tAA before data is available
tRC
• Outputs reflect new data
tAA
Address
A11-A0 old address
new address
CS
WE
Address Bus
2147H High-Speed 4096x1-bit static RAM
Dout
high
impedance
undef
tACS
Data Valid
tHz
2147H
Dout
A11-A0
DinWE CS
tRC = Read cycle time
tAA = Address access time
tACS = Chip select access time
tHZ = Chip deselections to highZ out
SRAM Memory Timing for Write
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• Address and data must be stable tS time-units before write
t
enable signal falls
t
WC
AA
Address
A11-A0 old address
CS
new address
tS
WE
Din
Address Bus
2147H High-Speed 4096X1-bit static RAM
2147H
Din
A11-A0
DinWE CS
old data
new data
tACS
tHz
tS = Signal setup time
tRC = Read cycle time
tAA = Address access time
tACS = Chip select access time
tHZ = Chip deselections to highZ out
DRAMtoOrganization
and title
Operations
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(a) Address lines/decoders
to select a row and a column
(b) Chip Select (not shown)
(c) Read/Write enable
(d) Data in/out
(e) Refresh counters
DRAM
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Master Access
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• DRAM Memory is arranged in a XY grid pattern of rows and
columns (like SRAM)
• First, the row address is sent to the memory chip and latched,
then the column address is sent in a similar fashion
• This row and column-addressing scheme (called multiplexing)
allows a large memory address to use fewer pins
•
BF533 uses this for DRAM memory maps
• The charge stored in the chosen memory cell is amplified
using the sense amplifier and then routed to the output pin
• Read/Write is controlled using the read/write logic
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How
DRAM
Works
Memory
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• ROM – Read Only Memory – come from factory programmed
• PROM – Programmable ROM – one time use – programmed
with programmer
• EPROM – Erasable PROM – can use multiple times – need
special eraser to reuse them
• EEPROM – Electrically erasable PROM – Typically slow
reading/writing – Can be used “in circuit” – generally small
memory footprints
• Flash – Have to write a block of data – writing is slow, reading
fast – will wear out after ~10k to 100k writes
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Memory
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Flash to
Technology
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• This is an 8 Mbit, 3.0
volt-only Flash
memory organized as
1,048,576 bytes or
524,288 words.
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Flash
• Two cautions for flash memory
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Flash is usually spec’d as Mb not MB
Reading from flash is same as RAM
Writing to flash requires a sector write
Backup
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DRAM
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Performance
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Specs
style
• Important DRAM Performance Considerations
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Random access time: time required to read any random single cell
Fast Page Cycle time: time required for page mode access read/write
to memory location on the most recentlyaccessed page (no need to
repeat RAS in this case)
Extended Data Out (EDO): allows setup of next address while current
data access is maintained
SDRAM Burst Mode: Synchronous DRAMs use a selfincrementing
counter and a mode register to determine the column address sequence
after the first memory location accessed on a page effective for
applications that usually require streams of data from one or more
pages on the DRAM
Required refresh rate: minimum rate of refreshes