EEL-6167 VLSI DESIGN
SPRING 2004 TERM PROJECT
Mirror Circuits: Design and Simulation
Craig Chin
Miguel Alonso Jr.
Overview
 The theory behind mirror-circuit logic design is
introduced.
 The method and tools involved in the simulation
and layout of the various logic circuits are
discussed.
 The simulation circuits, the circuit layouts, and the
simulation results are presented.
 Observations pertaining to the design process and
the simulation results are discussed.
Introduction
 Mirror circuits are based on series-parallel configurations of
MOSFETs.
 A mirror circuit has the same transistor topology for the
nFETs and the pFETs (refer to Figure 1).
 NAND2, NOR2, EXOR2, or EXNOR2 logic gates can be
constructed using the same mirror circuit structure.
 The different functionalities are implemented by varying the
inputs at each gate.
 Only one general layout is necessary.
 This simplifies the layout process.
Introduction
V CC
V CC
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
IN
0
0
Figure 1- Mirror Circuit for (a) Inverter and (b) Generic two input logic gate
Introduction
 The rise times and fall times of the EXOR and EXNOR
mirror circuit gates are shorter than their AOI counterparts.
 However, the rise times and fall times the mirror circuit
AND and NOR gates are slightly longer (see Table 1).
Introduction
Table 1- Rise Times and Fall times of Mirror Circuits vs. Conventional Circuits
Gate
Mirror
MODEL
Conventional
t r  R p C p  2 R p C out
t r  R p C out
t f  R n C n  R n C out
t
t r  R p C p  R p C out
t r  2 R p Co u t
t f  RnC n  2 RnC o u t
t
NAND
NOR
f
f


2 R
R
n
n
C
C
out
out
Method
 The circuits to be explored were designed using Orcad’s
PSPICE for the circuit simulation, and the LASI utility for
designing the physical layout.
 www.mosis.org, provides information on design rules for
various processes, along with the scalable CMOS (SCMOS)
design rule set.
 A scalable CMOS (SCMOS) design rule set is based on
reference measurement lambda (λ), which has units in
microns.
 All of the dimensions in the layout are written in the form
Value = mλ
 The layer maps used are shown in Figures 2 and 3.
Method
Figure 2- Layer Map for SCMOS
Method
Figure 3- Layer Map for SCMOS (cont'd)
Method
 LASI is available free from http://members.aol.com/lasicad
 This tool combines the layout process with PSPICE, giving a very
accurate representation of the physical model using SPICE.
 It auto-routes layouts, calculates parasitic capacitances, and provides
circuit files for use during SPICE simulation.
 It has the capability of performing design rule checks for a set of design
rules.
 ORCAD simulations provides the advantage of the hierarchical circuit
structures, where design takes place using sub-circuits.
 The Taiwan Semiconductor Manufacturing Corporation (TSMC) was
chosen to be the process, because their process parameters were the only
ones available on the Mosis website.
Method
 With the process parameters already defined, in order to
provide an accurate model for simulation, the length and
width of the NFET and PFET were specified to be:
Ln = 0.7um, Wn = 1.4um, Lp = 0.7um, Wp = 3.5um
 The (W/L) ratio for the NFET is 2 and for the PFET is 5, in
order to maintain the device trans-conductance’s the same.
 These values, in addition to the SPICE model parameters,
are used for performing the circuit simulations for the
Inverter, NAND, NOR, EXOR, and the D Flip Flop.
Circuit Diagrams and Layouts
Figure 4-NMOS FET Layout
Figure 5- PMOS FET Layout
Circuit Diagrams and Layouts
VCC
M4
MbreakpD
VCC
5V
0
V1 = 0V
V2 = 5V
TD = 0
TR = 0.01n
TF = 0.01n
PW = 0.005u
PER = 0.01u
V1
M3
MbreaknD
0
0
Figure 4 – Inverter Circuit Diagram
Figure 5 – Inverter Layout
Circuit Diagrams and Layouts
VCC
VCC
M3
5Vdc
M1
Va
Va
Vb
0
MbreakpD
V1 = 0V
V2 = 5V
TD = 0
TR = 0.01n
TF = 0.01n
PW = 0.5u
PER = 1u
MbreakPD
M4
V1
M2
Va
Vb
MbreakPD
MbreakPD
0
M7
M5
Vb
Va
Va
MbreakND
V1 = 0V
V2 = 5V
TD = 0
TR = 0.01n
TF = 0.01n
PW = 1u
PER = 2u
MbreaknD
M8
V2
M6
Vb
Vb
MbreakND
MbreakND
0
0
Figure 6 – NAND2 Circuit Diagram
Figure 7 – NAND2 Layout
Circuit Diagrams and Layouts
U2
Din
1
2
D
ENABLE
U5
Q
/Q
3
1
4
N/A
Dlatch
1
X
ENABLE
Q
/Q
Dlatch
U3
Clock
2
D
U4
Y
2
1
X
Y
2
Din
Not
V1 = 0V
V2 = 5V
TD = 0
TR = 0.01n
TF = 0.01n
PW = 1u
PER = 2u
Not
V1
0
Clock
V1 = 5V
V2 = 0V
TD = 0
TR = 0.01n
TF = 0.01n
PW = 0.5u
PER = 1u
V2
0
Figure 8 – Edge-Triggered D Flip-Flop Circuit Diagram
3
4
Q
/Q
Circuit Diagrams and Layouts
nand1
nand3
D
Va1
Vc1
Va3
Vb1
Vc3
Q
5V
Vb3
SCHEMATIC3
M4
SCHEMATIC5
0
ENABLE
MbreakpD
X
Y
M3
nand4
nand2
not1
Vc4
Vc2
Vx1 Vy 1
MbreaknD
Va4
Va2
/Q
Vb4
Vb2
0
SCHEMATIC6
SCHEMATIC7
SCHEMATIC4
Figure 9 – D Latch Sub-circuit
Diagram
Figure 10 – Inverter Sub-circuit
Diagram
Circuit Diagrams and Layouts
Figure 11 – Edge-Triggered D Flip-Flop Layout
Results of Simulation
5.0V
0V
SEL>>
-3.0V
V(M4:d)
5.0V
2.5V
0V
0s
0.2us
V(V1:+)
0.4us
0.6us
0.8us
1.0us
1.2us
1.4us
1.6us
1.8us
2.0us
Time
Figure 12 – Inverter Simulation at 1MHz
5.0V
2.5V
0V
-2.5V
V(M4:d)
5.0V
2.5V
SEL>>
0V
0s
2ns
4ns
6ns
8ns
10ns
12ns
14ns
16ns
18ns
20ns
V(M3:g)
Time
Figure 13 – Inverter Simulation at 10MHz
Results of Simulation
5.0V
2.5V
0V
-2.5V
V(M4:d)
5.0V
2.5V
SEL>>
0V
0s
2ns
4ns
6ns
8ns
10ns
12ns
14ns
16ns
18ns
20ns
V(M3:g)
Time
Figure 14 – Inverter Simulation at 100MHz
Results of Simulation
10V
5V
SEL>>
-3V
V(M4:d)
5.0V
2.5V
0V
V(VB)
5.0V
2.5V
0V
0s
0.5us
1.0us
1.5us
2.0us
2.5us
3.0us
3.5us
4.0us
V(VA)
Time
Figure 15 – NAND2 Simulation at 1MHz
10V
5V
0V
V(M4:d)
5.0V
2.5V
SEL>>
0V
V(VB)
5.0V
2.5V
0V
0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(VA)
Time
Figure 16 – NAND2 Simulation at 10MHz
Results of Simulation
10V
5V
0V
V(M4:d)
5.0V
2.5V
SEL>>
0V
V(VB)
5.0V
2.5V
0V
0s
5ns
10ns
15ns
20ns
25ns
30ns
35ns
40ns
V(VA)
Time
Figure 17 – NAND2 Simulation at 100MHz
Results of Simulation
5.0V
2.5V
0V
V(Q)
5.0V
2.5V
0V
V(DIN)
5.0V
2.5V
SEL>>
0V
0s
0.5us
1.0us
1.5us
2.0us
2.5us
3.0us
3.5us
4.0us
V(CLOCK)
Time
Figure 18 – Edge-Triggered D Flip-Flop Simulation at 1MHz Clock
5.0V
2.5V
0V
V(Q)
5.0V
2.5V
SEL>>
0V
V(DIN)
5.0V
2.5V
0V
0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(CLOCK)
Time
Figure 19 – Edge-Triggered D Flip-Flop Simulation at 10MHz Clock
Results of Simulation
5.0V
2.5V
0V
V(Q)
5.0V
2.5V
SEL>>
0V
V(DIN)
5.0V
2.5V
0V
0s
5ns
10ns
15ns
20ns
25ns
30ns
35ns
40ns
V(CLOCK)
Time
Figure 20 – Edge-Triggered D Flip-Flop Simulation at 100MHz Clock
Results of Simulation
 At 100 MHz





The rise time for the inverter was .24 ns
The fall time for the inverter was 0.04 ns
The propagation delay for the D Flip Flop was
2.72 ns
The rise time for the D Flip Flop was 2.02 ns
The fall time for the D Flip Flop was 0.916 ns
Discussion
 Mirror Circuits were investigated using the various
tools
 The advantage of using mirror circuits comes in the
layout process
 Mirror circuits do, however, experience changes in
the rise and fall times when compared to their
minimal realization counter parts
 This is evident from the simulation plots
Conclusion
 In general, in order to improve the performance of
the various circuits



Select a better process that allows for smaller geometries
Since the SCMOS design convention was used, there is
no need to redesign the layouts, it is simply a matter of
rescaling them
Perhaps, if the above does not improve performance, the
placement of the various sub-cells can be improved to
minimize metalization paths