Week 6: Sequential Logic
Lab 14-2: D type (p335)
Read pages 320-331 on sequential logic in the lab manual.
Answer the following questions in your report:
1) Hook up the circuit of figure L14.2 with D (pin 2) input driven by your slider
switches from last week (with pull-up resistors). For the CLK (pin 3), use your
“debounced” switch from last week. Remember to tie the unused inputs to
ground (pins 10 to 13; pin 8&9 are the other outputs).
2) Confirm that the D flip-flop ignores the level at its D input except when it sees a
rising clock edge. Sketch the clock and Q output waveforms you observe on the
scope during a rising clock edge.
3) Describe what happens when you assert the RESET* input (i.e., ground it, since it
is "active low").
4) What happens if you assert RESET* and SET* at the same time? Check both
outputs (Q and Q*) and figure out what determines their final state.
5) Add the feedback loop in circuit figure L14.3. First clock the circuit manually
using the “de-bounced” switch. Then, clock the D-type flip-flop with the squarewave of 0-5V at 1kHz signal via the 220 Ohm resistor into the CLK input.
a. Sketch the clock and Q waveforms you see on a scope when you drive the
clock with a 0-5V square wave at 1 kHz (you may need to use the
RUN/STOP function). How does the output (Q) frequency compare with
the input clock frequency?
6) Increase the clock frequency and measure the flip-flop's "propagation delay".
Does it depend on the clock frequency?
Lab 14-3: J-K type (p336)
Answer the following questions in your report:
1) Hook up the circuit figure L14.4 and fill in its truth table.
2) Add the inverter to build circuit figure L14.5 (hint: use a NAND gate as a
inverter, and remember to power your NAND chip). Fill in this circuit's truth
table.
3) Connect the J and K pins directly to build circuit figure L14.6 and fill in this
circuit's truth table.
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Lab 14-4: J-K in counters – Ripple and synchronous counter
(p338)
Answer the following questions in your report:
1) Build the 2-bit ripple counter circuit figure L14.7, with the output bits (Q0 and
Q1) driving a pair of LEDs that are ON for a high logic level.
2) Drive the first JK's clock input with a few Hertz 0-5V square wave and describe
the output.
3) Increase the clock frequency enough to observe the "ripple" delay between the
updates of Q0 and Q1 on each clock cycle. Sketch the clock, Q0 and Q1
waveforms to illustrate this effect, showing your measured delays.
4) Modify your circuit to build the "synchronous" counter of figure L14.8, and
confirm that the "ripple" delay is now gone. Make a similar sketch that shows
this.
Lab 14-6: Shift register (p340)
Answer the following questions in your report:
1) Build the shift register circuit figure L14.12 using a single 74HC175 chip, which
contains 4 D flip flops that share a common clock (pin 9) and active-low clear
(pin 1) inputs. Drive the clock input with a 0-5V 1KHz square wave and connect
the first flip-flop's D input (the "IN" signal) to a slider switch that you can toggle
manually. Hook up LEDs to indicate the logic levels of the Q0, Q1, Q2, Q3 signals
(the outputs of each flip flop in the chain).
2) Sketch the IN and Q0 waveforms you observe on the scope when changing the IN
value (and triggering on IN). Notice that the delay between changes at IN and Q0
is slightly different each time: this effect is called "jitter". The jitter refers to the
shifting of the clock edge relative to its expected position due to noise and
therefore can be viewed as an uncertainty in the clock edge. How big is the jitter?
How could you reduce it?
Note: To visual the jitter on your scope, you should set the persistency of the
display function to infinite. This function allows you to visual superposition of
outputs using the same t0.
3) Make a timing diagram that shows IN, Q0, Q1, Q2, Q3 for 16 consecutive high-low
cycles of IN.
4) Add the two NAND gates to build circuit figure L14.13. Set the clock rate to 0.5
Hertz and watch what happens after one rising edge of the first D input (the
"TRIG" signal). Make a timing diagram of the TRIG, Q0, Q1, Q2, Q3, OUT-A and
OUT-B signals that shows the full sequence. There is a partially filled in timing
diagram on the bottom of p.341 for your reference. (Hint: video the circuit with
your phone, as well as monitoring the D and the outputs with the scope).
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5) Describe why this digital circuit is sometimes called a "one-shot" (also referred
as monostable multivibrator). Notice that this circuit has a built-in time constant,
similar to an RC analog circuit.
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