Lec 4-2
Five operations of the machine cycle
Fetch- fetch the next program instruction
from memory. (PC+1); instruction to IR
Decode- decode the instruction stored in the IR.
Fetch- fetch the operand to the registers
Execute- process the command.
Store – write the results of the instruction
into main memory.
Instruction Cycle
Two steps:
* Fetch
* Execute
Fetch Cycle
• Program Counter (PC) holds address of next
instruction to fetch
• Processor fetches instruction from memory
location pointed to by PC
• Increment PC
– Unless told otherwise
• Instruction loaded into Instruction Register
(IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
– data transfer between CPU and main memory
• Processor I/O
– Data transfer between CPU and I/O module
• Data processing
– Some arithmetic or logical operation on data
• Control
– Alteration of sequence of operations
– e.g. jump
• Combination of above
• Example 1:
Describe the sequence of events carried out
during the machine cycle when executing the
following instructions.
Address Contents
500
LDA 1000
501
ADD 1001
502
STO 1002
503
JMP 510
1000
4
1001
6
1002
• Instruction #1
LDA 1000 – Load to the accumulator the
contents of the memory location 1000.
500
501
LDA 1000
502
ADD 1001
1000
STO 1002
:
:
1001
4
R
500
MAR 1000
Address
bus
PC
6
JMP 510
:
:
1002
LDA 1000
4
MM
:
:
1003
W
LDA
4 1000
500
501
ACC
503
MDR
IR
Data
bus
TMP
Decode
CPU
• Instruction #2
ADD 1001 – add the contents of location
1001 and the contents of the accumulator
and store the result back in the accumulator.
500
501
LDA 1000
502
ADD 1001
1000
STO 1002
:
:
1001
4
R
MAR
Address
bus
CPU
:
:
1002
ADD61001
501
502
ACC
6
JMP 510
MM
:
:
1003
W
1001
501
PC
503
ADD 1001
4
6
MDR
IR
Data
bus
TMP
Decode
Add
10
• Instruction #3
STO 1002 – store the contents of the
accumulator to the memory location 1002.
500
501
LDA 1000
502
ADD 1001
1000
STO 1002
:
:
1001
4
R
MAR
Address
bus
PC
503
1002
502
502
503
ACC 10
6
JMP 510
:
:
1002
MM
:
:
10
1003
W
STO
101002
STO 1002
MDR
IR
Data
bus
TMP
Decode
CPU
• Instruction #4
JMP 510 – Jump to memory location 510
500
501
LDA 1000
502
ADD 1001
1000
STO 1002
:
:
1001
4
R
MAR
Address
bus
PC
503
503
510
504
ACC
503
JMP 510
:
:
1002
6
10
MM
:
:
1003
W
JMP 510
JMP 510
MDR
IR
Data
bus
TMP
Decode
CPU
• Example 2:
Describe the sequence of events carried out during
the machine cycle when executing the following
instructions.
Address
Contents
100
JMP 200
200
MOV R1 R2
201
STO 800 R1
Move the contents of
register R2 to R1.
Store the contents of R1
in memory location 800.
Example 3:
Address Contents
100
JMP 200
200
LDA 1000
201
Comments
202
MPY 1001 Multiply the contents of the
Accumulator with the contents of the
memory location 1001 and store the
result back in the Accumulator.
STO 1002
1000
5
1001
10