Uses of Synchronized Clocks in Test
and Measurement Systems
Jeff Burch, Adam Cataldo, John Eidson, Andrew Fernandez,
Conrad Proft, Dieter Vook
Measurement Research Laboratory, Agilent Technologies, Inc.
CHESS
March 3, 2009
Agenda
1. Overview of clock synchronization and driving applications
2. Test & measurement (LXI Class B instrumentation & DAQ)
3. Experimental results
4. Conclusions
CHESS
Slide 2
March 3, 2009
Purpose of IEEE 1588
IEEE 1588 is a protocol designed to synchronize real-time
clocks in the nodes of a distributed system that communicate
using a network
• It does not say how to use these clocks (this is specified by the respective
application areas)
NETWORK
CHESS
Slide 3
March 3, 2009
Coupling IEEE 1588 to your application
generating timestamps
trigger-in
timestamp
Latch
IEEE 1588 Clock
event time
generating events
Latch
Comparator
trigger-out
IEEE 1588 Clock
generating waveforms
IEEE 1588 Clock
Synthesizer
waveform
CHESS
Slide 4
March 3, 2009
Synchronization Basics – Delay
Request-Response Mechanism
Master
time
t-ms
Slave
time
t1
Timestamps known
by slave
Sync
t 2 t2
Follow_Up
t1 , t2
t 3 t1 , t2 , t3
Delay_Req
t-sm
t4
Delay_Resp
t1 , t2 , t3 , t4
Grandmaster- M
S- BC - M
S- OC
CHESS
Slide 5
March 3, 2009
Synchronization Basics – Delay
Request-Response Mechanism - 2
Under the assumption that the link is symmetric
Offset = (Slave time) – (Master time) = [(t2 – t1) – (t4 – t3)]/2 = [(t-ms) – (t-sm)]/2
(propagation time) = [(t2 – t1) + (t4 – t3)]/2 = [(t-ms) + (t-sm)]/2
Can rewrite the offset as
Offset = t2 – t1 – (propagation time) = (t-ms) – (propagation time)
If the link is not symmetric
• The propagation time computed as above is the mean of the master-toslave and slave-to- master propagation times
• The offset is in error by the difference between the actual master-toslave and mean propagation times
CHESS
Slide 6
March 3, 2009
Synchronization Basics –
Peer Delay Mechanism
t-ms
Master
time
t1
Slave
time Timestamps known
by slave
Sync
t2 t 2
Follow_Up
t 1 , t2
Pdelay_Req
t-sm
t3 t 3
t4
t5
Pdelay_Resp
Pdelay_Resp_Follow_Up
t6
t6
t3, t4, t5, t6
Grandmaster- M
S- BC - M
S- OC
CHESS
Slide 7
March 3, 2009
IEEE 1588
MASTER
Application IEEE 1588 Timing Support
(e.g. time stamping, time triggers…)
SLAVE
Application Code
T1
IEEE 1588 Clock
Sync
T2
IEEE 1588
Code
IEEE 1588
Control
T3
OS
T4
Delay_Req
MAC
MII
IEEE 1588 Packet Detection
PHY
LAN
CHESS
Slide 8
March 3, 2009
End-to-End Transparent Clocks
The residence time is accumulated in a field of the Sync
(one-step clock) or Follow_Up (two-step clock) messages
Message at ingress
PTP message
payload
Correction field
Message at egress
PTP message
payload
Network
protocol Preamble
headers
Correction field
Network
protocol Preamble
headers
++
Ingress timestamp
Ingress
-+
Egress timestamp
Residence time bridge
Egress
CHESS
Slide 9
March 3, 2009
How well can you synchronize?
From: “DP83640 Synchronous Ethernet Mode: Achieving Sub-nanosecond Accuracy
in PTP Applications, National Semiconductor Application Note 1730, David Miller,
September 2007
SyncE
Enabled
Measured
Quantity
Mean
Standard
Deviation
Peak-to-peak
No
10 MHz clock
output
-2.148 ns
5.237 ns
48.3 ns
Yes
10 MHz clock
output
319 ps
80.6 ps
900 ps
Yes
1 pulse per
second output
1.005 ns
2.8 ps
2.02 ns
CHESS
Slide 10
March 3, 2009
Products (partial listing)
Infrastructure:
• Boundary and transparent clocks (IEEE 1588 bridges): Hirschmann,
Westermo, Cisco, others
• GPS master clocks: Symmetricom, Meinberg, Westermo,…
Silicon:
• Microprocessors with embedded 1588: Intel, Hyperstone, Freescale,
AMCC,…
• PHY/MAC level: National Semiconductor, others in proto or 1st silicon
(some also implement synchronous Ethernet)
Protocol & misc:
• 1588 stacks, IP blocks, consulting: IXXAT, U. Zurich, MoreThanIP, others
• Wireshark
CHESS
Slide 11
March 3, 2009
Websites
General IEEE 1588 site: contains product pointers,
conference records, general guidance, standards related
http://ieee1588.nist.gov/
ISPCS (International IEEE Symposium on Precision Clock
Synchronization) site: Conference on IEEE 1588 and
related subjects
http://www.ispcs.org/
CHESS
Slide 12
March 3, 2009
RoboTeam in Action: Process Relative Motion
Courtesy of Kuka Robotics
Corp.
CHESS
Slide 13
March 3, 2009
e.g. high speed printing
Courtesy of Bosch-Rexroth.
CHESS
Slide 14
March 3, 2009
IEEE 1588 enabled flight test instrumentation in the forward
fuselage of a test aircraft. (Data acquisition)
Courtesy of Teletronics
CHESS
Slide 15
March 3, 2009
Power System Applications
(Courtesy of General Electric)
GE uses 1588 in the Mark™ Vie control system for large generators,
turbines, wind farms, and other DCS applications. (>50K I/O Packs with
1588 shipped to date)
http://gepower.com/prod_serv/products/oc/en/control_solution/ppc_markviedcs_cs.h
tm
CHESS
Slide 16
March 3, 2009
Power System Applications
IEEE Power System Relaying Committee (PSRC) recently approved formation
of Working Group H7 "IEEE 1588 Profile for Protection Applications"
CHESS
Slide 17
March 3, 2009
Telecommunications Applications
Cellular backhaul is the major telecom application to date. MetroEthernet in field trial. Femtocells beginning.
Companies involved (partial list):
• Nokia-Siemens, Brilliant, Semtech, Zarlink, …
CHESS
Slide 18
March 3, 2009
Audio/video systems applications
Consumer electronics: IEEE 802.1as
http://www.ieee802.org/1/pages/802.1as.html
The “AVB” effort should be carefully investigated by both PTIDES and PRET.
CHESS
Slide 19
March 3, 2009
LXI Class A&B Instrument Overview
LXI Class
Class-C
A
B Instrument
Instrument
Instrument
LAN
TCP HTTP
Meas FW
PHY
UDP SCPI
TX
RX
P2P
Meas HW
DUT
TT TS
App Code Event Log
IEEE1588
8 LVDS
LXI Class B
• IEEE1588 Clock Sync
• Peer-to-Peer Messages
• Event Logs
• Downloaded Application Code
Trigger Bus
LXI Class A
• Trigger Bus
CHESS
Slide 20
March 3, 2009
LXI Class A&B benefits
Class B:
•
Increased visibility of system configuration, timing and
performance
•
Increased visibility for fault diagnosis and trouble shooting
•
Ability to precisely time measurement execution and state
evolution system-wide
•
Increased ability to optimize system performance, e.g.
throughput, timing precision
•
Increased ability to do cross domain measurement
correlations based on precisely time stamped data
Class A:
•
Increased traditional triggering flexibility: 8-wide, daisy chain
CHESS
Slide 21
March 3, 2009
DEMO TIME!
CHESS
Slide 22
March 3, 2009
LXI Class B experimental test system
Experiments:
1. Frequency response
2. Fault shutdown
Test system block diagram
CHESS
Slide 23
March 3, 2009
LXI Class B experimental test system
CHESS
Slide 24
March 3, 2009
PC Paced Instrument Sequencing-frequency response
*TRG; *OPC?
HW Trigger
DONE
*TRG; *OPC?
HW Trigger
DONE
CHESS
Slide 25
March 3, 2009
Instrument Sequencing by PC (Baseline)
Irregular signal timing due
to timing jitter in PC
CHESS
Slide 26
March 3, 2009
Peer-to-Peer Instrument Sequencing
MEASURE
STEP
MEASURE
STEP
COMPLETE
CHESS
Slide 27
March 3, 2009
Instrument Sequencing by P2P Messages
More regular signal timing
CHESS
Slide 28
March 3, 2009
LXI Class B: Time-Triggered Instrument Sequencing
TT
TT
TT
TT
Time overlap
TT
TT
TT
COMPLETE
TT
CHESS
Slide 29
March 3, 2009
Instrument Sequencing by Time-Triggers
Shorter interval due to overlap
CHESS
Slide 30
March 3, 2009
Sequencing to measure frequency response
CHESS
Slide 31
March 3, 2009
Power Supply Shutdown
PC Polled
POLL
FAULT
SHUTDOWN
FAULT
P2P Immediate
SHUTDOWN
TS
SHUTDOWN
FAULT
P2P Timed
TT = TS + Δ1
SHUTDOWN
TS
TT = TS + Δ2
SHUTDOWN
CHESS
Slide 32
March 3, 2009
PC polled
1. Short PS load
2. PS shuts off
3. Turn off FG
4. Turn off DMM
Asynchronous Fault
TT-Fault FET
Protect
PS-Volt
Shutdown
FG-out
DMM-off
Shutdown
CHESS
Slide 33
March 3, 2009
Time-Triggered Emergency Shutdown
Asynchronous Fault
Protect
Shutdown
Δ1
Δ2
Shutdown
CHESS
Slide 34
March 3, 2009
Power Shutdown performance
CHESS
Slide 35
March 3, 2009
Power Shutdown Event Log-based Analysis
PS
FGEN
DMM
Common Time Scale
CHESS
Slide 36
March 3, 2009
Conclusions:
Benefits of Class A & B:
•
Increased visibility of system configuration, timing and
performance
•
Increased visibility for fault diagnosis and trouble shooting
•
Ability to precisely time measurement execution and state
evolution system-wide
•
Increased ability to optimize system performance, e.g.
throughput, timing precision
•
Increased ability to do cross domain measurement
correlations based on precisely time stamped data
•
Increased traditional triggering flexibility: 8-wide, daisy chain
Performance measurements illustrate these benefits.
CHESS
Slide 37
March 3, 2009