The 8051
Assembly Language
Overview
•
•
•
•
•
Introduction
Addressing modes
Data processing (arithmetic and logic)
Data transfer instructions
Program flow instructions
Introduction
• As a typical 8-bit processor , 8051 instructions
have 8-bit opcodes.
• This provides a possibility of 2^8=256
instructions.
– 255 are implemented and 1 is undefined
• 139-1byte instructions
• 92-2byte instructions,
• 24 -3byte instructions
Instructions by opcode
0x01
0x02
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
NOP
AJMP LJMP RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
0x10
JBC
ACALL LCALL RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
0x20
JB
AJMP RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
0x30
JNB
ACALL RETI
RLC
ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC
0x40
JC
AJMP ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
0x50
JNC
ACALL ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
0x60
JZ
AJMP XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
0x70
JNZ
ACALL ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
0x80
SJMP AJMP ANL
MOVC DIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
0x90
MOV
ACALL MOV
MOVC SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB
0xa0
ORL
AJMP MOV
INC
MUL
?
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
0xb0
ANL
ACALL CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
0xc0
PUSH AJMP CLR
CLR
SWAP XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
0xd0
POP
SETB
DA
DJNZ
XCHD XCHD DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
0xe0
MOVX AJMP MOVX MOVX CLR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
0xf0
MOVX ACALL MOVX MOVX CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
0x00
0x00
0x03
ACALL SETB
0x04
Addressing modes
• When instruction operate on data, the question arises: “where is
the data?”
• The answer to this question lies in the 8051 addressing modes.
• There are several possible addressing modes and there are several
possible answers to the question such as in:
–
–
–
–
“byte 2 of the instruction”,
“in register R4”,
“in direct address 25H”,
“in external data memory at the address contained in the data
pointer”
• Addressing modes are an integral part of each computer’s
instruction set.
• They allow specifying the source or destination of data in different
ways depending on the programming situation
8 addressing modes
•
•
•
•
•
•
•
•
Register
Direct
Indirect
Immediate
Indexed
Relative
Absolute
Long
Immediate Addressing
• When a source operand is a constant rather than a
variable, the instruction uses a value known at
assemble time, then the content can be incorporated
into the instruction as a byte or immediate data.
• An additional instruction byte contains the value
• In assembly language , immediate operands are
preceded by a number sign, #
Immediate Mode
– specify data by its value
mov A, #0
;put 0 in the accumulator
;A = 00000000
mov R4, #11h
;put 11hex in the R4 register
;R4 = 00010001
mov B, #11
;put 11 decimal in b register
;B = 00001011
mov DPTR,#7521h
;put 7521 hex in DPTR
;DPTR = 0111010100100001
; All instructions using immediate addressing use an
8bit data constant for the immediate data, except
when initializing the data pointer , 16bit constant
is required
Register Addressing
• 8051 has 8 working registers numbers R0 to R7
• Instruction are encoded using the three least
significant bits of the instruction opcode to indicate a
register within this logical address space.
• Thus a function code and operand address can be
combined to form a 1 byte instruction
Register Addressing
– either source or destination is one of CPU register
MOV R0,A
MOV
ADD
ADD
MOV
MOV
MOV
A,R7
A,R4
A,R7
DPTR,#25F5H
R5,DPL
R,DPH
Note that MOV R4,R7 is incorrect
Direct Addressing
• There are 128 bytes of RAM in the 8051.
• The RAM has been assigned addresses 00 to 7FH.
– 1. RAM locations 00 - 1 FH are assigned to the register banks and
stack.
– 2. RAM locations 20 - 2FH are set aside as bit-addressable space to
save single bit data.
– 3. RAM locations 30 - 7FH are available as a place to save byte-sized
data.
Direct addressing mode
• It is most often used to access RAM locations
30H - 7FH.
• This is due to the fact that register bank
locations are accessed by the register names
of R0 - R7.
• There is no such name for other RAM
locations so must use direct addressing.
Direct addressing mode
• In the direct addressing mode, the data is in a
RAM memory location whose address is
known, and this address is given as a part of
the instruction.
Direct addressing mode
– specify data by its 8-bit address, Usually for 30h-7Fh
of RAM
Mov
Mov
Mov
Mov
a, 70h
R0,40h
56h,a
0D0h,a
;
;
;
;
copy contents of RAM at 70h to a
copy contents of RAM at 70h to a
put contents of a at 56h to a
put contents of a into PSW
Direct addressing mode
– play with R0-R7 by direct address
MOV A,4

MOV A,R4
MOV A,7

MOV A,R7
MOV 7,2

MOV R7,R6
MOV R2,#5
MOV R2,5
;Put 5 in R2
;Put content of RAM at 5 in R2
Register indirect addressing mode
• A register is used as a pointer to the data.
• If the data is inside the CPU, only registers R0 and R 1 are
used for this purpose.
• R2 - R7 cannot be used to hold the address of an operand
located in RAM when using indirect addressing mode.
• When RO and R 1 are used as pointers they must be
preceded by the @ sign.
Register indirect addressing mode
Advantage of register indirect addressing mode
• One of the advantages of register indirect
addressing mode is that it makes accessing
data dynamic rather than static as in the case
of direct addressing mode.
• Looping is not possible in direct addressing
mode.
• This is the main difference between the
direct and register indirect addressing modes.
Advantage of register indirect addressing mode
Limitation of register indirect addressing mode in
the 8051
• R0 and R1 are the only registers that can be used for pointers
in register indirect addressing mode.
• Since R0 and R l are 8 bits wide, their use is limited to
accessing any information in the internal RAM (scratch pad
memory of 30H - 7FH, or SFR).
• To access data stored in external RAM or in the code space
of on-chip ROM, we need a 16-bit pointer, the DPTR.
Register indirect Addressing Modes
– the address of the source or destination is specified in registers
and Uses registers R0 or R1 for 8-bit address:
mov psw, #0
mov r0, #0x3C
mov @r0, #3
; use register bank 0
; memory at 3C gets #3
; M[3C]  3
Uses DPTR register for 16-bit addresses:
mov dptr, #0x9000
movx a, @dptr
; dptr  9000h
; a  M[9000]
Note that 9000 is an address in external memory
Indexed addressing mode and on-chip
ROM access
• Indexed addressing used a base register (either the program counter or
the data pointer and an offset (the accumulator) in forming the effective
address for JMP or MOVC instruction.
• Indexed addressing mode is widely used in accessing data elements of
look-up table entries located in the program ROM space of the 8051.
• The instruction used for this purpose is :
MOVC A, @ A+DPTR
• The 16-bit register DPTR and register A are used to form the address of
the data element stored in on-chip ROM.
• Because the data elements are stored in the program (code) space ROM
of the 8051, the instruction MOVC is used instead of MOV. The "C"
means code.
• In this instruction the contents of A are added to the 16-bit register DPTR
to form the 16bit address of the needed data.
Indexed addressing mode and MOVX instruction
• The 8051 has another 64K bytes of memory space set aside exclusively
for data storage.
• This data memory space is referred to as external memory and it is
accessed by the MOVX instruction.
• The 8051 has a total of 128K bytes of memory space since 64K bytes of
code added to 64K bytes of data space gives us 128K bytes.
• One major difference between the code space and data space is that,
unlike code space, the data space cannot be shared between code and
data.
Register Indexed Addressing
Modes
– source or destination address is the sum of
the base address and the accumulator(Index)
• Base address can be DPTR or PC
mov dptr, #4000h
mov a, #5
movc a, @a + dptr
;a  M[4005]
Register indexed Addressing
Modes
•
Base address can be DPTR or PC
ORG 1000h
1000
1002
1003
mov a, #5
movc a, @a + PC
Nop
;a  M[1008]
PC
•
MOVC only can read internal code memory
Acc Register
• A register can be accessed by direct and register mode
• This 3 instruction has same function with different code
0703 E500
0705 8500E0
0708 8500E0
mov a,00h
mov acc,00h
mov 0e0h,00h
• Also this 3 instruction
070B E9
070C 89E0
070E 89E0
mov a,r1
mov acc,r1
mov 0e0h,r1
SFRs Address
• B – always direct mode - except in MUL & DIV
0703 8500F0
0706 8500F0
0709 858CF0
070B 858CF0
mov b,00h
mov 0f0h,00h
mov b,r4
mov 0f0h,r4
• P0~P3 – are direct address
0704 85F580
0706 85F580
0708 859080
mov p0,a
mov 80h,a
mov p0,p1
• Also other SFRs (pcon, tmod, psw,….)
SFRs Address
All SFRs such as (ACC, B, PCON, TMOD, PSW,
P0~P3, …)
are accessible by name and direct address
But all of them Must be coded as direct
address
Data Transfer Instructions
• MOV dest, source
• Stack instructions
PUSH byte
POP byte
dest  source
;increment stack
;move byte
;move from stack
;decrement
pointer,
on stack
to byte,
stack pointer
• Exchange instructions
XCH a, byte
XCHD a, byte
;exchange accumulator and byte
;exchange low nibbles of
;accumulator and byte
8051 Instruction Format
• Register addressing
Op code
070D
070E
070F
0710
0711
0712
0713
0714
0715
0716
0717
E8
E9
EA
ED
EF
2F
F8
F9
FA
FD
FD
n n n
mov
mov
mov
mov
mov
add
mov
mov
mov
mov
mov
a,r0
a,r1
a,r2
a,r5
a,r7
a,r7
r0,a
r1,a
r2,a
r5,a
r5,a
;E8
;E9
;EA
;ED
;Ef
=
=
=
=
=
1110
1110
1110
1110
1110
1000
1001
1010
1101
1111
Stacks
pop
push
stack pointer
stack
Go do the stack exercise…..
Stack
• Stack-oriented data transfer
– Only one operand (direct addressing)
– SP is other operand – register indirect - implied
• Direct addressing mode must be used in Push and Pop
mov sp, #0x40
push 0x55
pop b
;
;
;
;
Initialize SP
SP  SP+1, M[SP]  M[55]
M[41]  M[55]
b  M[55]
Note: can only specify RAM or SFRs (direct mode) to push or pop. Therefore,
to push/pop the accumulator, must use acc, not a
Exchange Instructions
two way data transfer
XCH a, 30h
XCH a, R0
XCH a, @R0
XCHD a, R0
a[7..4] a[3..0]
; a  M[30]
; a  R0
; a  M[R0]
; exchange “digit”
R0[7..4] R0[3..0]
Only 4 bits exchanged
Bit-Oriented Data Transfer
• transfers between individual bits.
• Carry flag (C) (bit 7 in the PSW) is used as a single-bit
accumulator
• RAM bits in addresses 20-2F are bit addressable
mov C, P0.0
mov C, 67h
mov C, 2ch.7
SFRs that are Bit Addressable
SFRs with addresses
ending in 0 or 8 are bitaddressable.
(80, 88, 90, 98, etc)
Notice that all 4 parallel
I/O ports are bit
addressable.
Data Processing Instructions
Arithmetic Instructions
Logic Instructions
Arithmetic Instructions
•
•
•
•
•
•
•
Add
Subtract
Increment
Decrement
Multiply
Divide
Decimal adjust
Arithmetic Instructions
Mnemonic
Description
ADD A, byte
add A to byte, put result in A
ADDC A, byte
add with carry
SUBB A, byte
subtract with borrow
INC A
increment A
INC byte
increment byte in memory
INC DPTR
increment data pointer
DEC A
decrement accumulator
DEC byte
decrement byte
MUL AB
multiply accumulator by b register
DIV AB
divide accumulator by b register
DA A
decimal adjust the accumulator
ADD Instructions
add a, byte
; a  a + byte
addc a, byte
; a  a + byte + C
These instructions affect 3 bits in PSW:
C = 1 if result of add is greater than FF
if the unsigned summed value of the Accumulator, operand and (in the case of ADDC) the
Carry flag exceeds 255 Carry is set. Otherwise, the Carry bit is cleared.
AC = 1 if there is a carry out of bit 3
if the unsigned summed value of the low nibble of the Accumulator, operand and (in the
case of ADDC) the Carry flag exceeds 15 the Auxillary Carry flag is set. Otherwise, the
Auxillary Carry flag is cleared.
OV = 1 if there is a carry out of bit 7, but not from bit 6, or visa versa.
if there is a carry-out of bit 6 or out of bit 7, but not both. if the addition of the
Accumulator, operand and (in the case of ADDC) the Carry flag treated as signed values results in a value
that is out of the range of a signed byte (-128 through +127) the Overflow flag is set. Otherwise, the
Overflow flag is cleared.
Instructions that Affect PSW bits
ADD Examples
• What is the value of the C,
AC, OV flags after the
second instruction is
executed?
mov a, #3Fh
add a, #D3h
0011 1111
1101 0011
0001 0010
C = 1
AC = 1
OV = 0
Signed Addition and Overflow
2’s
0000
…
0111
1000
…
1111
complement:
0000 00 0
1111
0000
1111
7F 127
80 -128
FF -1
0111 1111 (positive 127)
0111 0011 (positive 115)
1111 0010 (overflow
cannot represent 242 in 8
bits 2’s complement)
1000 1111
1101 0011
0110 0010
(negative 113)
(negative 45)
(overflow)
0011 1111 (positive)
1101 0011 (negative)
0001 0010 (never overflows)
Addition Example
; Computes Z = X + Y
; Adds values at locations 78h and 79h and puts them in 7Ah
;-----------------------------------------------------------------X
equ
78h
Y
equ
79h
Z
equ
7Ah
;----------------------------------------------------------------org 00h
ljmp Main
;----------------------------------------------------------------org 100h
Main:
mov a, X
add a, Y
mov Z, a
end
Subtract
SUBB A, byte
subtract with borrow
Example:
SUBB A, #0x4F
;A  A – 4F – C
Notice that
There is no subtraction WITHOUT borrow.
Therefore, if a subtraction without borrow is desired,
it is necessary to clear the C flag.
Example:
Clr c
SUBB A, #0x4F
;A  A – 4F
Increment and Decrement
INC A
increment A
INC byte
increment byte in memory
INC DPTR
increment data pointer
DEC A
decrement accumulator
DEC byte
decrement byte
• The increment and decrement instructions do NOT affect the C flag.
• Notice we can only INCREMENT the data pointer, not decrement.
Multiply
When multiplying two 8-bit numbers, the size of the maximum
product is 16-bits
FF x FF = FE01
(255 x 255 = 65025)
MUL AB
Note : B gets the High byte
A gets the Low byte
; BA

A * B
Division
• Integer Division
DIV AB
; divide A by B
A  Quotient(A/B)
B  Remainder(A/B)
OV - used to indicate a divide by zero condition.
C – set to zero
Decimal Adjust
DA a
; decimal adjust a
Used to facilitate BCD addition.
Adds “6” to either high or low nibble after an addition
to create a valid BCD number.
Example:
mov a, #23h
mov b, #29h
add a, b
DA a
; a  23h + 29h = 4Ch (wanted 52)
; a  a + 6 = 52
Logic Instructions
 Bitwise logic operations

(AND, OR, XOR, NOT)
 Clear
 Rotate
 Swap
Logic instructions do NOT affect the flags in PSW
Bitwise Logic
ANL  AND
ORL  OR
XRL  XOR
Examples:
ANL
00001111
10101100
00001100
ORL
00001111
10101100
10101111
XRL
00001111
10101100
10100011
CPL
10101100
01010011
CPL  Complement
Address Modes with Logic
ANL – AND
ORL – OR
XRL – eXclusive oR
a, byte
direct, reg. indirect, reg,
immediate
byte, a
direct
byte, #constant
CPL – Complement
a
ex:
cpl a
Uses of Logic Instructions
• Force individual bits low, without affecting other bits.
anl PSW, #0xE7
;PSW AND 11100111
• Force individual bits high.
orl PSW, #0x18
;PSW OR 00011000
• Complement individual bits
xrl P1, #0x40
;P1 XRL 01000000
Other Logic Instructions
CLR RL
–
RLC –
RR
–
RRC –
Carry
SWAP –
clear
rotate
rotate
rotate
rotate
left
left through Carry
right
right through
swap accumulator nibbles
CLR ( Set all bits to 0)
CLR A
CLR byte
CLR Ri
CLR @Ri
(direct mode)
(register mode)
(register indirect mode)
Rotate
• Rotate instructions operate only on a
RL a
Mov a,#0xF0
RR a
; a 11110000
; a 11100001
RR a
Mov a,#0xF0
RR a
; a 11110000
; a 01111000
Rotate through Carry
RRC a
C
The right-most bit (bit
0) of the Accumulator
is loaded into the Carry
Flag, and the original
Carry Flag is loaded
into bit 7. This function
can be used to quickly
divide a byte by 2.
mov a, #0A9h
add a, #14h
; a  A9
; a  BD (10111101), C0
rrc a
; a  01011110, C1
RLC a
C
mov a, #3ch
setb c
; a  3ch(00111100)
; c  1
rlc a
; a  01111001, C1
The left-most bit (bit
7) of the Accumulator
is loaded into the
Carry Flag, and the
original Carry Flag is
loaded into bit 0 of
the Accumulator. This
function can be used
to quickly multiply a
byte by 2.
Rotate and Multiplication/Division
• Note that a shift left is the same as multiplying
by 2, shift right is divide by 2
mov
clr
rlc
rlc
rrc
a, #3
C
a
a
a
;
;
;
;
;
A
C
A
A
A
00000011
0
00000110
00001100
00000110
(3)
(6)
(12)
(6)
Swap
SWAP a
SWAP swaps bits 0-3 of the Accumulator with
bits 4-7 of the Accumulator. This instruction is
identical to executing "RR A" or "RL A" four
times.
mov a, #72h
swap a
; a  27h
; a  27h
Bit Logic Operations
• Some logic operations can be used with single bit operands
ANL C, bit
ORL C, bit
CLR C
CLR bit
CPL C
CPL bit
SETB C
SETB bit
• “bit” can be any of the bit-addressable RAM locations or SFRs.
Program Flow Control
• Unconditional jumps (“go to”)
• Conditional jumps
• Call and return
Unconditional Jumps
• SJMP <rel addr>
;
Short jump,
relative address is 8-bit 2’s complement number,
so jump can be up to 127 locations forward, or 128
locations back.
• LJMP <address 16> ;
• AJMP <address 11> ;
Long jump
Absolute jump to
anywhere within 2K block of program memory
• JMP @A + DPTR
indexed jump
;
Long
Infinite Loops
SJMP jumps unconditionally to the address
specified reladdr. Reladdr must be within -128
or +127 bytes of the instruction that follows
the SJMP instruction.
Start: mov C, p3.7
mov p1.6, C
sjmp Start
Microcontroller application programs are almost always infinite loops!
This is because we want the program to
continue to run as long as power is applied to
the chip.
Re-locatable Code
Memory specific NOT Re-locatable (machine code)
org 8000h
Start: mov C, p1.6
mov p3.7, C
ljmp Start
end
LJMP jumps unconditionally to the
specified code addr.
Re-locatable (machine code)
org 8000h
Start: mov C, p1.6
mov p3.7, C
sjmp Start
end
SJMP jumps unconditionally to the address
specified reladdr. Reladdr must be within -128
or +127 bytes of the instruction that follows
the SJMP instruction.
If equal skip the next instruction works
wherever those three instructions are (the if
skip, the one being skipped and the one after
the skip).
Jump table
Mov dptr,#jump_table
Mov a,#index_number
Rl a
Jmp @a+dptr
...
Jump_table: ajmp case0
ajmp case1
ajmp case2
ajmp case3
Conditional Jump
• These instructions cause a jump to occur only if a condition
is true. Otherwise, program execution continues with the
next instruction.
loop: mov a, P1
jz loop
; if a=0, goto loop,
; else goto next instruction
mov b, a
• There is no zero flag (z)
• Content of A checked for zero on time
Conditional jumps
Mnemonic
Description
JZ <rel addr>
Jump if a = 0
JNZ <rel addr>
Jump if a != 0
JC <rel addr>
Jump if C = 1
JNC <rel addr>
Jump if C != 1
JB <bit>, <rel addr>
Jump if bit = 1
JNB <bit>,<rel addr>
Jump if bit != 1
JBC <bir>, <rel addr>
Jump if bit =1,
bit
&clear
CJNE A, direct, <rel addr> Compare A and memory,
jump if not equal
Next Time
Loops
Subroutines
Timers
Example: Conditional Jumps
if (a = 0) is true
send a 0 to LED
else
send a 1 to LED
jz led_off
Setb P1.6
sjmp skipover
led_off: clr P1.6
mov A, P0
skipover:
More Conditional Jumps
Mnemonic
Description
CJNE A, #data <rel addr>
Compare A and data, jump
if not equal
CJNE Rn, #data <rel addr>
Compare Rn and data,
jump if not equal
CJNE @Rn, #data <rel addr> Compare Rn and memory,
jump if not equal
DJNZ Rn, <rel addr>
Decrement Rn and then
jump if not zero
DJNZ direct, <rel addr>
Decrement memory and
then jump if not zero
Iterative Loops
For A = 0 to 4 do
{…}
clr a
loop: ...
...
inc a
cjne a, #4, loop
For A = 4 to 0 do
{…}
mov R0, #4
loop: ...
...
djnz R0, loop
Iterative Loops(examples)
mov a,#50h
mov b,#00h
cjne a,#50h,next
mov b,#01h
next: nop
end
mov a,#0aah
mov b,#10h
Back1:mov r6,#50
Back2:cpl a
djnz r6,back2
djnz b,back1
end
mov a,#25h
mov r0,#10h
mov r2,#5
Again: mov @ro,a
inc r0
djnz r2,again
end
mov a,#0h
mov r4,#12h
Back: add a,#05
djnz r4,back
mov r5,a
end
Call and Return
• Call is similar to a jump, but
– Call pushes PC on stack before branching
acall <address ll>
lcall <address 16>
; stack  PC
; PC  address 11 bit
; stack  PC
; PC  address 16 bit
Return
• Return is also similar to a jump, but
– Return instruction pops PC from stack to get
address to jump to
ret
; PC  stack
Subroutines
call to the subroutine
Main:
sublabel:
...
acall sublabel
...
...
...
...
the subroutine
ret
Initializing Stack Pointer
• SP is initialized to 07 after reset.(Same address as R7)
• With each push operation 1st , pc is increased
• When using subroutines, the stack will be used to store the PC, so it is very
important to initialize the stack pointer. Location 2Fh is often used.
mov SP, #2Fh
Subroutine - Example
square:
push b
mov b,a
mul ab
pop b
ret
• 8 byte and 11 machine cycle
square: inc a
movc a,@a+pc
ret
table: db 0,1,4,9,16,25,36,49,64,81
• 13 byte and 5 machine cycle
Subroutine – another example
; Program to compute square root of value on Port 3
; (bits 3-0) and output on Port 1.
org 0
ljmp Main
Main:
loop:
sqrt:
Sqrs:
mov P3, #0xFF
mov a, P3
anl a, #0x0F
lcall sqrt
mov P1, a
sjmp loop
reset service
; Port 3 is an input
; Clear bits 7..4 of A
inc a
movc a, @a + PC
ret
db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3
end
main program
subroutine
data
Why Subroutines?
• Subroutines allow us to have "structured"
assembly language programs.
• This is useful for breaking a large design into
manageable parts.
• It saves code space when subroutines can be
called many times in the same program.
example of delay
mov a,#0aah
Back1:mov p0,a
lcall delay1
cpl a
sjmp back1
Delay1:mov r0,#0ffh;1cycle
Here: djnz r0,here ;2cycle
ret
;2cycle
end
Delay=1+255*2+2=513 cycle
Delay2:
mov r6,#0ffh
back1: mov r7,#0ffh ;1cycle
Here: djnz r7,here ;2cycle
djnz r6,back1;2cycle
ret
;2cycle
end
Delay=1+(1+255*2+2)*255+2
=130818 machine cycle
Long delay Example
GREEN_LED:
Main:
Again:
Delay:
Loop1:
Loop0:
equ P1.6
org ooh
ljmp Main
reset service
org 100h
clr
GREEN_LED
acall Delay
cpl
GREEN_LED
sjmp Again
main program
mov
mov
mov
djnz
djnz
djnz
ret
END
R7,
R6,
R5,
R5,
R6,
R7,
#02
#00h
#00h
$
Loop0
Loop1
subroutine
Example
; Move string from code memory to RAM
org 0
mov dptr,#string
mov r0,#10h
Loop1:
clr a
movc a,@a+dptr
jz stop
mov @r0,a
inc dptr
inc r0
sjmp loop1
Stop:
sjmp stop
; on-chip code memory used for string
org 18h
String:
db ‘this is a string’,0
end
Example
; p0:input
back:
Again:
request
p1:output
mov a,#0ffh
mov p0,a
mov a,p0
mov p1,a
sjmp back
setb p1.2
mov a,#45h
;data
jnb p1.2,again ;wait for data
mov p0,a
setb p2.3
clr p2.3
;enable strobe
Example
; duty cycle 50%
back: cpl p1.2
acall delay
sjmp back
back:
setb p1.2
acall delay
Clr p1.2
acall delay
sjmp back
Example
; duty cycle 66%
back: setb p1.2
acall delay
acall delay
Clr p1.2
acall delay
sjmp back
8051 timer
Interrupts
Program Execution
…
mov a, #2
mov b, #16
mul ab
mov R0, a
mov R1, b
mov a, #12
mov b, #20
mul ab
add a, R0
mov R0, a
mov a, R1
addc a, b
mov R1, a
end
interrupt
ISR: inc r7
mov a,r7
jnz NEXT
cpl P1.6
NEXT: reti
return
Interrupt Sources
• Original 8051 has 5 sources of interrupts
–
–
–
–
–
Timer 0 overflow
Timer 1 overflow
External Interrupt 0
External Interrupt 1
Serial Port events (buffer full, buffer empty, etc)
• Enhanced version has 22 sources
– More timers, programmable counter array, ADC, more external
interrupts, another serial port (UART)
Interrupt Process
If interrupt event occurs AND interrupt flag for that event is
enabled, AND interrupts are enabled, then:
1. Current PC is pushed on stack.
2. Program execution continues at the interrupt vector
address for that interrupt.
3. When a RETI instruction is encountered, the PC is popped
from the stack and program execution resumes where it left
off.
Interrupt Priorities
• What if two interrupt sources interrupt at the
same time?
• The interrupt with the highest PRIORITY gets
serviced first.
• All interrupts have a default priority order.
• Priority can also be set to “high” or “low”.
Interrupt SFRs
Interrupt enables for the 5 original 8051 interrupts:
Timer 2
Serial (UART0)
Timer 1
Global Interrupt Enable –
External 1
must be set to 1 for any
Timer 0
1
=
Enable
interrupt to be enabled
External 0
0 = Disable
Interrupt Vectors
Each interrupt has a specific place in code memory where program
execution (interrupt service routine) begins.
External Interrupt 0:
Timer 0 overflow:
External Interrupt 1:
Timer 1 overflow:
Serial :
Timer 2 overflow(8052+)
0003h
000Bh
0013h
001Bh
0023h
002bh
Note: that there are
only 8 memory
locations between
vectors.
Interrupt Vectors
To avoid overlapping Interrupt Service routines, it is common to
put JUMP instructions at the vector address. This is similar to
the reset vector.
org 009B
ljmp EX7ISR
cseg at 0x100
Main: ...
...
EX7ISR:...
...
reti
; at EX7 vector
; at Main program
; Main program
; Interrupt service routine
; Can go after main program
; and subroutines.
Example Interrupt Service Routine
;EX7 ISR to blink the LED 5 times.
;Modifies R0, R5-R7, bank 3.
;----------------------------------------------------
ISRBLK:
Loop2:
Loop1:
Loop0:
push PSW
mov PSW,#18h
mov R0, #10
mov R7, #02h
mov R6, #00h
mov R5, #00h
djnz R5, $
djnz R6, Loop0
djnz R7, Loop1
cpl P1.6
djnz R0, Loop2
pop PSW
reti
;save state of status word
;select register bank 3
;initialize counter
;delay a while
;complement LED value
;go on then off 10 times